h8_adc, h8_port: convert i/o to devcb at cpu level

src/devices/cpu/h8/gt913.cpp

@@ -54,7 +54,7 @@ void gt913_device::map(address_map &map)
 	/* ctk530 writes here to latch LED matrix data, which generates an active high strobe on pin 99 (PLE/P16)
 	   there's otherwise no external address decoding (or the usual read/write strobes) used for the LED latches.
 	   just treat as a 16-bit write-only port for now */
-	map(0xe000, 0xe001).lw16(NAME([this](uint16_t data) { m_io.write_word(h8_device::PORT_4, data); }));
+	map(0xe000, 0xe001).lw16(NAME([this](uint16_t data) { do_write_port(h8_device::PORT_4, data); }));
 
 	map(0xfac0, 0xffbf).ram();
 

src/devices/cpu/h8/gt913.h

@@ -27,6 +27,15 @@ public:
 
 	virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto write_port4() { return m_write_port[PORT_4].bind(); }
+
 	void uart_rate_w(uint8_t data);
 	void uart_control_w(offs_t offset, uint8_t data);
 	uint8_t uart_control_r(offs_t offset);

src/devices/cpu/h8/h8.cpp

@@ -19,6 +19,9 @@ h8_device::h8_device(const machine_config &mconfig, device_type type, const char
 	cpu_device(mconfig, type, tag, owner, clock),
 	m_program_config("program", ENDIANNESS_BIG, 16, 16, 0, map_delegate),
 	m_io_config("io", ENDIANNESS_BIG, 16, 16, -1),
+	m_read_adc{ *this, *this, *this, *this, *this, *this, *this, *this },
+	m_read_port{ *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this },
+	m_write_port{ *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this },
 	m_PPC(0), m_NPC(0), m_PC(0), m_PIR(0), m_EXR(0), m_CCR(0), m_MAC(0), m_MACF(0),
 	m_TMP1(0), m_TMP2(0), m_TMPR(0), m_inst_state(0), m_inst_substate(0), m_icount(0), m_bcount(0), m_irq_vector(0), m_taken_irq_vector(0), m_irq_level(0), m_taken_irq_level(0), m_irq_required(false), m_irq_nmi(false)
 {
@@ -30,6 +33,32 @@ h8_device::h8_device(const machine_config &mconfig, device_type type, const char
 	m_mac_saturating = false;
 	m_has_trace = false;
 	m_has_hc = true;
+
+	for(int i=0; i != 8; i++)
+		m_read_adc[i].bind().set([this, i]() { return adc_default(i); });
+	for(int i=0; i != PORT_COUNT; i++) {
+		m_read_port[i].bind().set([this, i]() { return port_default_r(i); });
+		m_write_port[i].bind().set([this, i](u8 data) { port_default_w(i, data); });
+	}
+}
+
+u16 h8_device::adc_default(int adc)
+{
+	logerror("read of un-hooked adc %d\n", adc);
+	return 0;
+}
+
+const char h8_device::port_names[] = "123456789abcdefg";
+
+u8 h8_device::port_default_r(int port)
+{
+	logerror("read of un-hooked port %c\n", port_names[port]);
+	return 0;
+}
+
+void h8_device::port_default_w(int port, u8 data)
+{
+	logerror("write of un-hooked port %c %02x\n", port_names[port], data);
 }
 
 void h8_device::device_config_complete()
@@ -44,6 +73,13 @@ void h8_device::device_start()
 	space(AS_PROGRAM).specific(m_program);
 	space(AS_IO).specific(m_io);
 
+	for(auto &r : m_read_adc)
+		r.resolve();
+	for(auto &r : m_read_port)
+		r.resolve();
+	for(auto &w : m_write_port)
+		w.resolve();
+
 	uint32_t pcmask = m_mode_advanced ? 0xffffff : 0xffff;
 	state_add<uint32_t>(H8_PC, "PC",
 		[this]() { return m_NPC; },

src/devices/cpu/h8/h8.h

@@ -21,38 +21,6 @@ struct h8_dtc_state;
 
 class h8_device : public cpu_device {
 public:
-	enum {
-		// digital I/O ports
-		// ports 4-B are valid on 16-bit H8/3xx, ports 1-9 on 8-bit H8/3xx
-		// H8S/2394 has 12 ports named 1-6 and A-G
-		PORT_1,  // 0
-		PORT_2,  // 1
-		PORT_3,  // 2
-		PORT_4,  // 3
-		PORT_5,  // 4
-		PORT_6,  // 5
-		PORT_7,  // 6
-		PORT_8,  // 7
-		PORT_9,  // 8
-		PORT_A,  // 9
-		PORT_B,  // A
-		PORT_C,  // B
-		PORT_D,  // C
-		PORT_E,  // D
-		PORT_F,  // E
-		PORT_G,  // F
-
-		// analog inputs
-		ADC_0,
-		ADC_1,
-		ADC_2,
-		ADC_3,
-		ADC_4,
-		ADC_5,
-		ADC_6,
-		ADC_7
-	};
-
 	enum {
 		STATE_RESET              = 0x10000,
 		STATE_IRQ                = 0x10001,
@@ -63,6 +31,8 @@ public:
 		STATE_DTC_WRITEBACK      = 0x10006
 	};
 
+	auto read_adc(int port) { return m_read_adc[port].bind(); }
+
 	void internal_update();
 	void set_irq(int irq_vector, int irq_level, bool irq_nmi);
 	bool trigger_dma(int vector);
@@ -72,7 +42,36 @@ public:
 	void request_state(int state);
 	bool access_is_dma() const { return m_inst_state == STATE_DMA || m_inst_state == STATE_DTC; }
 
+	u16 do_read_adc(int port) { return m_read_adc[port](); }
+	u8 do_read_port(int port) { return m_read_port[port](); }
+	void do_write_port(int port, u8 data) { return m_write_port[port](data); }
+
 protected:
+	enum {
+		// digital I/O ports
+		// ports 4-B are valid on 16-bit H8/3xx, ports 1-9 on 8-bit H8/3xx
+		// H8S/2394 has 12 ports named 1-6 and A-G
+		PORT_1,
+		PORT_2,
+		PORT_3,
+		PORT_4,
+		PORT_5,
+		PORT_6,
+		PORT_7,
+		PORT_8,
+		PORT_9,
+		PORT_A,
+		PORT_B,
+		PORT_C,
+		PORT_D,
+		PORT_E,
+		PORT_F,
+		PORT_G,
+		PORT_COUNT
+	};
+
+	static const char port_names[];
+
 	enum {
 		F_I  = 0x80,
 		F_UI = 0x40,
@@ -118,6 +117,10 @@ protected:
 	memory_access<32, 1, 0, ENDIANNESS_BIG>::cache m_cache;
 	memory_access<32, 1, 0, ENDIANNESS_BIG>::specific m_program;
 	memory_access<16, 1, -1, ENDIANNESS_BIG>::specific m_io;
+	std::array<devcb_read16, 8> m_read_adc;
+	std::array<devcb_read8, PORT_COUNT> m_read_port;
+	std::array<devcb_write8, PORT_COUNT> m_write_port;
+
 	h8gen_dma_device *m_dma_device;
 	h8_dtc_device *m_dtc_device;
 	h8_dma_state *m_dma_channel[8];
@@ -169,6 +172,9 @@ protected:
 	void prefetch_done_noirq();
 	void prefetch_done_noirq_notrace();
 	void illegal();
+	u16 adc_default(int adc);
+	u8 port_default_r(int port);
+	void port_default_w(int port, u8 data);
 
 	uint8_t do_addx8(uint8_t a, uint8_t b);
 	uint8_t do_subx8(uint8_t a, uint8_t b);

src/devices/cpu/h8/h83002.h

@@ -32,6 +32,20 @@ public:
 	auto tend0() { return m_tend_cb[0].bind(); }
 	auto tend1() { return m_tend_cb[1].bind(); }
 
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto write_port4() { return m_write_port[PORT_4].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_port7()  { return m_read_port [PORT_7].bind(); }
+	auto read_port8()  { return m_read_port [PORT_8].bind(); }
+	auto write_port8() { return m_write_port[PORT_8].bind(); }
+	auto read_port9()  { return m_read_port [PORT_9].bind(); }
+	auto write_port9() { return m_write_port[PORT_9].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+
 	void set_mode_a20() { m_mode_a20 = true; }
 	void set_mode_a24() { m_mode_a20 = false; }
 

src/devices/cpu/h8/h83003.h

@@ -34,6 +34,24 @@ public:
 	auto tend2() { return m_tend_cb[2].bind(); }
 	auto tend3() { return m_tend_cb[3].bind(); }
 
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto write_port4() { return m_write_port[PORT_4].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_port7()  { return m_read_port [PORT_7].bind(); }
+	auto read_port8()  { return m_read_port [PORT_8].bind(); }
+	auto write_port8() { return m_write_port[PORT_8].bind(); }
+	auto read_port9()  { return m_read_port [PORT_9].bind(); }
+	auto write_port9() { return m_write_port[PORT_9].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+	auto read_portc()  { return m_read_port [PORT_C].bind(); }
+	auto write_portc() { return m_write_port[PORT_C].bind(); }
+
 	void set_mode_a20() { m_mode_a20 = true; }
 	void set_mode_a24() { m_mode_a20 = false; }
 

src/devices/cpu/h8/h83006.h

@@ -29,6 +29,20 @@ class h83006_device : public h8h_device {
 public:
 	h83006_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto write_port4() { return m_write_port[PORT_4].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_port7()  { return m_read_port [PORT_7].bind(); }
+	auto read_port8()  { return m_read_port [PORT_8].bind(); }
+	auto write_port8() { return m_write_port[PORT_8].bind(); }
+	auto read_port9()  { return m_read_port [PORT_9].bind(); }
+	auto write_port9() { return m_write_port[PORT_9].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+
 	void set_mode_a20() { m_mode_a20 = true; }
 	void set_mode_a24() { m_mode_a20 = false; }
 

src/devices/cpu/h8/h83008.h

@@ -29,6 +29,20 @@ class h83008_device : public h8h_device {
 public:
 	h83008_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto write_port4() { return m_write_port[PORT_4].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_port7()  { return m_read_port [PORT_7].bind(); }
+	auto read_port8()  { return m_read_port [PORT_8].bind(); }
+	auto write_port8() { return m_write_port[PORT_8].bind(); }
+	auto read_port9()  { return m_read_port [PORT_9].bind(); }
+	auto write_port9() { return m_write_port[PORT_9].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+
 	void set_mode_a20() { m_mode_a20 = true; }
 	void set_mode_a24() { m_mode_a20 = false; }
 

src/devices/cpu/h8/h83032.h

@@ -31,6 +31,26 @@ class h83032_device : public h8h_device {
 public:
 	h83032_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_port7()  { return m_read_port [PORT_7].bind(); }
+	auto read_port8()  { return m_read_port [PORT_8].bind(); }
+	auto write_port8() { return m_write_port[PORT_8].bind(); }
+	auto read_port9()  { return m_read_port [PORT_9].bind(); }
+	auto write_port9() { return m_write_port[PORT_9].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+
 	uint8_t syscr_r();
 	void syscr_w(uint8_t data);
 

src/devices/cpu/h8/h83042.h

@@ -35,6 +35,28 @@ class h83042_device : public h8h_device {
 public:
 	h83042_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto write_port4() { return m_write_port[PORT_4].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_port7()  { return m_read_port [PORT_7].bind(); }
+	auto read_port8()  { return m_read_port [PORT_8].bind(); }
+	auto write_port8() { return m_write_port[PORT_8].bind(); }
+	auto read_port9()  { return m_read_port [PORT_9].bind(); }
+	auto write_port9() { return m_write_port[PORT_9].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+
 	uint8_t syscr_r();
 	void syscr_w(uint8_t data);
 

src/devices/cpu/h8/h83048.h

@@ -35,6 +35,28 @@ class h83048_device : public h8h_device {
 public:
 	h83048_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto write_port4() { return m_write_port[PORT_4].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_port7()  { return m_read_port [PORT_7].bind(); }
+	auto read_port8()  { return m_read_port [PORT_8].bind(); }
+	auto write_port8() { return m_write_port[PORT_8].bind(); }
+	auto read_port9()  { return m_read_port [PORT_9].bind(); }
+	auto write_port9() { return m_write_port[PORT_9].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+
 	void set_mode_a20() { m_mode_a20 = true; }
 	void set_mode_a24() { m_mode_a20 = false; }
 

src/devices/cpu/h8/h83337.h

@@ -36,6 +36,24 @@ class h83337_device : public h8_device {
 public:
 	h83337_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto write_port4() { return m_write_port[PORT_4].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_port7()  { return m_read_port [PORT_7].bind(); }
+	auto read_port8()  { return m_read_port [PORT_8].bind(); }
+	auto write_port8() { return m_write_port[PORT_8].bind(); }
+	auto read_port9()  { return m_read_port [PORT_9].bind(); }
+	auto write_port9() { return m_write_port[PORT_9].bind(); }
+
 	uint8_t wscr_r();
 	void wscr_w(uint8_t data);
 	uint8_t stcr_r();

src/devices/cpu/h8/h8_adc.cpp

@@ -19,7 +19,7 @@ h8_adc_device::h8_adc_device(const machine_config &mconfig, device_type type, co
 	device_t(mconfig, type, tag, owner, clock),
 	m_cpu(*this, finder_base::DUMMY_TAG),
 	m_intc(*this, finder_base::DUMMY_TAG),
-	m_io(nullptr), m_intc_tag(nullptr), m_intc_vector(0), m_adcsr(0), m_adcr(0), m_register_mask(0), m_trigger(0), m_start_mode(0), m_start_channel(0),
+	m_intc_vector(0), m_adcsr(0), m_adcr(0), m_register_mask(0), m_trigger(0), m_start_mode(0), m_start_channel(0),
 	m_end_channel(0), m_start_count(0), m_mode(0), m_channel(0), m_count(0), m_analog_powered(false), m_adtrg(false), m_next_event(0)
 {
 	m_suspend_on_interrupt = false;
@@ -95,7 +95,6 @@ void h8_adc_device::set_suspend(bool suspend)
 
 void h8_adc_device::device_start()
 {
-	m_io = &m_cpu->space(AS_IO);
 	save_item(NAME(m_addr));
 	save_item(NAME(m_buf));
 	save_item(NAME(m_adcsr));
@@ -162,7 +161,7 @@ void h8_adc_device::conversion_wait(bool first, bool poweron, uint64_t current_t
 
 void h8_adc_device::buffer_value(int port, int buffer)
 {
-	m_buf[buffer] = m_io->read_word(h8_device::ADC_0 + port);
+	m_buf[buffer] = m_cpu->do_read_adc(port);
 	if(V>=1) logerror("adc buffer %d -> %d:%03x\n", port, buffer, m_buf[buffer]);
 }
 

src/devices/cpu/h8/h8_adc.h

@@ -37,8 +37,6 @@ protected:
 
 	required_device<h8_device> m_cpu;
 	required_device<h8_intc_device> m_intc;
-	address_space *m_io;
-	const char *m_intc_tag;
 	int m_intc_vector;
 
 	enum {

src/devices/cpu/h8/h8_port.cpp

@@ -7,7 +7,7 @@ DEFINE_DEVICE_TYPE(H8_PORT, h8_port_device, "h8_digital_port", "H8 digital port"
 
 h8_port_device::h8_port_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
 	device_t(mconfig, H8_PORT, tag, owner, clock),
-	m_cpu(*this, DEVICE_SELF_OWNER), m_io(nullptr), m_address(0), m_default_ddr(0), m_ddr(0), m_pcr(0), m_odr(0), m_mask(0), m_dr(0), m_last_output(0)
+	m_cpu(*this, DEVICE_SELF_OWNER), m_address(0), m_default_ddr(0), m_ddr(0), m_pcr(0), m_odr(0), m_mask(0), m_dr(0), m_last_output(0)
 {
 }
 
@@ -40,7 +40,7 @@ uint8_t h8_port_device::port_r()
 {
 	uint8_t res = m_mask | (m_dr & m_ddr);
 	if((m_ddr & ~m_mask) != uint8_t(~m_mask))
-		res |= m_io->read_word(m_address) & ~m_ddr;
+		res |= m_cpu->do_read_port(m_address) & ~m_ddr;
 
 	//  logerror("port_r %02x (%02x %02x)\n", res, ddr & ~mask, uint8_t(~mask));
 	return res;
@@ -75,13 +75,12 @@ void h8_port_device::update_output()
 	uint8_t res = m_dr & m_ddr & ~m_mask;
 	if(res != m_last_output) {
 		m_last_output = res;
-		m_io->write_word(m_address, res);
+		m_cpu->do_write_port(m_address, res);
 	}
 }
 
 void h8_port_device::device_start()
 {
-	m_io = &m_cpu->space(AS_IO);
 	save_item(NAME(m_ddr));
 	save_item(NAME(m_dr));
 	save_item(NAME(m_pcr));

src/devices/cpu/h8/h8_port.h

@@ -40,7 +40,6 @@ public:
 
 protected:
 	required_device<h8_device> m_cpu;
-	address_space *m_io;
 
 	int m_address;
 	uint8_t m_default_ddr, m_ddr, m_pcr, m_odr;

src/devices/cpu/h8/h8s2245.h

@@ -37,6 +37,30 @@ class h8s2245_device : public h8s2000_device {
 public:
 	h8s2245_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+	auto read_portc()  { return m_read_port [PORT_C].bind(); }
+	auto write_portc() { return m_write_port[PORT_C].bind(); }
+	auto read_portd()  { return m_read_port [PORT_D].bind(); }
+	auto write_portd() { return m_write_port[PORT_D].bind(); }
+	auto read_porte()  { return m_read_port [PORT_E].bind(); }
+	auto write_porte() { return m_write_port[PORT_E].bind(); }
+	auto read_portf()  { return m_read_port [PORT_F].bind(); }
+	auto write_portf() { return m_write_port[PORT_F].bind(); }
+	auto read_portg()  { return m_read_port [PORT_G].bind(); }
+	auto write_portg() { return m_write_port[PORT_G].bind(); }
+
 	uint8_t syscr_r();
 	void syscr_w(uint8_t data);
 	uint16_t mstpcr_r();

src/devices/cpu/h8/h8s2320.h

@@ -43,6 +43,32 @@ class h8s2320_device : public h8s2000_device {
 public:
 	h8s2320_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+	auto read_portc()  { return m_read_port [PORT_C].bind(); }
+	auto write_portc() { return m_write_port[PORT_C].bind(); }
+	auto read_portd()  { return m_read_port [PORT_D].bind(); }
+	auto write_portd() { return m_write_port[PORT_D].bind(); }
+	auto read_porte()  { return m_read_port [PORT_E].bind(); }
+	auto write_porte() { return m_write_port[PORT_E].bind(); }
+	auto read_portf()  { return m_read_port [PORT_F].bind(); }
+	auto write_portf() { return m_write_port[PORT_F].bind(); }
+	auto read_portg()  { return m_read_port [PORT_G].bind(); }
+	auto write_portg() { return m_write_port[PORT_G].bind(); }
+
 	auto tend0_cb() { return m_tend_cb[0].bind(); }
 	auto tend1_cb() { return m_tend_cb[1].bind(); }
 

src/devices/cpu/h8/h8s2357.h

@@ -39,6 +39,32 @@ class h8s2357_device : public h8s2000_device {
 public:
 	h8s2357_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+	auto read_portc()  { return m_read_port [PORT_C].bind(); }
+	auto write_portc() { return m_write_port[PORT_C].bind(); }
+	auto read_portd()  { return m_read_port [PORT_D].bind(); }
+	auto write_portd() { return m_write_port[PORT_D].bind(); }
+	auto read_porte()  { return m_read_port [PORT_E].bind(); }
+	auto write_porte() { return m_write_port[PORT_E].bind(); }
+	auto read_portf()  { return m_read_port [PORT_F].bind(); }
+	auto write_portf() { return m_write_port[PORT_F].bind(); }
+	auto read_portg()  { return m_read_port [PORT_G].bind(); }
+	auto write_portg() { return m_write_port[PORT_G].bind(); }
+
 	uint8_t syscr_r();
 	void syscr_w(uint8_t data);
 

src/devices/cpu/h8/h8s2655.h

@@ -31,6 +31,32 @@ class h8s2655_device : public h8s2600_device {
 public:
 	h8s2655_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	auto read_port1()  { return m_read_port [PORT_1].bind(); }
+	auto write_port1() { return m_write_port[PORT_1].bind(); }
+	auto read_port2()  { return m_read_port [PORT_2].bind(); }
+	auto write_port2() { return m_write_port[PORT_2].bind(); }
+	auto read_port3()  { return m_read_port [PORT_3].bind(); }
+	auto write_port3() { return m_write_port[PORT_3].bind(); }
+	auto read_port4()  { return m_read_port [PORT_4].bind(); }
+	auto read_port5()  { return m_read_port [PORT_5].bind(); }
+	auto write_port5() { return m_write_port[PORT_5].bind(); }
+	auto read_port6()  { return m_read_port [PORT_6].bind(); }
+	auto write_port6() { return m_write_port[PORT_6].bind(); }
+	auto read_porta()  { return m_read_port [PORT_A].bind(); }
+	auto write_porta() { return m_write_port[PORT_A].bind(); }
+	auto read_portb()  { return m_read_port [PORT_B].bind(); }
+	auto write_portb() { return m_write_port[PORT_B].bind(); }
+	auto read_portc()  { return m_read_port [PORT_C].bind(); }
+	auto write_portc() { return m_write_port[PORT_C].bind(); }
+	auto read_portd()  { return m_read_port [PORT_D].bind(); }
+	auto write_portd() { return m_write_port[PORT_D].bind(); }
+	auto read_porte()  { return m_read_port [PORT_E].bind(); }
+	auto write_porte() { return m_write_port[PORT_E].bind(); }
+	auto read_portf()  { return m_read_port [PORT_F].bind(); }
+	auto write_portf() { return m_write_port[PORT_F].bind(); }
+	auto read_portg()  { return m_read_port [PORT_G].bind(); }
+	auto write_portg() { return m_write_port[PORT_G].bind(); }
+
 	uint8_t syscr_r();
 	void syscr_w(uint8_t data);
 

src/devices/machine/gt913_io.cpp

@@ -22,16 +22,13 @@ DEFINE_DEVICE_TYPE(GT913_IO_HLE, gt913_io_hle_device, "gt913_io_hle", "Casio GT9
 gt913_io_hle_device::gt913_io_hle_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
 	device_t(mconfig, GT913_IO_HLE, tag, owner, clock),
 	m_cpu(*this, finder_base::DUMMY_TAG),
-	m_intc(*this, finder_base::DUMMY_TAG),
-	m_cpu_io(nullptr)
+	m_intc(*this, finder_base::DUMMY_TAG)
 {
 	m_timer_irq[0] = m_timer_irq[1] = 0;
 }
 
 void gt913_io_hle_device::device_start()
 {
-	m_cpu_io = &m_cpu->space(AS_IO);
-
 	m_timer[0] = timer_alloc(FUNC(gt913_io_hle_device::irq_timer_tick), this);
 	m_timer[1] = timer_alloc(FUNC(gt913_io_hle_device::irq_timer_tick), this);
 
@@ -137,9 +134,9 @@ void gt913_io_hle_device::adc_control_w(uint8_t data)
 	if (m_adc_enable && BIT(data, 0))
 	{
 		if (!m_adc_channel)
-			m_adc_data[0] = m_cpu_io->read_word(h8_device::ADC_0);
+			m_adc_data[0] = m_cpu->do_read_adc(0);
 		else
-			m_adc_data[1] = m_cpu_io->read_word(h8_device::ADC_1);
+			m_adc_data[1] = m_cpu->do_read_adc(1);
 	}
 }
 

src/devices/machine/gt913_io.h

@@ -51,9 +51,8 @@ protected:
 	TIMER_CALLBACK_MEMBER(irq_timer_tick);
 
 private:
-	required_device<cpu_device> m_cpu;
+	required_device<h8_device> m_cpu;
 	required_device<h8_intc_device> m_intc;
-	address_space *m_cpu_io;
 
 	/* timers */
 	uint8_t m_timer_control[2];

src/devices/sound/xt446.cpp

@@ -64,18 +64,6 @@ void xt446_device::xt446_map(address_map &map)
 	map(0x400000, 0x401fff).m(m_swp30, FUNC(swp30_device::map));
 }
 
-void xt446_device::xt446_iomap(address_map &map)
-{
-	map(h8_device::ADC_0, h8_device::ADC_0).lr16(NAME([]() -> u16 { return 0; }));
-	map(h8_device::ADC_1, h8_device::ADC_1).lr16(NAME([]() -> u16 { return 0; }));
-	map(h8_device::ADC_2, h8_device::ADC_2).lr16(NAME([]() -> u16 { return 0; }));
-	map(h8_device::ADC_3, h8_device::ADC_3).lr16(NAME([]() -> u16 { return 0; }));
-	map(h8_device::ADC_4, h8_device::ADC_4).lr16(NAME([]() -> u16 { return 0; }));
-	map(h8_device::ADC_5, h8_device::ADC_5).lr16(NAME([]() -> u16 { return 0; }));
-	map(h8_device::ADC_6, h8_device::ADC_6).lr16(NAME([]() -> u16 { return 0x200; }));
-	map(h8_device::ADC_7, h8_device::ADC_7).lr16(NAME([]() -> u16 { return 0x200; }));
-}
-
 void xt446_device::swp30_map(address_map &map)
 {
 	map(0x000000*4, 0x200000*4-1).rom().region("swp30",         0).mirror(4*0x200000);
@@ -87,7 +75,14 @@ void xt446_device::device_add_mconfig(machine_config &config)
 {
 	H8S2655(config, m_maincpu, 16_MHz_XTAL);
 	m_maincpu->set_addrmap(AS_PROGRAM, &xt446_device::xt446_map);
-	m_maincpu->set_addrmap(AS_IO, &xt446_device::xt446_iomap);
+	m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(2).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(3).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(4).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(5).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(6).set([]() -> u16 { return 0x200; });
+	m_maincpu->read_adc(7).set([]() -> u16 { return 0x200; });
 
 	SWP30(config, m_swp30);
 	m_swp30->set_addrmap(0, &xt446_device::swp30_map);

src/devices/sound/xt446.h

@@ -33,7 +33,6 @@ private:
 	required_device<swp30_device> m_swp30;
 	required_device<h8_sci_device> m_midi_serial;
 
-	void xt446_iomap(address_map &map);
 	void xt446_map(address_map &map);
 	void swp30_map(address_map &map);
 };

src/mame/bandai/design_master.cpp

@@ -65,17 +65,15 @@ protected:
 	virtual void machine_start() override;
 
 private:
-	void io_map(address_map &map);
 	void mem_map(address_map &map);
 
 	uint16_t io_p7_r();
-	void io_p7_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
 
 	uint32_t screen_update(screen_device& screen, bitmap_rgb32& bitmap, const rectangle& cliprect);
 
 	[[maybe_unused]] DECLARE_DEVICE_IMAGE_LOAD_MEMBER(cart_load_bdesignm);
 
-	required_device<cpu_device> m_maincpu;
+	required_device<h83334_device> m_maincpu;
 	required_device<generic_slot_device> m_cartslot;
 	memory_region *m_cartslot_region;
 	required_memory_bank m_bank;
@@ -115,17 +113,6 @@ uint16_t bdsm_state::io_p7_r()
 	return machine().rand();
 }
 
-void bdsm_state::io_p7_w(offs_t offset, uint16_t data, uint16_t mem_mask)
-{
-	logerror("%s: io_p7_w %04x %04x\n", machine().describe_context(), data, mem_mask);
-}
-
-
-void bdsm_state::io_map(address_map &map)
-{
-	map(h8_device::PORT_7, h8_device::PORT_7).rw(FUNC(bdsm_state::io_p7_r), FUNC(bdsm_state::io_p7_w));
-}
-
 static INPUT_PORTS_START( bdesignm )
 INPUT_PORTS_END
 
@@ -140,7 +127,7 @@ void bdsm_state::bdesignm(machine_config &config)
 	/* basic machine hardware */
 	H83334(config, m_maincpu, XTAL(20'000'000)); /* H8/328 (24kbytes internal ROM, 1kbyte internal ROM) ?Mhz */
 	m_maincpu->set_addrmap(AS_PROGRAM, &bdsm_state::mem_map);
-	m_maincpu->set_addrmap(AS_IO, &bdsm_state::io_map);
+	m_maincpu->read_port7().set(FUNC(bdsm_state::io_p7_r));
 
 	SCREEN(config, m_screen, SCREEN_TYPE_LCD);
 	m_screen->set_refresh_hz(60);

src/mame/brother/lw700i.cpp

@@ -61,7 +61,6 @@ private:
 	TIMER_DEVICE_CALLBACK_MEMBER(vbl_interrupt);
 
 	void main_map(address_map &map) ATTR_COLD;
-	void io_map(address_map &map) ATTR_COLD;
 
 	// devices
 	required_device<h83003_device> m_maincpu;
@@ -165,12 +164,6 @@ void lw700i_state::main_map(address_map &map)
 	map(0xf00048, 0xf00049).ram();
 }
 
-void lw700i_state::io_map(address_map &map)
-{
-	map(h83003_device::PORT_7, h83003_device::PORT_7).r(FUNC(lw700i_state::p7_r));
-	map(h83003_device::PORT_B, h83003_device::PORT_B).rw(FUNC(lw700i_state::pb_r), FUNC(lw700i_state::pb_w));
-}
-
 // row 0:   | 4 | 3 | W | E | D | X | ? | Enter? |
 // row 1:   | 5 | 6 | R | T | C | F | ? | DArr |
 // row 2:   | 8 | 7 | Y | H | G | V | ? | ? |
@@ -283,7 +276,10 @@ void lw700i_state::lw700i(machine_config &config)
 {
 	H83003(config, m_maincpu, XTAL(16'000'000));
 	m_maincpu->set_addrmap(AS_PROGRAM, &lw700i_state::main_map);
-	m_maincpu->set_addrmap(AS_IO, &lw700i_state::io_map);
+	m_maincpu->read_port7().set(FUNC(lw700i_state::p7_r));
+	m_maincpu->read_portb().set(FUNC(lw700i_state::pb_r));
+	m_maincpu->write_portb().set(FUNC(lw700i_state::pb_w));
+
 	m_maincpu->tend2().set(m_fdc, FUNC(hd63266f_device::tc_line_w));
 	TIMER(config, "scantimer").configure_scanline(FUNC(lw700i_state::vbl_interrupt), "screen", 0, 1);
 

src/mame/brother/lw840.cpp

@@ -202,11 +202,6 @@ private:
 		map(0xec0000, 0xec0001).r(FUNC(lw840_state::keyboard_r)).w(FUNC(lw840_state::keyboard_w));
 		map(0xec0004, 0xec0005).r(FUNC(lw840_state::disk_inserted_r));
 	}
-
-	void map_io(address_map &map) ATTR_COLD
-	{
-		map(h8_device::PORT_7, h8_device::PORT_7).r(FUNC(lw840_state::port7_r));
-	}
 };
 
 uint32_t lw840_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
@@ -347,7 +342,7 @@ void lw840_state::lw840(machine_config &config)
 	// basic machine hardware
 	H83003(config, maincpu, 14'745'600);
 	maincpu->set_addrmap(AS_PROGRAM, &lw840_state::map_program);
-	maincpu->set_addrmap(AS_IO, &lw840_state::map_io);
+	maincpu->read_port7().set(FUNC(lw840_state::port7_r));
 	maincpu->tend0().set("fdc", FUNC(gm82c765b_device::tc_line_w));
 
 	TIMER(config, "2khz").configure_periodic(FUNC(lw840_state::int2_timer_callback), attotime::from_hz(2*1000));

src/mame/casio/ctk551.cpp

@@ -273,11 +273,6 @@ private:
 	void gz70sp_map(address_map& map);
 	void ctk601_map(address_map& map);
 
-	void ap10_io_map(address_map& map);
-	void ctk530_io_map(address_map& map);
-	void gz70sp_io_map(address_map& map);
-	void ctk551_io_map(address_map &map);
-
 	virtual void driver_start() override;
 
 	required_device<gt913_device> m_maincpu;
@@ -431,38 +426,6 @@ void ctk551_state::ctk601_map(address_map& map)
 	map(0x380002, 0x380003).portr("PB").portw("PA").umask16(0x00ff);
 }
 
-void ctk551_state::ap10_io_map(address_map& map)
-{
-	map(h8_device::PORT_1, h8_device::PORT_1).portrw("P1").umask16(0x00ff);
-	map(h8_device::PORT_2, h8_device::PORT_4).noprw();
-	map(h8_device::ADC_0, h8_device::ADC_1).nopr();
-}
-
-void ctk551_state::ctk530_io_map(address_map& map)
-{
-	map(h8_device::PORT_1, h8_device::PORT_1).portrw("P1").umask16(0x00ff);
-	map(h8_device::PORT_2, h8_device::PORT_3).noprw();
-	map(h8_device::PORT_4, h8_device::PORT_4).portw("PLE");
-	map(h8_device::ADC_0, h8_device::ADC_1).nopr();
-}
-
-void ctk551_state::gz70sp_io_map(address_map& map)
-{
-	map(h8_device::PORT_1, h8_device::PORT_1).portrw("P1").umask16(0x00ff);
-	map(h8_device::PORT_2, h8_device::PORT_2).portrw("P2").umask16(0x00ff);
-	map(h8_device::PORT_3, h8_device::PORT_4).noprw();
-	map(h8_device::ADC_0, h8_device::ADC_1).nopr();
-}
-
-void ctk551_state::ctk551_io_map(address_map &map)
-{
-	map(h8_device::PORT_1, h8_device::PORT_1).portr("P1_R").portw("P1_W").umask16(0x00ff);
-	map(h8_device::PORT_2, h8_device::PORT_2).portrw("P2").umask16(0x00ff);
-	map(h8_device::PORT_3, h8_device::PORT_4).noprw(); // port 3 pins are shared w/ key matrix
-	map(h8_device::ADC_0,  h8_device::ADC_0).portr("AN0");
-	map(h8_device::ADC_1,  h8_device::ADC_1).portr("AN1");
-}
-
 void ctk551_state::driver_start()
 {
 	m_led_touch.resolve();
@@ -486,9 +449,18 @@ void ctk551_state::ap10(machine_config& config)
 	// CPU
 	GT913(config, m_maincpu, 24_MHz_XTAL / 2);
 	m_maincpu->set_addrmap(AS_DATA, &ctk551_state::ap10_map);
-	m_maincpu->set_addrmap(AS_IO, &ctk551_state::ap10_io_map);
 	m_maincpu->add_route(0, "lspeaker", 1.0);
 	m_maincpu->add_route(1, "rspeaker", 1.0);
+	m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_maincpu->read_port1().set_ioport("P1");
+	m_maincpu->write_port1().set_ioport("P1");
+	m_maincpu->read_port2().set([]() -> u16 { return 0; });
+	m_maincpu->write_port2().set([](u16) {});
+	m_maincpu->read_port3().set([]() -> u16 { return 0; });
+	m_maincpu->write_port3().set([](u16) {});
+	m_maincpu->read_port4().set([]() -> u16 { return 0; });
+	m_maincpu->write_port4().set([](u16) {});
 
 	NVRAM(config, "nvram");
 
@@ -514,9 +486,17 @@ void ctk551_state::ctk530(machine_config& config)
 	// CPU
 	GT913(config, m_maincpu, 20_MHz_XTAL / 2);
 	m_maincpu->set_addrmap(AS_DATA, &ctk551_state::ctk530_map);
-	m_maincpu->set_addrmap(AS_IO, &ctk551_state::ctk530_io_map);
 	m_maincpu->add_route(0, "lspeaker", 1.0);
 	m_maincpu->add_route(1, "rspeaker", 1.0);
+	m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_maincpu->read_port1().set_ioport("P1");
+	m_maincpu->write_port1().set_ioport("P1");
+	m_maincpu->read_port2().set([]() -> u16 { return 0; });
+	m_maincpu->write_port2().set([](u16) {});
+	m_maincpu->read_port3().set([]() -> u16 { return 0; });
+	m_maincpu->write_port3().set([](u16) {});
+	m_maincpu->write_port4().set_ioport("PLE");
 
 	// MIDI
 	auto& mdin(MIDI_PORT(config, "mdin"));
@@ -542,9 +522,18 @@ void ctk551_state::gz70sp(machine_config& config)
 	// CPU
 	GT913(config, m_maincpu, 30_MHz_XTAL / 2);
 	m_maincpu->set_addrmap(AS_DATA, &ctk551_state::gz70sp_map);
-	m_maincpu->set_addrmap(AS_IO, &ctk551_state::gz70sp_io_map);
 	m_maincpu->add_route(0, "lspeaker", 1.0);
 	m_maincpu->add_route(1, "rspeaker", 1.0);
+	m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_maincpu->read_port1().set_ioport("P1");
+	m_maincpu->write_port1().set_ioport("P1");
+	m_maincpu->read_port2().set_ioport("P2");
+	m_maincpu->write_port2().set_ioport("P2");
+	m_maincpu->read_port3().set([]() -> u16 { return 0; });
+	m_maincpu->write_port3().set([](u16) {});
+	m_maincpu->read_port4().set([]() -> u16 { return 0; });
+	m_maincpu->write_port4().set([](u16) {});
 
 	// MIDI (sci0 for RS232/422, sci1 for standard MIDI)
 	auto& mdin(MIDI_PORT(config, "mdin"));
@@ -560,9 +549,18 @@ void ctk551_state::ctk601(machine_config& config)
 	// CPU
 	GT913(config, m_maincpu, 30_MHz_XTAL / 2);
 	m_maincpu->set_addrmap(AS_DATA, &ctk551_state::ctk601_map);
-	m_maincpu->set_addrmap(AS_IO, &ctk551_state::ctk551_io_map);
 	m_maincpu->add_route(0, "lspeaker", 1.0);
 	m_maincpu->add_route(1, "rspeaker", 1.0);
+	m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_maincpu->read_port1().set_ioport("P1_R");
+	m_maincpu->write_port1().set_ioport("P1_W");
+	m_maincpu->read_port2().set_ioport("P2");
+	m_maincpu->write_port2().set_ioport("P2");
+	m_maincpu->read_port3().set([]() -> u16 { return 0; }); // port 3 pins are shared w/ key matrix
+	m_maincpu->write_port3().set([](u16) {});
+	m_maincpu->read_port4().set([]() -> u16 { return 0; });
+	m_maincpu->write_port4().set([](u16) {});
 
 	// TODO: DSP
 
@@ -596,9 +594,18 @@ void ctk551_state::ctk551(machine_config &config)
 	// CPU
 	GT913(config, m_maincpu, 30'000'000 / 2);
 	m_maincpu->set_addrmap(AS_DATA, &ctk551_state::ctk530_map);
-	m_maincpu->set_addrmap(AS_IO, &ctk551_state::ctk551_io_map);
 	m_maincpu->add_route(0, "lspeaker", 1.0);
 	m_maincpu->add_route(1, "rspeaker", 1.0);
+	m_maincpu->read_adc(0).set_ioport("AN0");
+	m_maincpu->read_adc(1).set_ioport("AN1");
+	m_maincpu->read_port1().set_ioport("P1_R");
+	m_maincpu->write_port1().set_ioport("P1_W");
+	m_maincpu->read_port2().set_ioport("P2");
+	m_maincpu->write_port2().set_ioport("P2");
+	m_maincpu->read_port3().set([]() -> u16 { return 0; }); // port 3 pins are shared w/ key matrix
+	m_maincpu->write_port3().set([](u16) {});
+	m_maincpu->read_port4().set([]() -> u16 { return 0; });
+	m_maincpu->write_port4().set([](u16) {});
 
 	// MIDI
 	auto &mdin(MIDI_PORT(config, "mdin"));

src/mame/cybiko/cybiko.cpp

@@ -179,32 +179,6 @@ uint16_t cybiko_state::port0_r()
 }
 
 
-//////////////////////
-// ADDRESS MAP - IO //
-//////////////////////
-
-void cybiko_state::cybikov1_io(address_map &map)
-{
-	map(h8_device::PORT_3, h8_device::PORT_3).w(FUNC(cybiko_state::serflash_w));
-	map(h8_device::PORT_F, h8_device::PORT_F).rw(FUNC(cybiko_state::clock_r), FUNC(cybiko_state::clock_w));
-	map(h8_device::ADC_1, h8_device::ADC_1).r(FUNC(cybiko_state::adc1_r));
-	map(h8_device::ADC_2, h8_device::ADC_2).r(FUNC(cybiko_state::adc2_r));
-}
-
-void cybiko_state::cybikov2_io(address_map &map)
-{
-	map(h8_device::PORT_1, h8_device::PORT_1).r(FUNC(cybiko_state::port0_r));
-	map(h8_device::PORT_3, h8_device::PORT_3).w(FUNC(cybiko_state::serflash_w));
-	map(h8_device::PORT_F, h8_device::PORT_F).rw(FUNC(cybiko_state::clock_r), FUNC(cybiko_state::clock_w));
-	map(h8_device::ADC_1, h8_device::ADC_1).r(FUNC(cybiko_state::adc1_r));
-	map(h8_device::ADC_2, h8_device::ADC_2).r(FUNC(cybiko_state::adc2_r));
-}
-
-void cybiko_state::cybikoxt_io(address_map &map)
-{
-	map(h8_device::PORT_A, h8_device::PORT_A).r(FUNC(cybiko_state::xtpower_r));
-	map(h8_device::PORT_F, h8_device::PORT_F).rw(FUNC(cybiko_state::xtclock_r), FUNC(cybiko_state::xtclock_w));
-}
 
 /////////////////
 // INPUT PORTS //
@@ -439,9 +413,13 @@ void cybiko_state::cybikov1(machine_config &config)
 	cybikov1_base(config);
 
 	// cpu
-	H8S2241(config, m_maincpu, XTAL(11'059'200));
-	m_maincpu->set_addrmap(AS_PROGRAM, &cybiko_state::cybikov1_mem);
-	m_maincpu->set_addrmap(AS_IO, &cybiko_state::cybikov1_io);
+	auto &maincpu(H8S2241(config, m_maincpu, XTAL(11'059'200)));
+	maincpu.set_addrmap(AS_PROGRAM, &cybiko_state::cybikov1_mem);
+	maincpu.read_adc(1).set(FUNC(cybiko_state::adc1_r));
+	maincpu.read_adc(2).set(FUNC(cybiko_state::adc2_r));
+	maincpu.write_port3().set(FUNC(cybiko_state::serflash_w));
+	maincpu.read_portf().set(FUNC(cybiko_state::clock_r));
+	maincpu.write_portf().set(FUNC(cybiko_state::clock_w));
 
 	subdevice<h8_sci_device>("maincpu:sci1")->tx_handler().set("flash1", FUNC(at45db041_device::si_w));
 	subdevice<h8_sci_device>("maincpu:sci1")->clk_handler().set("flash1", FUNC(at45db041_device::sck_w));
@@ -457,9 +435,14 @@ void cybiko_state::cybikov2(machine_config &config)
 	cybikov1_flash(config);
 
 	// cpu
-	H8S2246(config, m_maincpu, XTAL(11'059'200));
-	m_maincpu->set_addrmap(AS_PROGRAM, &cybiko_state::cybikov2_mem);
-	m_maincpu->set_addrmap(AS_IO, &cybiko_state::cybikov2_io);
+	auto &maincpu(H8S2246(config, m_maincpu, XTAL(11'059'200)));
+	maincpu.set_addrmap(AS_PROGRAM, &cybiko_state::cybikov2_mem);
+	maincpu.read_adc(1).set(FUNC(cybiko_state::adc1_r));
+	maincpu.read_adc(2).set(FUNC(cybiko_state::adc2_r));
+	maincpu.read_port1().set(FUNC(cybiko_state::port0_r));
+	maincpu.write_port3().set(FUNC(cybiko_state::serflash_w));
+	maincpu.read_portf().set(FUNC(cybiko_state::clock_r));
+	maincpu.write_portf().set(FUNC(cybiko_state::clock_w));
 
 	subdevice<h8_sci_device>("maincpu:sci1")->tx_handler().set("flash1", FUNC(at45db041_device::si_w));
 	subdevice<h8_sci_device>("maincpu:sci1")->clk_handler().set("flash1", FUNC(at45db041_device::sck_w));
@@ -481,9 +464,11 @@ void cybiko_state::cybikoxt(machine_config &config)
 	cybikov1_base(config);
 
 	// cpu
-	H8S2323(config, m_maincpu, XTAL(18'432'000));
-	m_maincpu->set_addrmap(AS_PROGRAM, &cybiko_state::cybikoxt_mem);
-	m_maincpu->set_addrmap(AS_IO, &cybiko_state::cybikoxt_io);
+	auto &maincpu(H8S2323(config, m_maincpu, XTAL(18'432'000)));
+	maincpu.set_addrmap(AS_PROGRAM, &cybiko_state::cybikoxt_mem);
+	maincpu.read_porta().set(FUNC(cybiko_state::xtpower_r));
+	maincpu.read_portf().set(FUNC(cybiko_state::xtclock_r));
+	maincpu.write_portf().set(FUNC(cybiko_state::xtclock_w));
 
 	// machine
 	SST_39VF400A(config, "flashxt");

src/mame/cybiko/cybiko.h

@@ -93,11 +93,8 @@ private:
 	DECLARE_QUICKLOAD_LOAD_MEMBER(quickload_cybiko);
 	DECLARE_QUICKLOAD_LOAD_MEMBER(quickload_cybikoxt);
 
-	void cybikov1_io(address_map &map);
 	void cybikov1_mem(address_map &map);
-	void cybikov2_io(address_map &map);
 	void cybikov2_mem(address_map &map);
-	void cybikoxt_io(address_map &map);
 	void cybikoxt_mem(address_map &map);
 };
 

src/mame/metro/metro.cpp

@@ -1070,13 +1070,6 @@ void metro_state::puzzlet_portb_w(u16 data)
 //  popmessage("PORTB %02x", data);
 }
 
-void metro_state::puzzlet_io_map(address_map &map)
-{
-	map(h8_device::PORT_7, h8_device::PORT_7).portr("IN2");
-	map(h8_device::PORT_B, h8_device::PORT_B).portr("DSW0").w(FUNC(metro_state::puzzlet_portb_w));
-}
-
-
 /***************************************************************************
                                 Varia Metal
 ***************************************************************************/
@@ -3492,9 +3485,11 @@ void metro_state::gstrik2(machine_config &config)
 void metro_state::puzzlet(machine_config &config)
 {
 	/* basic machine hardware */
-	H83007(config, m_maincpu, 20_MHz_XTAL); // H8/3007 - Hitachi HD6413007F20 CPU. Clock 20MHz
-	m_maincpu->set_addrmap(AS_PROGRAM, &metro_state::puzzlet_map);
-	m_maincpu->set_addrmap(AS_IO, &metro_state::puzzlet_io_map);
+	auto &maincpu(H83007(config, m_maincpu, 20_MHz_XTAL)); // H8/3007 - Hitachi HD6413007F20 CPU. Clock 20MHz
+	maincpu.set_addrmap(AS_PROGRAM, &metro_state::puzzlet_map);
+	maincpu.read_port7().set_ioport("IN2");
+	maincpu.read_portb().set_ioport("DSW0");
+	maincpu.write_portb().set(FUNC(metro_state::puzzlet_portb_w));
 
 	/* Coins/service */
 	z8_device &coinmcu(Z86E02(config, "coinmcu", 20_MHz_XTAL/5)); // clock divider guessed

src/mame/metro/metro.h

@@ -170,7 +170,6 @@ private:
 	void pangpoms_map(address_map &map);
 	void poitto_map(address_map &map);
 	void pururun_map(address_map &map);
-	void puzzlet_io_map(address_map &map);
 	void puzzlet_map(address_map &map);
 	void skyalert_map(address_map &map);
 	void toride2g_map(address_map &map);

src/mame/namco/namcond1.cpp

@@ -236,7 +236,7 @@ protected:
 
 private:
 	required_device<cpu_device> m_maincpu;
-	required_device<cpu_device> m_mcu;
+	required_device<h83002_device> m_mcu;
 	required_device<ygv608_device> m_ygv608;
 
 	required_shared_ptr<uint16_t> m_shared_ram;
@@ -254,7 +254,6 @@ private:
 	INTERRUPT_GEN_MEMBER(mcu_interrupt);
 	void abcheck_main_map(address_map &map);
 	void main_map(address_map &map);
-	void h8iomap(address_map &map);
 	void h8rwmap(address_map &map);
 };
 
@@ -472,14 +471,6 @@ void namcond1_state::h8rwmap(address_map &map)
 	map(0xffff1e, 0xffff1f).noprw();     // ^
 }
 
-void namcond1_state::h8iomap(address_map &map)
-{
-	map(h8_device::PORT_7, h8_device::PORT_7).r(FUNC(namcond1_state::mcu_p7_read));
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(namcond1_state::mcu_pa_read), FUNC(namcond1_state::mcu_pa_write));
-	map(h8_device::ADC_0, h8_device::ADC_3).noprw(); // MCU reads these, but the games have no analog controls
-	map(0x14, 0x17).nopr();         // abcheck
-}
-
 INTERRUPT_GEN_MEMBER(namcond1_state::mcu_interrupt)
 {
 	if (m_h8_irq5_enabled)
@@ -504,8 +495,15 @@ void namcond1_state::namcond1(machine_config &config)
 
 	H83002(config, m_mcu, XTAL(49'152'000) / 3);
 	m_mcu->set_addrmap(AS_PROGRAM, &namcond1_state::h8rwmap);
-	m_mcu->set_addrmap(AS_IO, &namcond1_state::h8iomap);
 	m_mcu->set_vblank_int("screen", FUNC(namcond1_state::mcu_interrupt));
+	m_mcu->read_adc(0).set([]() -> u16 { return 0; }); // MCU reads these, but the games have no analog controls
+	m_mcu->read_adc(1).set([]() -> u16 { return 0; });
+	m_mcu->read_adc(2).set([]() -> u16 { return 0; });
+	m_mcu->read_adc(3).set([]() -> u16 { return 0; });
+	m_mcu->read_port7().set(FUNC(namcond1_state::mcu_p7_read));
+	m_mcu->read_porta().set(FUNC(namcond1_state::mcu_pa_read));
+	m_mcu->write_porta().set(FUNC(namcond1_state::mcu_pa_write));
+
 
 	config.set_maximum_quantum(attotime::from_hz(6000));
 

src/mame/namco/namcos10_exio.cpp

@@ -224,23 +224,24 @@ void namcos10_mgexio_device::port_w(uint16_t data)
 	m_port_write[Port](data);
 }
 
-void namcos10_mgexio_device::io_map(address_map &map)
-{
-	map(h8_device::PORT_4, h8_device::PORT_4).rw(FUNC(namcos10_mgexio_device::port_r<0>), FUNC(namcos10_mgexio_device::port_w<0>));
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(namcos10_mgexio_device::port_r<1>), FUNC(namcos10_mgexio_device::port_w<1>));
-	map(h8_device::PORT_7, h8_device::PORT_7).rw(FUNC(namcos10_mgexio_device::port_r<2>), FUNC(namcos10_mgexio_device::port_w<2>));
-	map(h8_device::PORT_8, h8_device::PORT_8).rw(FUNC(namcos10_mgexio_device::port_r<3>), FUNC(namcos10_mgexio_device::port_w<3>));
-	map(h8_device::PORT_9, h8_device::PORT_9).rw(FUNC(namcos10_mgexio_device::port_r<4>), FUNC(namcos10_mgexio_device::port_w<4>));
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(namcos10_mgexio_device::port_r<5>), FUNC(namcos10_mgexio_device::port_w<5>));
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(namcos10_mgexio_device::port_r<6>), FUNC(namcos10_mgexio_device::port_w<6>));
-}
-
 void namcos10_mgexio_device::device_add_mconfig(machine_config &config)
 {
 	H83007(config, m_maincpu, 14.746_MHz_XTAL);
 	m_maincpu->set_mode_a20();
 	m_maincpu->set_addrmap(AS_PROGRAM, &namcos10_mgexio_device::map);
-	m_maincpu->set_addrmap(AS_IO, &namcos10_mgexio_device::io_map);
+	m_maincpu->read_port4().set(FUNC(namcos10_mgexio_device::port_r<0>));
+	m_maincpu->write_port4().set(FUNC(namcos10_mgexio_device::port_w<0>));
+	m_maincpu->read_port6().set(FUNC(namcos10_mgexio_device::port_r<1>));
+	m_maincpu->write_port6().set(FUNC(namcos10_mgexio_device::port_w<1>));
+	m_maincpu->read_port7().set(FUNC(namcos10_mgexio_device::port_r<2>));
+	m_maincpu->read_port8().set(FUNC(namcos10_mgexio_device::port_r<3>));
+	m_maincpu->write_port8().set(FUNC(namcos10_mgexio_device::port_w<3>));
+	m_maincpu->read_port9().set(FUNC(namcos10_mgexio_device::port_r<4>));
+	m_maincpu->write_port9().set(FUNC(namcos10_mgexio_device::port_w<4>));
+	m_maincpu->read_porta().set(FUNC(namcos10_mgexio_device::port_r<5>));
+	m_maincpu->write_porta().set(FUNC(namcos10_mgexio_device::port_w<5>));
+	m_maincpu->read_portb().set(FUNC(namcos10_mgexio_device::port_r<6>));
+	m_maincpu->write_portb().set(FUNC(namcos10_mgexio_device::port_w<6>));
 
 	NVRAM(config, m_nvram, nvram_device::DEFAULT_ALL_0);
 }

src/mame/namco/namcos10_exio.h

@@ -115,7 +115,6 @@ protected:
 
 private:
 	void map(address_map &map);
-	void io_map(address_map &map);
 
 	template <int Port> uint16_t port_r();
 	template <int Port> void port_w(uint16_t data);

src/mame/namco/namcos12.cpp

@@ -1145,23 +1145,28 @@ public:
 protected:
 	virtual void machine_reset() override;
 
-	void golgo13_h8iomap(address_map &map);
-	void kartduel_h8iomap(address_map &map);
-	void jvsiomap(address_map &map);
 	void jvsmap(address_map &map);
 	void namcos12_map(address_map &map);
-	void plarailjvsiomap(address_map &map);
 	void plarailjvsmap(address_map &map);
 	void ptblank2_map(address_map &map);
-	void s12h8iomap(address_map &map);
-	void s12h8jvsiomap(address_map &map);
-	void s12h8railiomap(address_map &map);
 	void s12h8rwjvsmap(address_map &map);
 	void s12h8rwmap(address_map &map);
-	void tdjvsiomap(address_map &map);
 	void tdjvsmap(address_map &map);
 	void tektagt_map(address_map &map);
 
+	uint16_t s12_mcu_gun_h_r();
+	uint16_t s12_mcu_gun_v_r();
+	uint8_t s12_mcu_p8_r();
+	uint8_t s12_mcu_jvs_p8_r();
+	uint8_t s12_mcu_pa_r();
+	void s12_mcu_pa_w(uint8_t data);
+	uint8_t s12_mcu_portB_r();
+	void s12_mcu_portB_w(uint8_t data);
+	uint8_t s12_mcu_p6_r();
+	uint16_t iob_p4_r();
+	uint16_t iob_p6_r();
+	void iob_p4_w(uint16_t data);
+
 	required_device<psxcpu_device> m_maincpu;
 	required_device<ram_device> m_ram;
 	required_device<h83002_device> m_sub;
@@ -1193,11 +1198,6 @@ private:
 	uint8_t m_jvssense;
 	uint8_t m_tssio_port_4;
 
-	uint16_t s12_mcu_p6_r();
-	uint16_t iob_p4_r();
-	uint16_t iob_p6_r();
-	void iob_p4_w(uint16_t data);
-
 	void sharedram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
 	uint16_t sharedram_r(offs_t offset, uint16_t mem_mask = ~0);
 	void bankoffset_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
@@ -1209,14 +1209,6 @@ private:
 	void tektagt_protection_2_w(offs_t offset, uint16_t data);
 	uint16_t tektagt_protection_2_r(offs_t offset);
 	uint16_t tektagt_protection_3_r();
-	uint16_t s12_mcu_p8_r();
-	uint16_t s12_mcu_jvs_p8_r();
-	uint16_t s12_mcu_pa_r();
-	void s12_mcu_pa_w(uint16_t data);
-	uint16_t s12_mcu_portB_r();
-	void s12_mcu_portB_w(uint16_t data);
-	uint16_t s12_mcu_gun_h_r();
-	uint16_t s12_mcu_gun_v_r();
 
 	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
 	void namcos12_rom_read( uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size );
@@ -1595,7 +1587,7 @@ void namcos12_state::s12h8rwjvsmap(address_map &map)
 	map(0x300030, 0x300031).noprw(); // most S12 bioses write here simply to generate a wait state.  there is no deeper meaning.
 }
 
-uint16_t namcos12_state::s12_mcu_p8_r()
+uint8_t namcos12_state::s12_mcu_p8_r()
 {
 	return 0x02;
 }
@@ -1604,88 +1596,41 @@ uint16_t namcos12_state::s12_mcu_p8_r()
 // in System 12, bit 0 of H8/3002 port A is connected to its chip enable
 // the actual I/O takes place through the H8/3002's serial port B.
 
-uint16_t namcos12_state::s12_mcu_pa_r()
+uint8_t namcos12_state::s12_mcu_pa_r()
 {
 	return m_sub_porta;
 }
 
-void namcos12_state::s12_mcu_pa_w(uint16_t data)
+void namcos12_state::s12_mcu_pa_w(uint8_t data)
 {
 	m_sub_porta = data;
 	m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
 	m_settings->ce_w((m_sub_portb & 0x20) && !(m_sub_porta & 1));
 }
 
-uint16_t namcos12_state::s12_mcu_portB_r()
+uint8_t namcos12_state::s12_mcu_portB_r()
 {
 	return m_sub_portb;
 }
 
-void namcos12_state::s12_mcu_portB_w(uint16_t data)
+void namcos12_state::s12_mcu_portB_w(uint8_t data)
 {
 	m_sub_portb = (m_sub_portb & 0x80) | (data & 0x7f);
 	m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
 	m_settings->ce_w((m_sub_portb & 0x20) && !(m_sub_porta & 1));
 }
 
-uint16_t namcos12_state::s12_mcu_p6_r()
+uint8_t namcos12_state::s12_mcu_p6_r()
 {
 	// bit 1 = JVS cable present sense (1 = I/O board plugged in)
 	return (m_jvssense << 1) | 0xfd;
 }
 
-uint16_t namcos12_state::s12_mcu_jvs_p8_r()
+uint8_t namcos12_state::s12_mcu_jvs_p8_r()
 {
 	return 0x12;    // bit 4 = JVS enable.  aplarail requires it to be on, soulclbr & others will require JVS I/O if it's on
 }
 
-void namcos12_state::s12h8iomap(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).r(FUNC(namcos12_state::s12_mcu_p6_r));
-	map(h8_device::PORT_7, h8_device::PORT_7).portr("DSW");
-	map(h8_device::PORT_8, h8_device::PORT_8).r(FUNC(namcos12_state::s12_mcu_p8_r)).nopw();
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(namcos12_state::s12_mcu_pa_r), FUNC(namcos12_state::s12_mcu_pa_w));
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(namcos12_state::s12_mcu_portB_r), FUNC(namcos12_state::s12_mcu_portB_w));
-	map(h8_device::ADC_0, h8_device::ADC_0).noprw();
-	map(h8_device::ADC_1, h8_device::ADC_1).noprw();
-	map(h8_device::ADC_2, h8_device::ADC_2).noprw();
-	map(h8_device::ADC_3, h8_device::ADC_3).noprw();
-}
-
-void namcos12_state::s12h8jvsiomap(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).r(FUNC(namcos12_state::s12_mcu_p6_r));
-	map(h8_device::PORT_7, h8_device::PORT_7).portr("DSW");
-	map(h8_device::PORT_8, h8_device::PORT_8).r(FUNC(namcos12_state::s12_mcu_jvs_p8_r)).nopw();
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(namcos12_state::s12_mcu_pa_r), FUNC(namcos12_state::s12_mcu_pa_w));
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(namcos12_state::s12_mcu_portB_r), FUNC(namcos12_state::s12_mcu_portB_w));
-	map(h8_device::ADC_0, h8_device::ADC_0).noprw();
-	map(h8_device::ADC_1, h8_device::ADC_1).noprw();
-	map(h8_device::ADC_2, h8_device::ADC_2).noprw();
-	map(h8_device::ADC_3, h8_device::ADC_3).noprw();
-}
-
-void namcos12_state::s12h8railiomap(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).r(FUNC(namcos12_state::s12_mcu_p6_r));
-	map(h8_device::PORT_7, h8_device::PORT_7).portr("DSW");
-	map(h8_device::PORT_8, h8_device::PORT_8).r(FUNC(namcos12_state::s12_mcu_jvs_p8_r)).nopw();
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(namcos12_state::s12_mcu_pa_r), FUNC(namcos12_state::s12_mcu_pa_w));
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(namcos12_state::s12_mcu_portB_r), FUNC(namcos12_state::s12_mcu_portB_w));
-	map(h8_device::ADC_0, h8_device::ADC_0).portr("LEVER");
-	map(h8_device::ADC_1, h8_device::ADC_1).noprw();
-	map(h8_device::ADC_2, h8_device::ADC_2).noprw();
-	map(h8_device::ADC_3, h8_device::ADC_3).noprw();
-}
-
-void namcos12_state::kartduel_h8iomap(address_map &map)
-{
-	s12h8iomap(map);
-	map(h8_device::ADC_0, h8_device::ADC_0).portr("BRAKE");
-	map(h8_device::ADC_1, h8_device::ADC_1).portr("GAS");
-	map(h8_device::ADC_2, h8_device::ADC_2).portr("STEER");
-}
-
 // Golgo 13 lightgun inputs
 
 uint16_t namcos12_state::s12_mcu_gun_h_r()
@@ -1698,14 +1643,6 @@ uint16_t namcos12_state::s12_mcu_gun_v_r()
 	return m_lightgun_io[1]->read();
 }
 
-void namcos12_state::golgo13_h8iomap(address_map &map)
-{
-	s12h8iomap(map);
-
-	map(h8_device::ADC_1, h8_device::ADC_1).r(FUNC(namcos12_state::s12_mcu_gun_h_r));
-	map(h8_device::ADC_2, h8_device::ADC_2).r(FUNC(namcos12_state::s12_mcu_gun_v_r));
-}
-
 void namcos12_state::init_namcos12()
 {
 	m_mainbank->configure_entries(0, memregion( "bankedroms" )->bytes() / 0x200000, memregion( "bankedroms" )->base(), 0x200000 );
@@ -1751,7 +1688,18 @@ void namcos12_state::namcos12_mobo(machine_config &config)
 	/* basic machine hardware */
 	H83002(config, m_sub, 16934400); // frequency based on research (superctr)
 	m_sub->set_addrmap(AS_PROGRAM, &namcos12_state::s12h8rwmap);
-	m_sub->set_addrmap(AS_IO, &namcos12_state::s12h8iomap);
+	m_sub->read_adc(0).set([]() -> u16 { return 0; });
+	m_sub->read_adc(1).set([]() -> u16 { return 0; });
+	m_sub->read_adc(2).set([]() -> u16 { return 0; });
+	m_sub->read_adc(3).set([]() -> u16 { return 0; });
+	m_sub->read_port6().set(FUNC(namcos12_state::s12_mcu_p6_r));
+	m_sub->read_port7().set_ioport("DSW");
+	m_sub->read_port8().set(FUNC(namcos12_state::s12_mcu_p8_r));
+	m_sub->write_port8().set([](u16) {});
+	m_sub->read_porta().set(FUNC(namcos12_state::s12_mcu_pa_r));
+	m_sub->write_porta().set(FUNC(namcos12_state::s12_mcu_pa_w));
+	m_sub->read_portb().set(FUNC(namcos12_state::s12_mcu_portB_r));
+	m_sub->write_portb().set(FUNC(namcos12_state::s12_mcu_portB_w));
 
 	NAMCO_SETTINGS(config, m_settings, 0);
 
@@ -1830,7 +1778,8 @@ void namcos12_boothack_state::golgo13(machine_config &config)
 	coh700(config);
 
 	/* basic machine hardware */
-	m_sub->set_addrmap(AS_IO, &namcos12_boothack_state::golgo13_h8iomap);
+	m_sub->read_adc(1).set(FUNC(namcos12_boothack_state::s12_mcu_gun_h_r));
+	m_sub->read_adc(2).set(FUNC(namcos12_boothack_state::s12_mcu_gun_v_r));
 }
 
 void namcos12_boothack_state::kartduel(machine_config &config)
@@ -1838,7 +1787,9 @@ void namcos12_boothack_state::kartduel(machine_config &config)
 	coh700(config);
 
 	/* basic machine hardware */
-	m_sub->set_addrmap(AS_IO, &namcos12_boothack_state::kartduel_h8iomap);
+	m_sub->read_adc(0).set_ioport("BRAKE");
+	m_sub->read_adc(1).set_ioport("GAS");
+	m_sub->read_adc(2).set_ioport("STEER");
 }
 
 #define JVSCLOCK    (XTAL(14'745'600))
@@ -1848,11 +1799,6 @@ void namcos12_state::jvsmap(address_map &map)
 	map(0xc000, 0xfb7f).ram();
 }
 
-void namcos12_state::jvsiomap(address_map &map)
-{
-}
-
-
 void namcos12_boothack_state::truckk(machine_config &config)
 {
 	coh700(config);
@@ -1861,7 +1807,6 @@ void namcos12_boothack_state::truckk(machine_config &config)
 
 	h83334_device &iocpu(H83334(config, "iocpu", JVSCLOCK));
 	iocpu.set_addrmap(AS_PROGRAM, &namcos12_boothack_state::jvsmap);
-	iocpu.set_addrmap(AS_IO, &namcos12_boothack_state::jvsiomap);
 
 	subdevice<h8_sci_device>("iocpu:sci0")->tx_handler().set("sub:sci0", FUNC(h8_sci_device::rx_w));
 	subdevice<h8_sci_device>("sub:sci0")->tx_handler().set("iocpu:sci0", FUNC(h8_sci_device::rx_w));
@@ -1899,15 +1844,6 @@ void namcos12_state::tdjvsmap(address_map &map)
 	map(0xc000, 0xfb7f).ram();
 }
 
-void namcos12_state::tdjvsiomap(address_map &map)
-{
-	map(h8_device::PORT_4, h8_device::PORT_4).rw(FUNC(namcos12_state::iob_p4_r), FUNC(namcos12_state::iob_p4_w));
-	map(h8_device::PORT_6, h8_device::PORT_6).r(FUNC(namcos12_state::iob_p6_r));
-	map(h8_device::ADC_0, h8_device::ADC_0).portr("STEER");
-	map(h8_device::ADC_1, h8_device::ADC_1).portr("BRAKE");
-	map(h8_device::ADC_2, h8_device::ADC_2).portr("GAS");
-}
-
 void namcos12_state::plarailjvsmap(address_map &map)
 {
 	map(0x0000, 0x3fff).rom().region("iocpu", 0);
@@ -1916,15 +1852,6 @@ void namcos12_state::plarailjvsmap(address_map &map)
 	map(0xc000, 0xfb7f).ram();
 }
 
-void namcos12_state::plarailjvsiomap(address_map &map)
-{
-	map(h8_device::PORT_4, h8_device::PORT_4).rw(FUNC(namcos12_state::iob_p4_r), FUNC(namcos12_state::iob_p4_w));
-	map(h8_device::PORT_6, h8_device::PORT_6).portr("SERVICE");
-	map(h8_device::ADC_0, h8_device::ADC_0).noprw();
-	map(h8_device::ADC_1, h8_device::ADC_1).noprw();
-	map(h8_device::ADC_2, h8_device::ADC_2).noprw();
-}
-
 void namcos12_boothack_state::technodr(machine_config &config)
 {
 	coh700(config);
@@ -1933,11 +1860,16 @@ void namcos12_boothack_state::technodr(machine_config &config)
 
 	// modify H8/3002 map to omit direct-connected controls
 	m_sub->set_addrmap(AS_PROGRAM, &namcos12_boothack_state::s12h8rwjvsmap);
-	m_sub->set_addrmap(AS_IO, &namcos12_boothack_state::s12h8jvsiomap);
+	m_sub->read_port8().set(FUNC(namcos12_boothack_state::s12_mcu_jvs_p8_r));
 
 	h83334_device &iocpu(H83334(config, "iocpu", JVSCLOCK));
 	iocpu.set_addrmap(AS_PROGRAM, &namcos12_boothack_state::tdjvsmap);
-	iocpu.set_addrmap(AS_IO, &namcos12_boothack_state::tdjvsiomap);
+	iocpu.read_adc(0).set_ioport("STEER");
+	iocpu.read_adc(1).set_ioport("BRAKE");
+	iocpu.read_adc(2).set_ioport("GAS");
+	iocpu.read_port4().set(FUNC(namcos12_boothack_state::iob_p4_r));
+	iocpu.write_port4().set(FUNC(namcos12_boothack_state::iob_p4_w));
+	iocpu.read_port6().set(FUNC(namcos12_boothack_state::iob_p6_r));
 
 	subdevice<h8_sci_device>("iocpu:sci0")->tx_handler().set("sub:sci0", FUNC(h8_sci_device::rx_w));
 	subdevice<h8_sci_device>("sub:sci0")->tx_handler().set("iocpu:sci0", FUNC(h8_sci_device::rx_w));
@@ -1953,11 +1885,28 @@ void namcos12_boothack_state::aplarail(machine_config &config)
 
 	// modify H8/3002 map to omit direct-connected controls
 	m_sub->set_addrmap(AS_PROGRAM, &namcos12_boothack_state::s12h8rwjvsmap);
-	m_sub->set_addrmap(AS_IO, &namcos12_boothack_state::s12h8railiomap);
+	m_sub->read_adc(0).set_ioport("LEVER");
+	m_sub->read_adc(1).set([]() -> u16 { return 0; });
+	m_sub->read_adc(2).set([]() -> u16 { return 0; });
+	m_sub->read_adc(3).set([]() -> u16 { return 0; });
+	m_sub->read_port6().set(FUNC(namcos12_boothack_state::s12_mcu_p6_r));
+	m_sub->read_port7().set_ioport("DSW");
+	m_sub->read_port8().set(FUNC(namcos12_boothack_state::s12_mcu_jvs_p8_r));
+	m_sub->write_port8().set([](u8) {});
+	m_sub->read_porta().set(FUNC(namcos12_boothack_state::s12_mcu_pa_r));
+	m_sub->write_porta().set(FUNC(namcos12_boothack_state::s12_mcu_pa_w));
+	m_sub->read_portb().set(FUNC(namcos12_boothack_state::s12_mcu_portB_r));
+	m_sub->write_portb().set(FUNC(namcos12_boothack_state::s12_mcu_portB_w));	
 
 	h83334_device &iocpu(H83334(config, "iocpu", JVSCLOCK));
 	iocpu.set_addrmap(AS_PROGRAM, &namcos12_boothack_state::plarailjvsmap);
-	iocpu.set_addrmap(AS_IO, &namcos12_boothack_state::plarailjvsiomap);
+	iocpu.read_adc(0).set([]() -> u16 { return 0; });
+	iocpu.read_adc(1).set([]() -> u16 { return 0; });
+	iocpu.read_adc(2).set([]() -> u16 { return 0; });
+	iocpu.read_adc(3).set([]() -> u16 { return 0; });
+	iocpu.read_port4().set(FUNC(namcos12_boothack_state::iob_p4_r));
+	iocpu.write_port4().set(FUNC(namcos12_boothack_state::iob_p4_w));
+	iocpu.read_port6().set_ioport("SERVICE");
 
 	subdevice<h8_sci_device>("iocpu:sci0")->tx_handler().set("sub:sci0", FUNC(h8_sci_device::rx_w));
 	subdevice<h8_sci_device>("sub:sci0")->tx_handler().set("iocpu:sci0", FUNC(h8_sci_device::rx_w));

src/mame/namco/namcos23.cpp

@@ -1747,9 +1747,7 @@ private:
 	void gmen_sh2_map(address_map &map);
 	void gorgon_map(address_map &map);
 	void s23_map(address_map &map);
-	void s23h8iomap(address_map &map);
 	void s23h8rwmap(address_map &map);
-	void s23iobrdiomap(address_map &map);
 	void s23iobrdmap(address_map &map);
 	void motoxgo_exio_map(address_map &map);
 	void timecrs2iobrdmap(address_map &map);
@@ -3320,20 +3318,6 @@ void namcos23_state::s23h8rwmap(address_map &map)
 }
 
 
-void namcos23_state::s23h8iomap(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(namcos23_state::mcu_p6_r), FUNC(namcos23_state::mcu_p6_w));
-	map(h8_device::PORT_8, h8_device::PORT_8).rw(FUNC(namcos23_state::mcu_p8_r), FUNC(namcos23_state::mcu_p8_w));
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(namcos23_state::mcu_pa_r), FUNC(namcos23_state::mcu_pa_w));
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(namcos23_state::mcu_pb_r), FUNC(namcos23_state::mcu_pb_w));
-	map(h8_device::ADC_0, h8_device::ADC_0).noprw();
-	map(h8_device::ADC_1, h8_device::ADC_1).noprw();
-	map(h8_device::ADC_2, h8_device::ADC_2).noprw();
-	map(h8_device::ADC_3, h8_device::ADC_3).noprw();
-}
-
-
-
 
 
 /***************************************************************************
@@ -3386,23 +3370,6 @@ void namcos23_state::s23iobrdmap(address_map &map)
 	map(0xc000, 0xfb7f).ram();
 }
 
-void namcos23_state::s23iobrdiomap(address_map &map)
-{
-	map(h8_device::PORT_4, h8_device::PORT_4).rw(FUNC(namcos23_state::iob_p4_r), FUNC(namcos23_state::iob_p4_w));
-	map(h8_device::PORT_5, h8_device::PORT_5).noprw();   // bit 2 = status LED to indicate transmitting packet to main
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(namcos23_state::iob_p6_r), FUNC(namcos23_state::iob_p6_w));
-	map(h8_device::PORT_8, h8_device::PORT_8).noprw();   // unknown - used on ASCA-5 only
-	map(h8_device::PORT_9, h8_device::PORT_9).noprw();   // unknown - used on ASCA-5 only
-	map(h8_device::ADC_0, h8_device::ADC_0).portr("ADC0");
-	map(h8_device::ADC_1, h8_device::ADC_1).portr("ADC1");
-	map(h8_device::ADC_2, h8_device::ADC_2).portr("ADC2");
-	map(h8_device::ADC_3, h8_device::ADC_3).portr("ADC3");
-	map(h8_device::ADC_4, h8_device::ADC_4).portr("ADC4");
-	map(h8_device::ADC_5, h8_device::ADC_5).portr("ADC5");
-	map(h8_device::ADC_6, h8_device::ADC_6).portr("ADC6");
-	map(h8_device::ADC_7, h8_device::ADC_7).portr("ADC7");
-}
-
 
 void namcos23_state::motoxgo_exio_map(address_map &map)
 {
@@ -3826,14 +3793,39 @@ void namcos23_state::gorgon(machine_config &config)
 
 	H83002(config, m_subcpu, H8CLOCK);
 	m_subcpu->set_addrmap(AS_PROGRAM, &namcos23_state::s23h8rwmap);
-	m_subcpu->set_addrmap(AS_IO, &namcos23_state::s23h8iomap);
+	m_subcpu->read_adc(0).set([]() -> u16 { return 0; });
+	m_subcpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_subcpu->read_adc(2).set([]() -> u16 { return 0; });
+	m_subcpu->read_adc(3).set([]() -> u16 { return 0; });
+	m_subcpu->read_port6().set(FUNC(namcos23_state::mcu_p6_r));
+	m_subcpu->write_port6().set(FUNC(namcos23_state::mcu_p6_w));
+	m_subcpu->read_port8().set(FUNC(namcos23_state::mcu_p8_r));
+	m_subcpu->write_port8().set(FUNC(namcos23_state::mcu_p8_w));
+	m_subcpu->read_porta().set(FUNC(namcos23_state::mcu_pa_r));
+	m_subcpu->write_porta().set(FUNC(namcos23_state::mcu_pa_w));
+	m_subcpu->read_portb().set(FUNC(namcos23_state::mcu_pb_r));
+	m_subcpu->write_portb().set(FUNC(namcos23_state::mcu_pb_w));
 
 	// Timer at 115200*16 for the jvs serial clock
 	m_subcpu->subdevice<h8_sci_device>("sci0")->set_external_clock_period(attotime::from_hz(JVSCLOCK/8));
 
 	H83334(config, m_iocpu, JVSCLOCK);
 	m_iocpu->set_addrmap(AS_PROGRAM, &namcos23_state::s23iobrdmap);
-	m_iocpu->set_addrmap(AS_IO, &namcos23_state::s23iobrdiomap);
+	m_iocpu->read_adc(0).set_ioport("ADC0");
+	m_iocpu->read_adc(1).set_ioport("ADC1");
+	m_iocpu->read_adc(2).set_ioport("ADC2");
+	m_iocpu->read_adc(3).set_ioport("ADC3");
+	m_iocpu->read_adc(4).set_ioport("ADC4");
+	m_iocpu->read_adc(5).set_ioport("ADC5");
+	m_iocpu->read_adc(6).set_ioport("ADC6");
+	m_iocpu->read_adc(7).set_ioport("ADC7");
+	m_iocpu->read_port4().set(FUNC(namcos23_state::iob_p4_r));
+	m_iocpu->write_port4().set(FUNC(namcos23_state::iob_p4_w));
+	m_iocpu->write_port5().set([](u8) {});   // bit 2 = status LED to indicate transmitting packet to main
+	m_iocpu->read_port6().set(FUNC(namcos23_state::iob_p6_r));
+	m_iocpu->write_port6().set(FUNC(namcos23_state::iob_p6_w));
+	m_iocpu->write_port8().set([](u8) {});   // unknown - used on ASCA-5 only
+	m_iocpu->write_port9().set([](u8) {});   // unknown - used on ASCA-5 only
 
 	m_iocpu->subdevice<h8_sci_device>("sci0")->tx_handler().set("subcpu:sci0", FUNC(h8_sci_device::rx_w));
 	m_subcpu->subdevice<h8_sci_device>("sci0")->tx_handler().set("iocpu:sci0", FUNC(h8_sci_device::rx_w));
@@ -3888,14 +3880,32 @@ void namcos23_state::s23(machine_config &config)
 
 	H83002(config, m_subcpu, H8CLOCK);
 	m_subcpu->set_addrmap(AS_PROGRAM, &namcos23_state::s23h8rwmap);
-	m_subcpu->set_addrmap(AS_IO, &namcos23_state::s23h8iomap);
+	m_subcpu->read_adc(0).set([]() -> u16 { return 0; });
+	m_subcpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_subcpu->read_adc(2).set([]() -> u16 { return 0; });
+	m_subcpu->read_adc(3).set([]() -> u16 { return 0; });
+	m_subcpu->read_port6().set(FUNC(namcos23_state::mcu_p6_r));
+	m_subcpu->write_port6().set(FUNC(namcos23_state::mcu_p6_w));
+	m_subcpu->read_port8().set(FUNC(namcos23_state::mcu_p8_r));
+	m_subcpu->write_port8().set(FUNC(namcos23_state::mcu_p8_w));
+	m_subcpu->read_porta().set(FUNC(namcos23_state::mcu_pa_r));
+	m_subcpu->write_porta().set(FUNC(namcos23_state::mcu_pa_w));
+	m_subcpu->read_portb().set(FUNC(namcos23_state::mcu_pb_r));
+	m_subcpu->write_portb().set(FUNC(namcos23_state::mcu_pb_w));
 
 	// Timer at 115200*16 for the jvs serial clock
 	m_subcpu->subdevice<h8_sci_device>("sci0")->set_external_clock_period(attotime::from_hz(JVSCLOCK/8));
 
 	H83334(config, m_iocpu, JVSCLOCK);
 	m_iocpu->set_addrmap(AS_PROGRAM, &namcos23_state::s23iobrdmap);
-	m_iocpu->set_addrmap(AS_IO, &namcos23_state::s23iobrdiomap);
+	m_iocpu->read_adc(0).set_ioport("ADC0");
+	m_iocpu->read_adc(1).set_ioport("ADC1");
+	m_iocpu->read_adc(2).set_ioport("ADC2");
+	m_iocpu->read_adc(3).set_ioport("ADC3");
+	m_iocpu->read_adc(4).set_ioport("ADC4");
+	m_iocpu->read_adc(5).set_ioport("ADC5");
+	m_iocpu->read_adc(6).set_ioport("ADC6");
+	m_iocpu->read_adc(7).set_ioport("ADC7");
 
 	m_iocpu->subdevice<h8_sci_device>("sci0")->tx_handler().set("subcpu:sci0", FUNC(h8_sci_device::rx_w));
 	m_subcpu->subdevice<h8_sci_device>("sci0")->tx_handler().set("iocpu:sci0", FUNC(h8_sci_device::rx_w));

src/mame/nichibutsu/hrdvd.cpp

@@ -125,7 +125,6 @@ public:
 	void general_init(int patchaddress, int patchvalue);
 	void hrdvd(machine_config &config);
 	void hrdvd_map(address_map &map);
-	void hrdvd_sub_io_map(address_map &map);
 	void hrdvd_sub_map(address_map &map);
 
 	static void dvdrom_config(device_t *device);
@@ -275,14 +274,6 @@ void hrdvd_state::hrdvd_sub_map(address_map &map)
 }
 
 
-void hrdvd_state::hrdvd_sub_io_map(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(hrdvd_state::p6_r), FUNC(hrdvd_state::p6_w));
-	map(h8_device::PORT_A, h8_device::PORT_A).w (FUNC(hrdvd_state::pa_w));
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(hrdvd_state::pb_r), FUNC(hrdvd_state::pb_w));
-}
-
-
 static INPUT_PORTS_START( hrdvd )
 	PORT_START("KEY.0")
 	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_START1 )
@@ -490,7 +481,11 @@ void hrdvd_state::hrdvd(machine_config &config)
 
 	H83002(config, m_subcpu, 27_MHz_XTAL/2);
 	m_subcpu->set_addrmap(AS_PROGRAM, &hrdvd_state::hrdvd_sub_map);
-	m_subcpu->set_addrmap(AS_IO, &hrdvd_state::hrdvd_sub_io_map);
+	m_subcpu->read_port6().set(FUNC(hrdvd_state::p6_r));
+	m_subcpu->write_port6().set(FUNC(hrdvd_state::p6_w));
+	m_subcpu->write_porta().set(FUNC(hrdvd_state::pa_w));
+	m_subcpu->read_portb().set(FUNC(hrdvd_state::pb_r));
+	m_subcpu->write_portb().set(FUNC(hrdvd_state::pb_w));
 
 	m_maincpu->tx0_handler().set(*m_subcpu->subdevice<h8_sci_device>("sci0"), FUNC(h8_sci_device::rx_w));
 	m_subcpu->subdevice<h8_sci_device>("sci0")->tx_handler().set(m_maincpu, FUNC(tmp68301_device::rx0_w));

src/mame/sega/flashbeats.cpp

@@ -47,7 +47,6 @@ public:
 
 	void flashbeats(machine_config &config);
 	void flashbeats_map(address_map &map);
-	void flashbeats_io_map(address_map &map);
 	void main_scsp_map(address_map &map);
 	void scsp_mem(address_map &map);
 
@@ -106,11 +105,6 @@ void flashbeats_state::flashbeats_map(address_map &map)
 	map(0xa10000, 0xa10fff).ram();
 }
 
-void flashbeats_state::flashbeats_io_map(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(flashbeats_state::p6_r), FUNC(flashbeats_state::p6_w));
-}
-
 void flashbeats_state::main_scsp_map(address_map &map)
 {
 	map(0x000000, 0x0fffff).ram().share("sound_ram");
@@ -128,7 +122,8 @@ void flashbeats_state::flashbeats(machine_config &config)
 	/* basic machine hardware */
 	H83007(config, m_maincpu, 16_MHz_XTAL); // 16 MHz oscillator next to chip, also 16 MHz causes SCI0 and 1 rates to be 31250 (MIDI)
 	m_maincpu->set_addrmap(AS_PROGRAM, &flashbeats_state::flashbeats_map);
-	m_maincpu->set_addrmap(AS_IO, &flashbeats_state::flashbeats_io_map);
+	m_maincpu->read_port6().set(FUNC(flashbeats_state::p6_r));
+	m_maincpu->write_port6().set(FUNC(flashbeats_state::p6_w));
 
 	M68000(config, m_scspcpu, 11289600);
 	m_scspcpu->set_addrmap(AS_PROGRAM, &flashbeats_state::main_scsp_map);

src/mame/seta/seta2.cpp

@@ -92,7 +92,6 @@ funcube series:
 #include "emu.h"
 #include "seta2.h"
 
-#include "cpu/h8/h83006.h"
 #include "cpu/m68000/mcf5206e.h"
 #include "machine/mcf5206e.h"
 #include "machine/nvram.h"
@@ -906,13 +905,13 @@ uint16_t funcube_state::coins_r()
 void funcube_state::funcube_debug_outputs()
 {
 #ifdef MAME_DEBUG
-//  popmessage("LED: %02x OUT: %02x", (int)*m_funcube_leds, (int)*m_outputs);
+//  popmessage("LED: %02x OUT: %02x", m_funcube_leds, m_outputs);
 #endif
 }
 
 void funcube_state::leds_w(uint16_t data)
 {
-	*m_funcube_leds = data;
+	m_funcube_leds = data;
 
 	m_leds[0] = BIT(~data, 0); // win lamp (red)
 	m_leds[1] = BIT(~data, 1); // win lamp (green)
@@ -929,12 +928,12 @@ void funcube_state::leds_w(uint16_t data)
 uint16_t funcube_state::outputs_r()
 {
 	// Bits 1,2,3 read
-	return *m_outputs;
+	return m_outputs;
 }
 
 void funcube_state::outputs_w(uint16_t data)
 {
-	*m_outputs = data;
+	m_outputs = data;
 
 	// Bits 0,1,3 written
 
@@ -954,25 +953,6 @@ uint16_t funcube_state::battery_r()
 	return ioport("BATTERY")->read() ? 0x40 : 0x00;
 }
 
-// cabinet linking on sci0
-void funcube_state::funcube_sub_io(address_map &map)
-{
-	map(h8_device::PORT_7, h8_device::PORT_7).r(FUNC(funcube_state::coins_r));
-	map(h8_device::PORT_4, h8_device::PORT_4).r(FUNC(funcube_state::battery_r));
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(funcube_state::outputs_r), FUNC(funcube_state::outputs_w)).share("outputs");
-	map(h8_device::PORT_B, h8_device::PORT_B).w(FUNC(funcube_state::leds_w)).share("funcube_leds");
-}
-
-void funcube_state::funcube2_sub_io(address_map &map)
-{
-	map(h8_device::PORT_7, h8_device::PORT_7).r(FUNC(funcube_state::coins_r));
-	map(h8_device::PORT_4, h8_device::PORT_4).noprw();  // unused
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(funcube_state::outputs_r), FUNC(funcube_state::outputs_w)).share("outputs");
-	map(h8_device::PORT_B, h8_device::PORT_B).w(FUNC(funcube_state::leds_w)).share("funcube_leds");
-}
-
-
-
 
 /***************************************************************************
 
@@ -2477,12 +2457,17 @@ void funcube_state::machine_start()
 	seta2_state::machine_start();
 	save_item(NAME(m_coin_start_cycles));
 	save_item(NAME(m_hopper_motor));
+	save_item(NAME(m_outputs));
+	save_item(NAME(m_funcube_leds));
+
 }
 
 void funcube_state::machine_reset()
 {
 	m_coin_start_cycles = 0;
 	m_hopper_motor = 0;
+	m_outputs = 0;
+	m_funcube_leds = 0;
 }
 
 void funcube_state::funcube(machine_config &config)
@@ -2493,7 +2478,11 @@ void funcube_state::funcube(machine_config &config)
 
 	H83007(config, m_sub, FUNCUBE_SUB_CPU_CLOCK);
 	m_sub->set_addrmap(AS_PROGRAM, &funcube_state::funcube_sub_map);
-	m_sub->set_addrmap(AS_IO, &funcube_state::funcube_sub_io);
+	m_sub->read_port4().set(FUNC(funcube_state::battery_r));
+	m_sub->read_port7().set(FUNC(funcube_state::coins_r));
+	m_sub->read_porta().set(FUNC(funcube_state::outputs_r));
+	m_sub->write_porta().set(FUNC(funcube_state::outputs_w));
+	m_sub->write_portb().set(FUNC(funcube_state::leds_w));
 
 	MCF5206E_PERIPHERAL(config, "maincpu_onboard", 0, m_maincpu);
 
@@ -2531,7 +2520,7 @@ void funcube_state::funcube2(machine_config &config)
 	funcube(config);
 	m_maincpu->set_addrmap(AS_PROGRAM, &funcube_state::funcube2_map);
 
-	m_sub->set_addrmap(AS_IO, &funcube_state::funcube2_sub_io);
+	m_sub->read_port4().set([]() -> u8 { return 0; }); // unused
 
 	// video hardware
 	m_screen->set_visarea(0x0, 0x140-1, 0x00, 0xf0-1);

src/mame/seta/seta2.h

@@ -7,6 +7,7 @@
 
 
 #include "cpu/m68000/tmp68301.h"
+#include "cpu/h8/h83006.h"
 #include "machine/eepromser.h"
 #include "machine/intelfsh.h"
 #include "machine/ticket.h"
@@ -115,7 +116,7 @@ protected:
 	void x1_map(address_map &map);
 
 	required_device<cpu_device> m_maincpu;
-	optional_device<cpu_device> m_sub;
+	optional_device<h83007_device> m_sub;
 	required_device<gfxdecode_device> m_gfxdecode;
 	required_device<screen_device> m_screen;
 	required_device<palette_device> m_palette;
@@ -167,8 +168,6 @@ class funcube_state : public seta2_state
 public:
 	funcube_state(const machine_config &mconfig, device_type type, const char *tag)
 		: seta2_state(mconfig, type, tag)
-		, m_outputs(*this, "outputs")
-		, m_funcube_leds(*this, "funcube_leds")
 	{ }
 
 	void funcube(machine_config &config);
@@ -195,15 +194,12 @@ private:
 	TIMER_DEVICE_CALLBACK_MEMBER(funcube_interrupt);
 
 	void funcube2_map(address_map &map);
-	void funcube2_sub_io(address_map &map);
 	void funcube_map(address_map &map);
-	void funcube_sub_io(address_map &map);
 	void funcube_sub_map(address_map &map);
 
 	void funcube_debug_outputs();
 
-	required_shared_ptr<uint16_t> m_outputs;
-	required_shared_ptr<uint16_t> m_funcube_leds;
+	uint16_t m_outputs, m_funcube_leds;
 	uint64_t m_coin_start_cycles = 0;
 	uint8_t m_hopper_motor = 0;
 };

src/mame/taito/invqix.cpp

@@ -155,11 +155,10 @@ private:
 
 	void vctl_w(uint16_t data);
 
-	void invqix_io_map(address_map &map);
 	void invqix_prg_map(address_map &map);
 
 	// devices
-	required_device<cpu_device> m_maincpu;
+	required_device<h8s2394_device> m_maincpu;
 	required_device<eeprom_serial_93cxx_device> m_eeprom;
 	required_shared_ptr<uint16_t> m_vram;
 
@@ -285,18 +284,6 @@ void invqix_state::invqix_prg_map(address_map &map)
 	map(0x620004, 0x620005).w(FUNC(invqix_state::vctl_w));
 }
 
-void invqix_state::invqix_io_map(address_map &map)
-{
-	map(h8_device::PORT_1, h8_device::PORT_1).portr("P1");
-	map(h8_device::PORT_2, h8_device::PORT_2).portr("SYSTEM").nopw();
-	map(h8_device::PORT_3, h8_device::PORT_3).rw(FUNC(invqix_state::port3_r), FUNC(invqix_state::port3_w));
-	map(h8_device::PORT_4, h8_device::PORT_4).portr("P4");
-	map(h8_device::PORT_5, h8_device::PORT_5).rw(FUNC(invqix_state::port5_r), FUNC(invqix_state::port5_w));
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(invqix_state::port6_r), FUNC(invqix_state::port6_w));
-	map(h8_device::PORT_A, h8_device::PORT_A).r(FUNC(invqix_state::porta_r));
-	map(h8_device::PORT_G, h8_device::PORT_G).r(FUNC(invqix_state::portg_r)).nopw();
-}
-
 static INPUT_PORTS_START( invqix )
 	PORT_START("SYSTEM")
 	PORT_SERVICE_NO_TOGGLE( 0x01, IP_ACTIVE_LOW )
@@ -333,9 +320,21 @@ void invqix_state::invqix(machine_config &config)
 {
 	H8S2394(config, m_maincpu, XTAL(20'000'000));
 	m_maincpu->set_addrmap(AS_PROGRAM, &invqix_state::invqix_prg_map);
-	m_maincpu->set_addrmap(AS_IO, &invqix_state::invqix_io_map);
 	m_maincpu->set_vblank_int("screen", FUNC(invqix_state::irq1_line_hold));
 	m_maincpu->set_periodic_int(FUNC(invqix_state::irq0_line_hold), attotime::from_hz(60));
+	m_maincpu->read_port1().set_ioport("P1");
+	m_maincpu->read_port2().set_ioport("SYSTEM");
+	m_maincpu->write_port2().set([](u8) {});
+	m_maincpu->read_port3().set(FUNC(invqix_state::port3_r));
+	m_maincpu->write_port3().set(FUNC(invqix_state::port3_w));
+	m_maincpu->read_port4().set_ioport("P4");
+	m_maincpu->read_port5().set(FUNC(invqix_state::port5_r));
+	m_maincpu->write_port5().set(FUNC(invqix_state::port5_w));
+	m_maincpu->read_port6().set(FUNC(invqix_state::port6_r));
+	m_maincpu->write_port6().set(FUNC(invqix_state::port6_w));
+	m_maincpu->read_porta().set(FUNC(invqix_state::porta_r));
+	m_maincpu->read_portg().set(FUNC(invqix_state::portg_r));
+	m_maincpu->write_portg().set([](u8) {});
 
 	/* video hardware */
 	screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));

src/mame/yamaha/ymmu100.cpp

@@ -301,7 +301,6 @@ private:
 	void pg_w(u16 data);
 
 	virtual void machine_start() override;
-	void mu100_iomap(address_map &map);
 	void mu100_map(address_map &map);
 	void swp30_map(address_map &map);
 };
@@ -671,26 +670,6 @@ void mu100_state::pg_w(u16 data)
 	logerror("pbsel3 %d\n", data & 1);
 }
 
-void mu100_state::mu100_iomap(address_map &map)
-{
-	map(h8_device::PORT_1, h8_device::PORT_1).rw(FUNC(mu100_state::p1_r), FUNC(mu100_state::p1_w));
-	map(h8_device::PORT_2, h8_device::PORT_2).w(FUNC(mu100_state::p2_w));
-	map(h8_device::PORT_3, h8_device::PORT_3).w(FUNC(mu100_state::p3_w));
-	map(h8_device::PORT_5, h8_device::PORT_5).w(FUNC(mu100_state::p5_w));
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(mu100_state::p6_r), FUNC(mu100_state::p6_w));
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(mu100_state::pa_r), FUNC(mu100_state::pa_w));
-	map(h8_device::PORT_F, h8_device::PORT_F).w(FUNC(mu100_state::pf_w));
-	map(h8_device::PORT_G, h8_device::PORT_G).w(FUNC(mu100_state::pg_w));
-	map(h8_device::ADC_0, h8_device::ADC_0).r(FUNC(mu100_state::adc_ar_r));
-	map(h8_device::ADC_1, h8_device::ADC_1).r(FUNC(mu100_state::adc_zero_r));
-	map(h8_device::ADC_2, h8_device::ADC_2).r(FUNC(mu100_state::adc_al_r));
-	map(h8_device::ADC_1, h8_device::ADC_3).r(FUNC(mu100_state::adc_zero_r));
-	map(h8_device::ADC_4, h8_device::ADC_4).r(FUNC(mu100_state::adc_midisw_r));
-	map(h8_device::ADC_5, h8_device::ADC_5).r(FUNC(mu100_state::adc_zero_r));
-	map(h8_device::ADC_6, h8_device::ADC_6).r(FUNC(mu100_state::adc_battery_r));
-	map(h8_device::ADC_7, h8_device::ADC_7).r(FUNC(mu100_state::adc_type_r));
-}
-
 void mu100_state::swp30_map(address_map &map)
 {
 	map(0x000000*4, 0x200000*4-1).rom().region("swp30",         0).mirror(4*0x200000);
@@ -702,7 +681,25 @@ void mu100_state::mu100(machine_config &config)
 {
 	H8S2655(config, m_maincpu, 16_MHz_XTAL);
 	m_maincpu->set_addrmap(AS_PROGRAM, &mu100_state::mu100_map);
-	m_maincpu->set_addrmap(AS_IO, &mu100_state::mu100_iomap);
+	m_maincpu->read_adc(0).set(FUNC(mu100_state::adc_ar_r));
+	m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(2).set(FUNC(mu100_state::adc_al_r));
+	m_maincpu->read_adc(3).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(4).set(FUNC(mu100_state::adc_midisw_r));
+	m_maincpu->read_adc(5).set([]() -> u16 { return 0; });
+	m_maincpu->read_adc(6).set(FUNC(mu100_state::adc_battery_r));
+	m_maincpu->read_adc(7).set(FUNC(mu100_state::adc_type_r));
+	m_maincpu->read_port1().set(FUNC(mu100_state::p1_r));
+	m_maincpu->write_port1().set(FUNC(mu100_state::p1_w));
+	m_maincpu->write_port2().set(FUNC(mu100_state::p2_w));
+	m_maincpu->write_port3().set(FUNC(mu100_state::p3_w));
+	m_maincpu->write_port5().set(FUNC(mu100_state::p5_w));
+	m_maincpu->read_port6().set(FUNC(mu100_state::p6_r));
+	m_maincpu->write_port6().set(FUNC(mu100_state::p6_w));
+	m_maincpu->read_porta().set(FUNC(mu100_state::pa_r));
+	m_maincpu->write_porta().set(FUNC(mu100_state::pa_w));
+	m_maincpu->write_portf().set(FUNC(mu100_state::pf_w));
+	m_maincpu->write_portg().set(FUNC(mu100_state::pg_w));
 
 	MULCD(config, m_lcd);
 

src/mame/yamaha/ymmu5.cpp

@@ -48,7 +48,6 @@ private:
 	output_finder<2, 8, 8, 5> m_outputs;
 
 	void mu5_map(address_map &map);
-	void mu5_io_map(address_map &map);
 	void ymw258_map(address_map &map);
 
 	u8 m_lcd_ctrl = 0U;
@@ -72,18 +71,6 @@ void mu5_state::mu5_map(address_map &map)
 	map(0x400000, 0x400007).rw(m_ymw258, FUNC(multipcm_device::read), FUNC(multipcm_device::write)).umask16(0xffff);
 }
 
-void mu5_state::mu5_io_map(address_map &map)
-{
-	map(h8_device::PORT_4, h8_device::PORT_4).lr8(NAME([this]() -> u8 { return m_matrixsel; }));
-	map(h8_device::PORT_4, h8_device::PORT_4).lw8(NAME([this](u8 data) { m_matrixsel = data; }));
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(mu5_state::lcd_ctrl_r), FUNC(mu5_state::lcd_ctrl_w));
-	map(h8_device::PORT_7, h8_device::PORT_7).r(FUNC(mu5_state::matrix_r));
-	map(h8_device::PORT_A, h8_device::PORT_A).nopr();
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(mu5_state::lcd_data_r), FUNC(mu5_state::lcd_data_w));
-
-	map(h8_device::ADC_7, h8_device::ADC_7).lr8(NAME([]() -> u8 { return 0xff; })); // battery level
-}
-
 void mu5_state::ymw258_map(address_map &map)
 {
 	map(0x000000, 0x1fffff).rom();
@@ -225,7 +212,15 @@ void mu5_state::mu5(machine_config &config)
 	/* basic machine hardware */
 	H83002(config, m_maincpu, 10_MHz_XTAL); // clock verified by schematics
 	m_maincpu->set_addrmap(AS_PROGRAM, &mu5_state::mu5_map);
-	m_maincpu->set_addrmap(AS_IO, &mu5_state::mu5_io_map);
+	m_maincpu->read_adc(7).set([]() -> u8 { return 0xff; }); // Bettery level
+	m_maincpu->read_port4().set([this]() -> u8 { return m_matrixsel; });
+	m_maincpu->write_port4().set([this](u8 data) { m_matrixsel = data; });
+	m_maincpu->read_port6().set(FUNC(mu5_state::lcd_ctrl_r));
+	m_maincpu->write_port6().set(FUNC(mu5_state::lcd_ctrl_w));
+	m_maincpu->read_port7().set(FUNC(mu5_state::matrix_r));
+	m_maincpu->read_porta().set([]() -> u8 { return 0; });
+	m_maincpu->read_portb().set(FUNC(mu5_state::lcd_data_r));
+	m_maincpu->write_portb().set(FUNC(mu5_state::lcd_data_w));
 
 	SPEAKER(config, "lspeaker").front_left();
 	SPEAKER(config, "rspeaker").front_right();

src/mame/yamaha/ymmu50.cpp

@@ -94,7 +94,6 @@ private:
 	void pc_w(u16 data);
 	u16 pc_r();
 
-	void mu50_iomap(address_map &map);
 	void mu50_map(address_map &map);
 
 	virtual void machine_start() override;
@@ -209,28 +208,26 @@ u16 mu50_state::pc_r()
 	return res;
 }
 
-
-void mu50_state::mu50_iomap(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(mu50_state::p6_r), FUNC(mu50_state::p6_w));
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(mu50_state::pa_r), FUNC(mu50_state::pa_w));
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(mu50_state::pb_r), FUNC(mu50_state::pb_w));
-	map(h8_device::PORT_C, h8_device::PORT_C).rw(FUNC(mu50_state::pc_r), FUNC(mu50_state::pc_w));
-	map(h8_device::ADC_0, h8_device::ADC_0).r(FUNC(mu50_state::adc_ar_r));
-	map(h8_device::ADC_1, h8_device::ADC_1).lr16([]() -> u16 { return 0; }, "gnd");
-	map(h8_device::ADC_2, h8_device::ADC_2).r(FUNC(mu50_state::adc_al_r));
-	map(h8_device::ADC_3, h8_device::ADC_3).lr16([]() -> u16 { return 0; }, "gnd");
-	map(h8_device::ADC_4, h8_device::ADC_4).r(FUNC(mu50_state::adc_midisw_r));
-	map(h8_device::ADC_5, h8_device::ADC_6).lr16([]() -> u16 { return 0; }, "gnd");
-	map(h8_device::ADC_6, h8_device::ADC_6).r(FUNC(mu50_state::adc_battery_r));
-	map(h8_device::ADC_7, h8_device::ADC_7).lr16([]() -> u16 { return 0; }, "gnd");
-}
-
 void mu50_state::mu50(machine_config &config)
 {
 	H83003(config, m_mu50cpu, 12_MHz_XTAL);
 	m_mu50cpu->set_addrmap(AS_PROGRAM, &mu50_state::mu50_map);
-	m_mu50cpu->set_addrmap(AS_IO, &mu50_state::mu50_iomap);
+	m_mu50cpu->read_adc(0).set(FUNC(mu50_state::adc_ar_r));
+	m_mu50cpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_mu50cpu->read_adc(2).set(FUNC(mu50_state::adc_al_r));
+	m_mu50cpu->read_adc(3).set([]() -> u16 { return 0; });
+	m_mu50cpu->read_adc(4).set(FUNC(mu50_state::adc_midisw_r));
+	m_mu50cpu->read_adc(5).set([]() -> u16 { return 0; });
+	m_mu50cpu->read_adc(6).set(FUNC(mu50_state::adc_battery_r));
+	m_mu50cpu->read_adc(7).set([]() -> u16 { return 0; });
+	m_mu50cpu->read_port6().set(FUNC(mu50_state::p6_r));
+	m_mu50cpu->write_port6().set(FUNC(mu50_state::p6_w));
+	m_mu50cpu->read_porta().set(FUNC(mu50_state::pa_r));
+	m_mu50cpu->write_porta().set(FUNC(mu50_state::pa_w));
+	m_mu50cpu->read_portb().set(FUNC(mu50_state::pb_r));
+	m_mu50cpu->write_portb().set(FUNC(mu50_state::pb_w));
+	m_mu50cpu->read_portc().set(FUNC(mu50_state::pc_r));
+	m_mu50cpu->write_portc().set(FUNC(mu50_state::pc_w));
 
 	MULCD(config, m_lcd);
 

src/mame/yamaha/ymmu80.cpp

@@ -214,7 +214,6 @@ private:
 	u16 pb_r();
 
 	virtual void machine_start() override;
-	void mu80_iomap(address_map &map);
 	void mu80_map(address_map &map);
 };
 
@@ -325,26 +324,24 @@ u16 mu80_state::pa_r()
 	return cur_pa;
 }
 
-void mu80_state::mu80_iomap(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(mu80_state::p6_r), FUNC(mu80_state::p6_w));
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(mu80_state::pa_r), FUNC(mu80_state::pa_w));
-	map(h8_device::PORT_B, h8_device::PORT_B).rw(FUNC(mu80_state::pb_r), FUNC(mu80_state::pb_w));
-	map(h8_device::ADC_0, h8_device::ADC_0).r(FUNC(mu80_state::adc_ar_r));
-	map(h8_device::ADC_1, h8_device::ADC_1).r(FUNC(mu80_state::adc_zero_r));
-	map(h8_device::ADC_2, h8_device::ADC_2).r(FUNC(mu80_state::adc_al_r));
-	map(h8_device::ADC_3, h8_device::ADC_3).r(FUNC(mu80_state::adc_zero_r));
-	map(h8_device::ADC_4, h8_device::ADC_4).r(FUNC(mu80_state::adc_midisw_r));
-	map(h8_device::ADC_5, h8_device::ADC_6).r(FUNC(mu80_state::adc_zero_r));
-	map(h8_device::ADC_6, h8_device::ADC_6).r(FUNC(mu80_state::adc_battery_r));
-	map(h8_device::ADC_7, h8_device::ADC_7).r(FUNC(mu80_state::adc_zero_r)); // inputmod from the gate array
-}
-
 void mu80_state::mu80(machine_config &config)
 {
 	H83002(config, m_mu80cpu, 12_MHz_XTAL);
 	m_mu80cpu->set_addrmap(AS_PROGRAM, &mu80_state::mu80_map);
-	m_mu80cpu->set_addrmap(AS_IO, &mu80_state::mu80_iomap);
+	m_mu80cpu->read_adc(0).set(FUNC(mu80_state::adc_ar_r));
+	m_mu80cpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_mu80cpu->read_adc(2).set(FUNC(mu80_state::adc_al_r));
+	m_mu80cpu->read_adc(3).set([]() -> u16 { return 0; });
+	m_mu80cpu->read_adc(4).set(FUNC(mu80_state::adc_midisw_r));
+	m_mu80cpu->read_adc(5).set([]() -> u16 { return 0; });
+	m_mu80cpu->read_adc(6).set(FUNC(mu80_state::adc_battery_r));
+	m_mu80cpu->read_adc(7).set([]() -> u16 { return 0; }); // inputmod from the gate array
+	m_mu80cpu->read_port6().set(FUNC(mu80_state::p6_r));
+	m_mu80cpu->write_port6().set(FUNC(mu80_state::p6_w));
+	m_mu80cpu->read_porta().set(FUNC(mu80_state::pa_r));
+	m_mu80cpu->write_porta().set(FUNC(mu80_state::pa_w));
+	m_mu80cpu->read_portb().set(FUNC(mu80_state::pb_r));
+	m_mu80cpu->write_portb().set(FUNC(mu80_state::pb_w));
 
 	MULCD(config, m_lcd);
 

src/mame/yamaha/ymqy70.cpp

@@ -110,7 +110,6 @@ private:
 	void pa_w(u16 data) { if (data) sw_sel = data; }
 	u8 sw_in();
 	u16 adc_bkupbat_r() { return 0x2a0; }
-	void io_map(address_map &map);
 	void mem_map(address_map &map);
 	void lcd_map(address_map &map);
 	void lcd_palette(palette_device &palette) const;
@@ -132,16 +131,6 @@ u8 qy70_state::sw_in()
 	return m_switches[idx]->read();
 }
 
-void qy70_state::io_map(address_map &map)
-{
-	map(h8_device::PORT_A, h8_device::PORT_A).w(FUNC(qy70_state::pa_w));
-	// PORT_B bit 0 1MHz output for Mac serial, bit 1 Rec LED, bit 2 Play LED,
-	//        bit 3 lcdc reset, bit 4 GND, bit 5 subcpu SBSY, bit 6-7 subcpu
-	// ADC_0  Power battery voltage
-	// ADC_2  Host type select: 5V Mac, 3.33V PC-1, 1.66V PC-2, 0V MIDI
-	map(h8_device::ADC_4, h8_device::ADC_4).r(FUNC(qy70_state::adc_bkupbat_r));
-}
-
 void qy70_state::mem_map(address_map &map)
 {
 	map(0x000000, 0x1fffff).rom().region("mainprog", 0);
@@ -167,7 +156,12 @@ void qy70_state::qy70(machine_config &config)
 {
 	H83002(config, m_maincpu, 10_MHz_XTAL);
 	m_maincpu->set_addrmap(AS_PROGRAM, &qy70_state::mem_map);
-	m_maincpu->set_addrmap(AS_IO, &qy70_state::io_map);
+	// ADC_0  Power battery voltage
+	// ADC_2  Host type select: 5V Mac, 3.33V PC-1, 1.66V PC-2, 0V MIDI
+	m_maincpu->read_adc(4).set(FUNC(qy70_state::adc_bkupbat_r));
+	m_maincpu->write_porta().set(FUNC(qy70_state::pa_w));
+	// PORT_B bit 0 1MHz output for Mac serial, bit 1 Rec LED, bit 2 Play LED,
+	//        bit 3 lcdc reset, bit 4 GND, bit 5 subcpu SBSY, bit 6-7 subcpu
 
 	NVRAM(config, "userdata.nv", nvram_device::DEFAULT_NONE);
 	NVRAM(config, "workdata.nv", nvram_device::DEFAULT_NONE);

src/mame/yamaha/ymvl70.cpp

@@ -104,7 +104,6 @@ private:
 	u16 pc_r();
 
 	virtual void machine_start() override;
-	void vl70_iomap(address_map &map);
 	void vl70_map(address_map &map);
 };
 
@@ -219,27 +218,25 @@ u16 vl70_state::pa_r()
 	return cur_pa;
 }
 
-void vl70_state::vl70_iomap(address_map &map)
-{
-	map(h8_device::PORT_6, h8_device::PORT_6).rw(FUNC(vl70_state::p6_r), FUNC(vl70_state::p6_w));
-	map(h8_device::PORT_A, h8_device::PORT_A).rw(FUNC(vl70_state::pa_r), FUNC(vl70_state::pa_w));
-	map(h8_device::PORT_B, h8_device::PORT_B).w(FUNC(vl70_state::pb_w));
-	map(h8_device::PORT_C, h8_device::PORT_C).rw(FUNC(vl70_state::pc_r), FUNC(vl70_state::pc_w));
-	map(h8_device::ADC_0, h8_device::ADC_0).r(FUNC(vl70_state::adc_breath_r));
-	map(h8_device::ADC_1, h8_device::ADC_6).r(FUNC(vl70_state::adc_zero_r));
-	map(h8_device::ADC_2, h8_device::ADC_2).r(FUNC(vl70_state::adc_midisw_r));
-	map(h8_device::ADC_3, h8_device::ADC_6).r(FUNC(vl70_state::adc_zero_r));
-	map(h8_device::ADC_4, h8_device::ADC_4).r(FUNC(vl70_state::adc_battery_r));
-	map(h8_device::ADC_5, h8_device::ADC_6).r(FUNC(vl70_state::adc_zero_r));
-	map(h8_device::ADC_6, h8_device::ADC_6).r(FUNC(vl70_state::adc_zero_r));
-	map(h8_device::ADC_7, h8_device::ADC_7).r(FUNC(vl70_state::adc_zero_r));
-}
-
 void vl70_state::vl70(machine_config &config)
 {
 	H83003(config, m_vl70cpu, 10_MHz_XTAL);
 	m_vl70cpu->set_addrmap(AS_PROGRAM, &vl70_state::vl70_map);
-	m_vl70cpu->set_addrmap(AS_IO, &vl70_state::vl70_iomap);
+	m_vl70cpu->read_adc(0).set(FUNC(vl70_state::adc_breath_r));
+	m_vl70cpu->read_adc(1).set([]() -> u16 { return 0; });
+	m_vl70cpu->read_adc(2).set(FUNC(vl70_state::adc_midisw_r));
+	m_vl70cpu->read_adc(3).set([]() -> u16 { return 0; });
+	m_vl70cpu->read_adc(4).set(FUNC(vl70_state::adc_battery_r));
+	m_vl70cpu->read_adc(5).set([]() -> u16 { return 0; });
+	m_vl70cpu->read_adc(6).set([]() -> u16 { return 0; });
+	m_vl70cpu->read_adc(7).set([]() -> u16 { return 0; });
+	m_vl70cpu->read_port6().set(FUNC(vl70_state::p6_r));
+	m_vl70cpu->write_port6().set(FUNC(vl70_state::p6_w));
+	m_vl70cpu->read_porta().set(FUNC(vl70_state::pa_r));
+	m_vl70cpu->write_porta().set(FUNC(vl70_state::pa_w));
+	m_vl70cpu->write_portb().set(FUNC(vl70_state::pb_w));
+	m_vl70cpu->read_portc().set(FUNC(vl70_state::pc_r));
+	m_vl70cpu->write_portc().set(FUNC(vl70_state::pc_w));
 
 	MULCD(config, m_lcd);