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https://github.com/holub/mame
synced 2025-06-06 12:53:46 +03:00
lgtz80.cpp: Identify CPU as KL5C80A12; hook up input ports and interrupt
This commit is contained in:
AJR
parent
c75845b1ef
commit
ce44d4bf34
@ -12,19 +12,21 @@ scratched off square 44-pin chip, stickered ASIC 4
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12 MHz XTAL (near ASIC 2)
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7.3728 MHz XTAL (near ASIC 4)
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U6295 sound chip
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HM86171-80 RAM (near CPU ROM)
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HM86171-80 RAMDAC (near CPU ROM)
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6x M5M5256DVP (1 near CPU ROM, 5 near GFX ROMs)
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The two dumped games use PCBs with different layout, however the components appear
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to be the same or at least same from different manufacturers.
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TODO: everything. Exact CPU model isn't identified, but it's surely a Z80 derivative.
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TODO: everything. "ASIC 1" is probably a KL5C80A12 CPU, though its on-chip peripherals are mostly unused.
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fruitcat currently runs off the rails due to seemingly missing code, but fortuitously recovers.
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*/
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#include "emu.h"
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#include "cpu/z80/z80.h"
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#include "cpu/z80/kl5c80a12.h"
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#include "sound/okim6295.h"
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#include "emupal.h"
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@ -44,7 +46,8 @@ public:
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m_control(0)
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{ }
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void lgtz80(machine_config &config) ATTR_COLD;
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void fruitcat(machine_config &config) ATTR_COLD;
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void arthurkn(machine_config &config) ATTR_COLD;
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void init_arthurkn() ATTR_COLD;
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void init_fruitcat() ATTR_COLD;
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@ -55,17 +58,22 @@ protected:
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virtual void video_start() override ATTR_COLD;
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private:
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required_device<cpu_device> m_maincpu;
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required_device<kl5c80a12_device> m_maincpu;
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uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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uint8_t control_r();
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void control_w(uint8_t data);
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void vblank_nmi_w(int state);
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void p0_w(u8 data);
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u8 control_r();
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void control_w(u8 data);
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u8 e0_r();
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void program_map(address_map &map) ATTR_COLD;
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void io_map(address_map &map) ATTR_COLD;
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void fruitcat_io_map(address_map &map) ATTR_COLD;
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void arthurkn_io_map(address_map &map) ATTR_COLD;
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uint8_t m_control;
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u8 m_control;
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};
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@ -76,7 +84,7 @@ void lgtz80_state::machine_start()
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void lgtz80_state::machine_reset()
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{
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m_control = 0;
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control_w(0);
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}
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uint32_t lgtz80_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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@ -89,63 +97,91 @@ void lgtz80_state::video_start()
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}
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uint8_t lgtz80_state::control_r()
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void lgtz80_state::p0_w(u8 data)
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{
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logerror("%s: p0_w(%02X)\n", machine().describe_context(), data);
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}
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u8 lgtz80_state::control_r()
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{
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return m_control;
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}
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void lgtz80_state::control_w(uint8_t data)
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void lgtz80_state::control_w(u8 data)
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{
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// Bit 7 = NMI mask
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logerror("%s: control_w(%02X)\n", machine().describe_context(), data);
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m_control = data;
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if (!BIT(data, 7))
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m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
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}
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u8 lgtz80_state::e0_r()
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{
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// arthurkn: protection?
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return 0x6e;
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}
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void lgtz80_state::vblank_nmi_w(int state)
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{
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if (state && BIT(m_control, 7))
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m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
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}
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void lgtz80_state::program_map(address_map &map)
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{
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map(0x0000, 0x7fff).rom();
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map(0x8000, 0x9fff).ram(); // NVRAM?
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map(0xb000, 0xbfff).rom(); // not correct
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map(0xf800, 0xffff).ram();
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map(0x00000, 0x1ffff).rom();
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map(0x28000, 0x29fff).ram(); // NVRAM?
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map(0x2a000, 0x2bfff).ram(); // arthurkn needs to copy code to RAM here, but fruitcat doesn't initialize it!
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map(0x4c000, 0x4efff).ram(); // video RAM?
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}
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void lgtz80_state::io_map(address_map &map)
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void lgtz80_state::fruitcat_io_map(address_map &map)
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{
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map.global_mask(0xff);
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map(0x80, 0x82).nopw(); // RAMDAC?
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map(0xc0, 0xc0).rw(FUNC(lgtz80_state::control_r), FUNC(lgtz80_state::control_w));
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}
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void lgtz80_state::arthurkn_io_map(address_map &map)
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{
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map.global_mask(0xff);
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map(0x88, 0x88).nopw();
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map(0xb0, 0xb2).nopw(); // RAMDAC?
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map(0xc0, 0xc0).rw(FUNC(lgtz80_state::control_r), FUNC(lgtz80_state::control_w));
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map(0xe0, 0xe0).r(FUNC(lgtz80_state::e0_r));
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}
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static INPUT_PORTS_START( fruitcat )
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PORT_START("IN0")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_START("IN1")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_START("IN2")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_START("IN3")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
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// no DSW on PCB
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INPUT_PORTS_END
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@ -156,12 +192,15 @@ static GFXDECODE_START( gfx_lgtz80 )
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GFXDECODE_END
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void lgtz80_state::lgtz80(machine_config &config)
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void lgtz80_state::fruitcat(machine_config &config)
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{
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Z80(config, m_maincpu, 12_MHz_XTAL / 4 ); // exact CPU model and divider not verified
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KL5C80A12(config, m_maincpu, 12_MHz_XTAL); // exact CPU model and divider not verified
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m_maincpu->set_addrmap(AS_PROGRAM, &lgtz80_state::program_map);
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m_maincpu->set_addrmap(AS_IO, &lgtz80_state::io_map);
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// m_maincpu->set_vblank_int("screen", FUNC(lgtz80_state::irq0_line_hold));
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m_maincpu->set_addrmap(AS_IO, &lgtz80_state::fruitcat_io_map);
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m_maincpu->out_p0_callback().set(FUNC(lgtz80_state::p0_w));
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m_maincpu->in_p1_callback().set_ioport("IN1");
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m_maincpu->in_p2_callback().set_ioport("IN2");
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m_maincpu->in_p3_callback().set_ioport("IN3");
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screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); // TODO
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screen.set_refresh_hz(60);
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@ -169,6 +208,7 @@ void lgtz80_state::lgtz80(machine_config &config)
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screen.set_size(64*8, 64*8);
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screen.set_visarea(0, 64*8-1, 0, 32*8-1);
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screen.set_screen_update(FUNC(lgtz80_state::screen_update));
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screen.screen_vblank().set(FUNC(lgtz80_state::vblank_nmi_w));
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GFXDECODE(config, "gfxdecode", "palette", gfx_lgtz80);
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@ -179,6 +219,12 @@ void lgtz80_state::lgtz80(machine_config &config)
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OKIM6295(config, "oki", 12_MHz_XTAL / 12, okim6295_device::PIN7_HIGH).add_route(ALL_OUTPUTS, "mono", 1.0); // pin 7 and clock not verified
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}
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void lgtz80_state::arthurkn(machine_config &config)
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{
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fruitcat(config);
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m_maincpu->set_addrmap(AS_IO, &lgtz80_state::arthurkn_io_map);
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}
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ROM_START( fruitcat )
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ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 )
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@ -214,7 +260,7 @@ ROM_END
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void lgtz80_state::init_fruitcat()
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{
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// Encryption involves a permutation of odd-numbered data lines, conditional on address lines
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uint8_t *rom = memregion("maincpu")->base();
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u8 *rom = memregion("maincpu")->base();
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for (int i = 0; i < 0x20000; i++)
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{
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switch (i & 0x7c0)
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@ -329,7 +375,7 @@ void lgtz80_state::init_fruitcat()
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void lgtz80_state::init_arthurkn()
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{
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// Encryption involves a permutation of odd-numbered data lines, conditional on address lines
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uint8_t *rom = memregion("maincpu")->base();
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u8 *rom = memregion("maincpu")->base();
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for (int i = 0; i < 0x20000; i++)
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{
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switch (i & 0x7c0)
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@ -444,5 +490,5 @@ void lgtz80_state::init_arthurkn()
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} // anonymous namespace
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GAME( 2003?, fruitcat, 0, lgtz80, fruitcat, lgtz80_state, init_fruitcat, ROT0, "LGT", "Fruit Cat (v2.00)", MACHINE_IS_SKELETON )
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GAME( 200?, arthurkn, 0, lgtz80, fruitcat, lgtz80_state, init_arthurkn, ROT0, "LGT", "Arthur's Knights", MACHINE_IS_SKELETON )
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GAME( 2003?, fruitcat, 0, fruitcat, fruitcat, lgtz80_state, init_fruitcat, ROT0, "LGT", "Fruit Cat (v2.00)", MACHINE_IS_SKELETON )
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GAME( 200?, arthurkn, 0, arthurkn, fruitcat, lgtz80_state, init_arthurkn, ROT0, "LGT", "Arthur's Knights", MACHINE_IS_SKELETON )
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