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m_owner cleanup (nw)

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This commit is contained in:
AJR 2017-05-25 12:08:57 -04:00
parent a7fbc354c0
commit ce5641bb8c
6 changed files with 189 additions and 189 deletions
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8
src/devices/machine/68561mpcc.cpp
View File

@ -471,7 +471,7 @@ void mpcc_device::update_serial()
stop_bits_t stop_bits = get_stop_bits();
parity_t parity = get_parity();
LOGSETUP(" %s() %s Setting data frame %d+%d%c%s\n", FUNCNAME, m_owner->tag(), 1,
LOGSETUP(" %s() %s Setting data frame %d+%d%c%s\n", FUNCNAME, owner()->tag(), 1,
data_bits, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O',
stop_bits == STOP_BITS_1 ? "1" : (stop_bits == STOP_BITS_2 ? "2" : "1.5"));
@ -554,7 +554,7 @@ void mpcc_device::tra_callback()
// Otherwise we don't know why we are called...
else
{
logerror("%s %s Failed to transmit\n", FUNCNAME, m_owner->tag());
logerror("%s %s Failed to transmit\n", FUNCNAME, owner()->tag());
}
}
@ -834,7 +834,7 @@ READ8_MEMBER( mpcc_device::read )
case 0x1d: data = do_brdr2(); break;
case 0x1e: data = do_ccr(); break;
case 0x1f: data = do_ecr(); break;
default: logerror("%s:%s invalid register accessed: %02x\n", m_owner->tag(), tag(), offset);
default: logerror("%s:%s invalid register accessed: %02x\n", owner()->tag(), tag(), offset);
}
LOGR(" * %s Reg %02x -> %02x \n", tag(), offset, data);
return data;
@ -870,7 +870,7 @@ WRITE8_MEMBER( mpcc_device::write )
case 0x1d: do_brdr2(data); break;
case 0x1e: do_ccr(data); break;
case 0x1f: do_ecr(data); break;
default: logerror("%s:%s invalid register accessed: %02x\n", m_owner->tag(), tag(), offset);
default: logerror("%s:%s invalid register accessed: %02x\n", owner()->tag(), tag(), offset);
}
}

36
src/devices/machine/scnxx562.cpp
View File

@ -84,7 +84,7 @@ DONE (x) (p=partly) NMOS CMOS
// MACROS / CONSTANTS
//**************************************************************************
/* Useful temporary debug printout format */
// printf("TAG %lld %s%s Data:%d\n", machine().firstcpu->total_cycles(), __PRETTY_FUNCTION__, m_owner->tag(), data);
// printf("TAG %lld %s%s Data:%d\n", machine().firstcpu->total_cycles(), __PRETTY_FUNCTION__, owner()->tag(), data);
#define LOG_GENERAL (1U << 0)
#define LOG_R (1U << 1)
@ -950,7 +950,7 @@ void duscc_channel::tra_callback()
{
int db = transmit_register_get_data_bit();
LOGR(LLFORMAT " %s() \"%s \"Channel %c transmit data bit %d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, db);
LOGR(LLFORMAT " %s() \"%s \"Channel %c transmit data bit %d\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, db);
// transmit data
if (m_index == duscc_device::CHANNEL_A)
@ -960,7 +960,7 @@ void duscc_channel::tra_callback()
}
else
{
LOG(LLFORMAT " %s() \"%s \"Channel %c Failed to transmit \n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index);
LOG(LLFORMAT " %s() \"%s \"Channel %c Failed to transmit \n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index);
logerror("%s Channel %c Failed to transmit\n", FUNCNAME, 'A' + m_index);
}
}
@ -1000,7 +1000,7 @@ void duscc_channel::rcv_callback()
{
if (m_rcv == 1)
{
LOG(LLFORMAT " %s() \"%s \"Channel %c received data bit %d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_rxd);
LOG(LLFORMAT " %s() \"%s \"Channel %c received data bit %d\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_rxd);
receive_register_update_bit(m_rxd);
}
}
@ -1016,7 +1016,7 @@ void duscc_channel::rcv_complete()
receive_register_extract();
data = get_received_char();
LOGINT(LLFORMAT " %s() \"%s \"Channel %c Received Data %c\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, data);
LOGINT(LLFORMAT " %s() \"%s \"Channel %c Received Data %c\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, data);
receive_data(data);
}
@ -1050,7 +1050,7 @@ int duscc_channel::get_tx_clock_mode()
void duscc_channel::set_rts(int state)
{
LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index);
LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, owner()->tag(), 'A' + m_index);
if (m_index == duscc_device::CHANNEL_A)
m_uart->m_out_rtsa_cb(state);
else
@ -2216,7 +2216,7 @@ uint8_t duscc_channel::read(offs_t &offset)
{
uint8_t data = 0;
int reg = (offset | m_a7) & ~0x20; // Add extended rgisters and remove the channel B bit from offset
LOG("\"%s\" %s: %c : Register read '%02x' <- [%02x]", m_owner->tag(), FUNCNAME, 'A' + m_index, data, reg );
LOG("\"%s\" %s: %c : Register read '%02x' <- [%02x]", owner()->tag(), FUNCNAME, 'A' + m_index, data, reg );
LOGR(" * %c Reg %02x -> %02x \n", 'A' + m_index, reg, data);
switch (reg)
{
@ -2254,7 +2254,7 @@ uint8_t duscc_channel::read(offs_t &offset)
logerror("%s: %c : Unsupported RRx register:%02x\n", FUNCNAME, 'A' + m_index, reg);
}
LOGR("%s \"%s\": %c : Register R%d read '%02x'\n", FUNCNAME, m_owner->tag(), 'A' + m_index, reg, data);
LOGR("%s \"%s\": %c : Register R%d read '%02x'\n", FUNCNAME, owner()->tag(), 'A' + m_index, reg, data);
return data;
}
@ -2266,8 +2266,8 @@ void duscc_channel::write(uint8_t data, offs_t &offset)
{
int reg = (offset | m_a7) & ~0x20; // Add extended rgisters and remove the channel B bit from offset
LOGSETUP(" * %s%c Reg %02x <- %02x \n", m_owner->tag(), 'A' + m_index, reg, data);
LOG("\"%s\" %s: %c : Register write '%02x' -> [%02x]", m_owner->tag(), FUNCNAME, 'A' + m_index, data, reg );
LOGSETUP(" * %s%c Reg %02x <- %02x \n", owner()->tag(), 'A' + m_index, reg, data);
LOG("\"%s\" %s: %c : Register write '%02x' -> [%02x]", owner()->tag(), FUNCNAME, 'A' + m_index, data, reg );
switch (reg)
{
case REG_CMR1: do_dusccreg_cmr1_w(data); break;
@ -2359,7 +2359,7 @@ void duscc_channel::m_tx_fifo_rp_step()
void duscc_channel::receive_data(uint8_t data)
{
LOG("\"%s\": %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data);
LOG("\"%s\": %c : Receive Data Byte '%02x'\n", owner()->tag(), 'A' + m_index, data);
if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) ))
{
@ -2404,7 +2404,7 @@ void duscc_channel::receive_data(uint8_t data)
WRITE_LINE_MEMBER( duscc_channel::cts_w )
{
LOG("\"%s\" %s: %c : CTS %u\n", m_owner->tag(), FUNCNAME, 'A' + m_index, state);
LOG("\"%s\" %s: %c : CTS %u\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
if (m_cts != state)
{
@ -2434,7 +2434,7 @@ WRITE_LINE_MEMBER( duscc_channel::cts_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( duscc_channel::dcd_w )
{
LOG("\"%s\" %s: %c : DCD %u - not implemented\n", m_owner->tag(), FUNCNAME, 'A' + m_index, state);
LOG("\"%s\" %s: %c : DCD %u - not implemented\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
#if 0
if (m_dcd != state)
@ -2458,7 +2458,7 @@ WRITE_LINE_MEMBER( duscc_channel::dcd_w )
WRITE_LINE_MEMBER( duscc_channel::ri_w )
{
LOG("\"%s\" %s: %c : RI %u - not implemented\n", m_owner->tag(), FUNCNAME, 'A' + m_index, state);
LOG("\"%s\" %s: %c : RI %u - not implemented\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
#if 0
if (m_ri != state)
{
@ -2473,7 +2473,7 @@ WRITE_LINE_MEMBER( duscc_channel::ri_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( duscc_channel::sync_w )
{
LOG("\"%s\" %s: %c : SYNC %u - not implemented\n", m_owner->tag(), FUNCNAME, 'A' + m_index, state);
LOG("\"%s\" %s: %c : SYNC %u - not implemented\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
}
//-------------------------------------------------
@ -2481,7 +2481,7 @@ WRITE_LINE_MEMBER( duscc_channel::sync_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( duscc_channel::rxc_w )
{
LOG("\"%s\" %s: %c : RXC %u - not implemented\n", m_owner->tag(), FUNCNAME, 'A' + m_index, state);
LOG("\"%s\" %s: %c : RXC %u - not implemented\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
}
//-------------------------------------------------
@ -2489,7 +2489,7 @@ WRITE_LINE_MEMBER( duscc_channel::rxc_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( duscc_channel::txc_w )
{
LOG("\"%s\" %s: %c : TXC %u - not implemented\n", m_owner->tag(), FUNCNAME, 'A' + m_index, state);
LOG("\"%s\" %s: %c : TXC %u - not implemented\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
}
//-------------------------------------------------
@ -2511,7 +2511,7 @@ void duscc_channel::update_serial()
else
parity = PARITY_NONE;
LOG(LLFORMAT " %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, 1,
LOG(LLFORMAT " %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, 1,
data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2);
set_data_frame(1, data_bit_count, parity, stop_bits);

96
src/devices/machine/z80dart.cpp
View File

@ -598,7 +598,7 @@ void z80dart_channel::tra_complete()
{
if ((m_wr[5] & WR5_TX_ENABLE) && !(m_wr[5] & WR5_SEND_BREAK) && !(m_rr[0] & RR0_TX_BUFFER_EMPTY))
{
LOG("Z80DART \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data);
LOG("Z80DART \"%s\" Channel %c : Transmit Data Byte '%02x'\n", owner()->tag(), 'A' + m_index, m_tx_data);
transmit_register_setup(m_tx_data);
@ -769,7 +769,7 @@ uint8_t z80dart_channel::control_read()
break;
}
//LOG("Z80DART \"%s\" Channel %c : Control Register Read '%02x'\n", m_owner->tag(), 'A' + m_index, data);
//LOG("Z80DART \"%s\" Channel %c : Control Register Read '%02x'\n", owner()->tag(), 'A' + m_index, data);
return data;
}
@ -784,7 +784,7 @@ void z80dart_channel::control_write(uint8_t data)
int reg = m_wr[0] & WR0_REGISTER_MASK;
uint8_t prev = m_wr[reg];
LOG("Z80DART \"%s\" Channel %c : Control Register Write '%02x'\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80DART \"%s\" Channel %c : Control Register Write '%02x'\n", owner()->tag(), 'A' + m_index, data);
// write data to selected register
if (reg < 6)
@ -802,12 +802,12 @@ void z80dart_channel::control_write(uint8_t data)
switch (data & WR0_COMMAND_MASK)
{
case WR0_NULL:
LOG("Z80DART \"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Null\n", owner()->tag(), 'A' + m_index);
break;
case WR0_SEND_ABORT:
LOG("Z80DART \"%s\" Channel %c : Send Abort\n", m_owner->tag(), 'A' + m_index);
logerror("Z80DART \"%s\" Channel %c : unsupported command: Send Abort\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Send Abort\n", owner()->tag(), 'A' + m_index);
logerror("Z80DART \"%s\" Channel %c : unsupported command: Send Abort\n", owner()->tag(), 'A' + m_index);
break;
case WR0_RESET_EXT_STATUS:
@ -820,36 +820,36 @@ void z80dart_channel::control_write(uint8_t data)
m_rx_rr0_latch = 0;
LOG("Z80DART \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Reset External/Status Interrupt\n", owner()->tag(), 'A' + m_index);
break;
case WR0_CHANNEL_RESET:
// channel reset
LOG("Z80DART \"%s\" Channel %c : Channel Reset\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Channel Reset\n", owner()->tag(), 'A' + m_index);
device_reset();
break;
case WR0_ENABLE_INT_NEXT_RX:
// enable interrupt on next receive character
LOG("Z80DART \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", owner()->tag(), 'A' + m_index);
m_rx_first = 1;
break;
case WR0_RESET_TX_INT:
// reset transmitter interrupt pending
LOG("Z80DART \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index);
logerror("Z80DART \"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", owner()->tag(), 'A' + m_index);
logerror("Z80DART \"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", owner()->tag(), 'A' + m_index);
break;
case WR0_ERROR_RESET:
// error reset
LOG("Z80DART \"%s\" Channel %c : Error Reset\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Error Reset\n", owner()->tag(), 'A' + m_index);
m_rr[1] &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR);
break;
case WR0_RETURN_FROM_INT:
// return from interrupt
LOG("Z80DART \"%s\" Channel %c : Return from Interrupt\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Return from Interrupt\n", owner()->tag(), 'A' + m_index);
m_uart->z80daisy_irq_reti();
if((m_uart->m_variant == z80dart_device::TYPE_I8274) || (m_uart->m_variant == z80dart_device::TYPE_UPD7201))
{
@ -866,29 +866,29 @@ void z80dart_channel::control_write(uint8_t data)
break;
case 1:
LOG("Z80DART \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait");
LOG("Z80DART \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit");
LOG("Z80DART \"%s\" Channel %c : External Interrupt Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Transmit Interrupt Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Status Affects Vector %u\n", owner()->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Wait/Ready Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Wait/Ready Function %s\n", owner()->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait");
LOG("Z80DART \"%s\" Channel %c : Wait/Ready on %s\n", owner()->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit");
switch (data & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_DISABLE:
LOG("Z80DART \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Receiver Interrupt Disabled\n", owner()->tag(), 'A' + m_index);
break;
case WR1_RX_INT_FIRST:
LOG("Z80DART \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Receiver Interrupt on First Character\n", owner()->tag(), 'A' + m_index);
break;
case WR1_RX_INT_ALL_PARITY:
LOG("Z80DART \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", owner()->tag(), 'A' + m_index);
break;
case WR1_RX_INT_ALL:
LOG("Z80DART \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index);
LOG("Z80DART \"%s\" Channel %c : Receiver Interrupt on All Characters\n", owner()->tag(), 'A' + m_index);
break;
}
@ -905,34 +905,34 @@ void z80dart_channel::control_write(uint8_t data)
m_rr[2] = m_wr[2];
}
m_uart->check_interrupts();
LOG("Z80DART \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80DART \"%s\" Channel %c : Interrupt Vector %02x\n", owner()->tag(), 'A' + m_index, data);
break;
case 3:
LOG("Z80DART \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length());
LOG("Z80DART \"%s\" Channel %c : Receiver Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Auto Enables %u\n", owner()->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Receiver Bits/Character %u\n", owner()->tag(), 'A' + m_index, get_rx_word_length());
if (data != prev)
update_serial();
break;
case 4:
LOG("Z80DART \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd");
LOG("Z80DART \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits()));
LOG("Z80DART \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode());
LOG("Z80DART \"%s\" Channel %c : Parity Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Parity %s\n", owner()->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd");
LOG("Z80DART \"%s\" Channel %c : Stop Bits %s\n", owner()->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits()));
LOG("Z80DART \"%s\" Channel %c : Clock Mode %uX\n", owner()->tag(), 'A' + m_index, get_clock_mode());
if (data != prev)
update_serial();
break;
case 5:
LOG("Z80DART \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length());
LOG("Z80DART \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Transmitter Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Transmitter Bits/Character %u\n", owner()->tag(), 'A' + m_index, get_tx_word_length());
LOG("Z80DART \"%s\" Channel %c : Send Break %u\n", owner()->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Request to Send %u\n", owner()->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0);
LOG("Z80DART \"%s\" Channel %c : Data Terminal Ready %u\n", owner()->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0);
if (data != prev)
update_serial();
@ -954,12 +954,12 @@ void z80dart_channel::control_write(uint8_t data)
break;
case 6:
LOG("Z80DART \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80DART \"%s\" Channel %c : Transmit Sync %02x\n", owner()->tag(), 'A' + m_index, data);
m_sync = (m_sync & 0xff00) | data;
break;
case 7:
LOG("Z80DART \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80DART \"%s\" Channel %c : Receive Sync %02x\n", owner()->tag(), 'A' + m_index, data);
m_sync = (data << 8) | (m_sync & 0xff);
break;
}
@ -989,7 +989,7 @@ uint8_t z80dart_channel::data_read()
}
}
LOG("Z80DART \"%s\" Channel %c : Data Register Read '%02x'\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80DART \"%s\" Channel %c : Data Register Read '%02x'\n", owner()->tag(), 'A' + m_index, data);
return data;
}
@ -1005,7 +1005,7 @@ void z80dart_channel::data_write(uint8_t data)
if ((m_wr[5] & WR5_TX_ENABLE) && is_transmit_register_empty())
{
LOG("Z80DART \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data);
LOG("Z80DART \"%s\" Channel %c : Transmit Data Byte '%02x'\n", owner()->tag(), 'A' + m_index, m_tx_data);
transmit_register_setup(m_tx_data);
@ -1022,7 +1022,7 @@ void z80dart_channel::data_write(uint8_t data)
m_rr[1] &= ~RR1_ALL_SENT;
LOG("Z80DART \"%s\" Channel %c : Data Register Write '%02x'\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80DART \"%s\" Channel %c : Data Register Write '%02x'\n", owner()->tag(), 'A' + m_index, data);
}
@ -1032,7 +1032,7 @@ void z80dart_channel::data_write(uint8_t data)
void z80dart_channel::receive_data(uint8_t data)
{
LOG("Z80DART \"%s\" Channel %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80DART \"%s\" Channel %c : Receive Data Byte '%02x'\n", owner()->tag(), 'A' + m_index, data);
if (m_rx_data_fifo.full())
{
@ -1092,7 +1092,7 @@ void z80dart_channel::receive_data(uint8_t data)
WRITE_LINE_MEMBER( z80dart_channel::cts_w )
{
LOG("Z80DART \"%s\" Channel %c : CTS %u\n", m_owner->tag(), 'A' + m_index, state);
LOG("Z80DART \"%s\" Channel %c : CTS %u\n", owner()->tag(), 'A' + m_index, state);
if (m_cts != state)
{
@ -1131,7 +1131,7 @@ WRITE_LINE_MEMBER( z80dart_channel::cts_w )
WRITE_LINE_MEMBER( z80dart_channel::dcd_w )
{
LOG("Z80DART \"%s\" Channel %c : DCD %u\n", m_owner->tag(), 'A' + m_index, state);
LOG("Z80DART \"%s\" Channel %c : DCD %u\n", owner()->tag(), 'A' + m_index, state);
if (m_dcd != state)
{
@ -1169,7 +1169,7 @@ WRITE_LINE_MEMBER( z80dart_channel::dcd_w )
WRITE_LINE_MEMBER( z80dart_channel::ri_w )
{
LOG("Z80DART \"%s\" Channel %c : RI %u\n", m_owner->tag(), 'A' + m_index, state);
LOG("Z80DART \"%s\" Channel %c : RI %u\n", owner()->tag(), 'A' + m_index, state);
if (m_ri != state)
{
@ -1202,7 +1202,7 @@ WRITE_LINE_MEMBER( z80dart_channel::ri_w )
WRITE_LINE_MEMBER( z80dart_channel::sync_w )
{
LOG("Z80DART \"%s\" Channel %c : SYNC %u\n", m_owner->tag(), 'A' + m_index, state);
LOG("Z80DART \"%s\" Channel %c : SYNC %u\n", owner()->tag(), 'A' + m_index, state);
}
@ -1212,7 +1212,7 @@ WRITE_LINE_MEMBER( z80dart_channel::sync_w )
WRITE_LINE_MEMBER( z80dart_channel::rxc_w )
{
//LOG("Z80DART \"%s\" Channel %c : Receiver Clock Pulse\n", m_owner->tag(), m_index + 'A');
//LOG("Z80DART \"%s\" Channel %c : Receiver Clock Pulse\n", owner()->tag(), m_index + 'A');
int clocks = get_clock_mode();
if (clocks == 1)
rx_clock_w(state);
@ -1234,7 +1234,7 @@ WRITE_LINE_MEMBER( z80dart_channel::rxc_w )
WRITE_LINE_MEMBER( z80dart_channel::txc_w )
{
//LOG("Z80DART \"%s\" Channel %c : Transmitter Clock Pulse\n", m_owner->tag(), m_index + 'A');
//LOG("Z80DART \"%s\" Channel %c : Transmitter Clock Pulse\n", owner()->tag(), m_index + 'A');
int clocks = get_clock_mode();
if (clocks == 1)
tx_clock_w(state);

126
src/devices/machine/z80scc.cpp
View File

@ -1037,7 +1037,7 @@ void z80scc_channel::device_timer(emu_timer &timer, device_timer_id id, int para
//int brconst = m_wr13 << 8 | m_wr12 | 1; // If the counter is 1 the effect is passthrough ehh?! To avoid div0...
if (m_wr14 & WR14_BRG_ENABLE)
{
// int rate = m_owner->clock() / brconst;
// int rate = owner()->clock() / brconst;
// attotime attorate = attotime::from_hz(rate);
// timer.adjust(attorate, id, attorate);
txc_w(m_brg_counter & 1);
@ -1070,7 +1070,7 @@ void z80scc_channel::tra_callback()
{
if (!(m_wr5 & WR5_TX_ENABLE))
{
LOG(LLFORMAT " %s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOG(LLFORMAT " %s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// transmit mark
if (m_index == z80scc_device::CHANNEL_A)
m_uart->m_out_txda_cb(1);
@ -1079,7 +1079,7 @@ void z80scc_channel::tra_callback()
}
else if (m_wr5 & WR5_SEND_BREAK)
{
LOG(LLFORMAT " %s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOG(LLFORMAT " %s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// transmit break
if (m_index == z80scc_device::CHANNEL_A)
m_uart->m_out_txda_cb(0);
@ -1090,7 +1090,7 @@ void z80scc_channel::tra_callback()
{
int db = transmit_register_get_data_bit();
LOG(LLFORMAT " %s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5);
LOG(LLFORMAT " %s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, db, m_wr5);
// transmit data
if (m_index == z80scc_device::CHANNEL_A)
m_uart->m_out_txda_cb(db);
@ -1099,8 +1099,8 @@ void z80scc_channel::tra_callback()
}
else
{
LOG(LLFORMAT " %s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, m_owner->tag(), 'A' + m_index);
LOG(LLFORMAT " %s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, owner()->tag(), 'A' + m_index);
}
}
@ -1124,7 +1124,7 @@ void z80scc_channel::tra_complete()
if ( (m_rr0 & RR0_TX_BUFFER_EMPTY) == 0 || // Takes care of the NMOS/CMOS 1 slot TX FIFO
m_tx_fifo_rp != m_tx_fifo_wp) // or there are more characters to send in a longer FIFO.
{
LOGTX(" %s() %s %c done sending, loading data from fifo:%02x '%c'\n", FUNCNAME, m_owner->tag(), 'A' + m_index,
LOGTX(" %s() %s %c done sending, loading data from fifo:%02x '%c'\n", FUNCNAME, owner()->tag(), 'A' + m_index,
m_tx_data_fifo[m_tx_fifo_rp], isascii(m_tx_data_fifo[m_tx_fifo_rp]) ? m_tx_data_fifo[m_tx_fifo_rp] : ' ');
transmit_register_setup(m_tx_data_fifo[m_tx_fifo_rp]); // Reload the shift register
m_tx_fifo_rp_step();
@ -1132,7 +1132,7 @@ void z80scc_channel::tra_complete()
}
else
{
LOGTX(" %s() %s %c done sending, setting all sent bit\n", FUNCNAME, m_owner->tag(), 'A' + m_index);
LOGTX(" %s() %s %c done sending, setting all sent bit\n", FUNCNAME, owner()->tag(), 'A' + m_index);
m_rr1 |= RR1_ALL_SENT;
// when the RTS bit is reset, the _RTS output goes high after the transmitter empties
@ -1156,7 +1156,7 @@ void z80scc_channel::tra_complete()
}
else if (m_wr5 & WR5_SEND_BREAK)
{
LOG(LLFORMAT " %s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOG(LLFORMAT " %s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// transmit break
if (m_index == z80scc_device::CHANNEL_A)
m_uart->m_out_txda_cb(0);
@ -1165,7 +1165,7 @@ void z80scc_channel::tra_complete()
}
else
{
LOG(LLFORMAT " %s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOG(LLFORMAT " %s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// transmit mark
if (m_index == z80scc_device::CHANNEL_A)
m_uart->m_out_txda_cb(1);
@ -1183,14 +1183,14 @@ void z80scc_channel::rcv_callback()
{
if (m_wr3 & WR3_RX_ENABLE)
{
LOG(LLFORMAT " %s() \"%s \"Channel %c receive data bit %d m_wr3:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_rxd, m_wr3);
LOG(LLFORMAT " %s() \"%s \"Channel %c receive data bit %d m_wr3:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_rxd, m_wr3);
receive_register_update_bit(m_rxd);
}
#if 1
else
{
LOG(LLFORMAT " %s() \"%s \"Channel %c Received Data Bit but receiver is disabled\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index);
logerror("%s \"%s \"Channel %c Received data dit but receiver is disabled\n", FUNCNAME, m_owner->tag(), 'A' + m_index);
LOG(LLFORMAT " %s() \"%s \"Channel %c Received Data Bit but receiver is disabled\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index);
logerror("%s \"%s \"Channel %c Received data dit but receiver is disabled\n", FUNCNAME, owner()->tag(), 'A' + m_index);
}
#endif
}
@ -1206,7 +1206,7 @@ void z80scc_channel::rcv_complete()
receive_register_extract();
data = get_received_char();
LOG(LLFORMAT " %s() \"%s \"Channel %c Received Data %c\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, data);
LOG(LLFORMAT " %s() \"%s \"Channel %c Received Data %c\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, data);
receive_data(data);
#if START_BIT_HUNT
m_rcv_mode = RCV_SEEKING;
@ -1246,7 +1246,7 @@ TODO:
*/
void z80scc_channel::set_rts(int state)
{
LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index);
LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, owner()->tag(), 'A' + m_index);
if (m_index == z80scc_device::CHANNEL_A)
m_uart->m_out_rtsa_cb(state);
else
@ -1255,7 +1255,7 @@ void z80scc_channel::set_rts(int state)
void z80scc_channel::update_rts()
{
// LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index);
// LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, owner()->tag(), 'A' + m_index);
if (m_wr5 & WR5_RTS)
{
// when the RTS bit is set, the _RTS output goes low
@ -1616,7 +1616,7 @@ uint8_t z80scc_channel::scc_register_read( uint8_t reg)
case REG_RR14_WR7_OR_R10: data = do_sccreg_rr14(); break;
case REG_RR15_WR15_EXT_STAT: data = do_sccreg_rr15(); break;
default:
logerror(" \"%s\" %s: %c : Unsupported RRx register:%02x\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg);
logerror(" \"%s\" %s: %c : Unsupported RRx register:%02x\n", owner()->tag(), FUNCNAME, 'A' + m_index, reg);
}
return data;
}
@ -1642,7 +1642,7 @@ uint8_t z80scc_channel::control_read()
data = scc_register_read(reg);
//LOG("%s \"%s\": %c : Register R%d read '%02x'\n", FUNCNAME, m_owner->tag(), 'A' + m_index, reg, data);
//LOG("%s \"%s\": %c : Register R%d read '%02x'\n", FUNCNAME, owner()->tag(), 'A' + m_index, reg, data);
return data;
}
@ -1665,11 +1665,11 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
addressing*/
if (m_uart->m_variant & z80scc_device::SET_Z85X3X)
{
LOG("%s %s: %c : - Point High command\n", FUNCNAME, m_owner->tag(), 'A' + m_index);
LOG("%s %s: %c : - Point High command\n", FUNCNAME, owner()->tag(), 'A' + m_index);
m_uart->m_wr0_ptrbits |= 8;
}
else
LOG("%s %s: %c : - NULL command 2\n", FUNCNAME, m_owner->tag(), 'A' + m_index);
LOG("%s %s: %c : - NULL command 2\n", FUNCNAME, owner()->tag(), 'A' + m_index);
break;
case WR0_RESET_EXT_STATUS:
/*After an External/Status interrupt (a change on a modem line or a break condition,
@ -1684,7 +1684,7 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
(there are two transitions), another interrupt is not generated. Exceptions to this
rule are detailed in the RR0 description.*/
LOGCMD("%s %c - Reset External/Status Interrupt, latch %s\n", m_owner->tag(), 'A' + m_index,
LOGCMD("%s %c - Reset External/Status Interrupt, latch %s\n", owner()->tag(), 'A' + m_index,
m_extint_latch == 1? "is released" : "was already released");
// Release latch if no other external or status sources are active
if ((m_extint_latch = m_uart->update_extint(m_index)) == 0)
@ -1698,11 +1698,11 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
if (m_uart->m_variant & z80scc_device::SET_NMOS)
{
logerror("WR0 SWI ack command not supported on NMOS\n");
LOGCMD("%s: %c : WR0_RESET_HIGHEST_IUS command not available on NMOS!\n", m_owner->tag(), 'A' + m_index);
LOGCMD("%s: %c : WR0_RESET_HIGHEST_IUS command not available on NMOS!\n", owner()->tag(), 'A' + m_index);
}
else
{
LOGCMD("%s: %c : Reset Highest IUS\n", m_owner->tag(), 'A' + m_index);
LOGCMD("%s: %c : Reset Highest IUS\n", owner()->tag(), 'A' + m_index);
// loop over all interrupt sources
for (auto & elem : m_uart->m_int_state)
{
@ -1723,17 +1723,17 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
data with the special condition is held in the Receive FIFO until this command is issued. If either
of these modes is selected and this command is issued before the data has been read from the
Receive FIFO, the data is lost */
LOGCMD("%s: %c : WR0_ERROR_RESET - not implemented\n", m_owner->tag(), 'A' + m_index);
LOGCMD("%s: %c : WR0_ERROR_RESET - not implemented\n", owner()->tag(), 'A' + m_index);
m_rx_fifo_rp_step(); // Reset error state in fifo and unlock it. unlock == step to next slot in fifo.
break;
case WR0_SEND_ABORT: // Flush transmitter and Send 8-13 bits of '1's, used with SDLC
LOGCMD("%s: %c : WR0_SEND_ABORT - not implemented\n", m_owner->tag(), 'A' + m_index);
LOGCMD("%s: %c : WR0_SEND_ABORT - not implemented\n", owner()->tag(), 'A' + m_index);
break;
case WR0_NULL: // Do nothing
LOGCMD("%s: %c : WR0_NULL\n", m_owner->tag(), 'A' + m_index);
LOGCMD("%s: %c : WR0_NULL\n", owner()->tag(), 'A' + m_index);
break;
case WR0_ENABLE_INT_NEXT_RX: // enable interrupt on next receive character
LOGCMD("%s: %c : WR0_ENABLE_INT_NEXT\n", m_owner->tag(), 'A' + m_index);
LOGCMD("%s: %c : WR0_ENABLE_INT_NEXT\n", owner()->tag(), 'A' + m_index);
m_rx_first = 1;
break;
case WR0_RESET_TX_INT: // reset transmitter interrupt pending
@ -1743,7 +1743,7 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
been completely sent. This command is necessary to prevent the transmitter from requesting an
interrupt when the transmit buffer becomes empty (with Transmit Interrupt Enabled).*/
m_tx_int_disarm = 1;
LOGCMD("%s: %c : WR0_RESET_TX_INT\n", m_owner->tag(), 'A' + m_index);
LOGCMD("%s: %c : WR0_RESET_TX_INT\n", owner()->tag(), 'A' + m_index);
m_uart->m_int_state[INT_TRANSMIT_PRIO + (m_index == z80scc_device::CHANNEL_A ? 0 : 3 )] = 0;
// Based on the fact that prio levels are aligned with the bitorder of rr3 we can do this...
m_uart->m_chanA->m_rr3 &= ~((1 << INT_TRANSMIT_PRIO) + (m_index == z80scc_device::CHANNEL_A ? 3 : 0 ));
@ -1783,7 +1783,7 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
/* Write Register 1 is the control register for the various SCC interrupt and Wait/Request modes.*/
void z80scc_channel::do_sccreg_wr1(uint8_t data)
{
LOG("%s(%02x) \"%s\": %c : %s - %02x\n", FUNCNAME, data, m_owner->tag(), 'A' + m_index, FUNCNAME, data);
LOG("%s(%02x) \"%s\": %c : %s - %02x\n", FUNCNAME, data, owner()->tag(), 'A' + m_index, FUNCNAME, data);
/* TODO: Sort out SCC specific behaviours from legacy SIO behaviours:
- Channel B only bits vs
- Parity Is Special Condition, bit2 */
@ -1918,7 +1918,7 @@ void z80scc_channel::do_sccreg_wr7(uint8_t data)
/* WR8 is the transmit buffer register */
void z80scc_channel::do_sccreg_wr8(uint8_t data)
{
LOG("%s(%02x) \"%s\": %c : Transmit Buffer write %02x\n", FUNCNAME, data, m_owner->tag(), 'A' + m_index, data);
LOG("%s(%02x) \"%s\": %c : Transmit Buffer write %02x\n", FUNCNAME, data, owner()->tag(), 'A' + m_index, data);
data_write(data);
}
@ -1933,18 +1933,18 @@ void z80scc_channel::do_sccreg_wr9(uint8_t data)
switch (data & WR9_CMD_MASK)
{
case WR9_CMD_NORESET:
LOG("\"%s\": %c : Master Interrupt Control - No reset %02x\n", m_owner->tag(), 'A' + m_index, data);
LOG("\"%s\": %c : Master Interrupt Control - No reset %02x\n", owner()->tag(), 'A' + m_index, data);
break;
case WR9_CMD_CHNB_RESET:
LOGINT("\"%s\": %c : Master Interrupt Control - Channel B reset %02x\n", m_owner->tag(), 'A' + m_index, data);
LOGINT("\"%s\": %c : Master Interrupt Control - Channel B reset %02x\n", owner()->tag(), 'A' + m_index, data);
m_uart->m_chanB->reset();
break;
case WR9_CMD_CHNA_RESET:
LOGINT("\"%s\": %c : Master Interrupt Control - Channel A reset %02x\n", m_owner->tag(), 'A' + m_index, data);
LOGINT("\"%s\": %c : Master Interrupt Control - Channel A reset %02x\n", owner()->tag(), 'A' + m_index, data);
m_uart->m_chanA->reset();
break;
case WR9_CMD_HW_RESET:
LOGINT("\"%s\": %c : Master Interrupt Control - Device reset %02x\n", m_owner->tag(), 'A' + m_index, data);
LOGINT("\"%s\": %c : Master Interrupt Control - Device reset %02x\n", owner()->tag(), 'A' + m_index, data);
/*"The effects of this command are identical to those of a hardware reset, except that the Shift Right/Shift Left bit is
not changed and the MIE, Status High/Status Low and DLC bits take the programmed values that accompany this command."
*/
@ -1974,7 +1974,7 @@ void z80scc_channel::do_sccreg_wr9(uint8_t data)
void z80scc_channel::do_sccreg_wr10(uint8_t data)
{
m_wr10 = data;
LOG("\"%s\": %c : %s Misc Tx/Rx Control %02x - not implemented \n", m_owner->tag(), 'A' + m_index, FUNCNAME, data);
LOG("\"%s\": %c : %s Misc Tx/Rx Control %02x - not implemented \n", owner()->tag(), 'A' + m_index, FUNCNAME, data);
LOG("- 6/8 bit sync %d\n", data & WR10_8_6_BIT_SYNC ? 1 : 0);
LOG("- Loop Mode %d\n", data & WR10_LOOP_MODE ? 1 : 0);
LOG("- Abort/Flag on underrun %d\n", data & WR10_ABORT_FLAG_UNDERRUN ? 1 : 0);
@ -1991,7 +1991,7 @@ receive and transmit clocks, the type of signal on the /SYNC and /RTxC pins, and
the /TRxC pin.*/
void z80scc_channel::do_sccreg_wr11(uint8_t data)
{
LOG("\"%s\": %c : %s Clock Mode Control %02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data);
LOG("\"%s\": %c : %s Clock Mode Control %02x\n", owner()->tag(), 'A' + m_index, FUNCNAME, data);
m_wr11 = data;
/*Bit 7: This bit controls the type of input signal the SCC expects to see on the /RTxC pin. If this bit is set
to 0, the SCC expects a TTL-compatible signal as an input to this pin. If this bit is set to 1, the SCC
@ -2079,7 +2079,7 @@ void z80scc_channel::do_sccreg_wr12(uint8_t data)
{
m_wr12 = data;
update_serial();
LOG("\"%s\": %c : %s %02x Low byte of Time Constant for Baudrate generator\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data);
LOG("\"%s\": %c : %s %02x Low byte of Time Constant for Baudrate generator\n", owner()->tag(), 'A' + m_index, FUNCNAME, data);
}
/* WR13 contains the upper byte of the time constant for the baud rate generator. */
@ -2087,7 +2087,7 @@ void z80scc_channel::do_sccreg_wr13(uint8_t data)
{
m_wr13 = data;
update_serial();
LOG("\"%s\": %c : %s %02x High byte of Time Constant for Baudrate generator\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data);
LOG("\"%s\": %c : %s %02x High byte of Time Constant for Baudrate generator\n", owner()->tag(), 'A' + m_index, FUNCNAME, data);
}
/*
@ -2097,7 +2097,7 @@ void z80scc_channel::do_sccreg_wr14(uint8_t data)
switch (data & WR14_DPLL_CMD_MASK)
{
case WR14_CMD_NULL:
LOG("\"%s\": %c : %s Misc Control Bits Null Command %02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data);
LOG("\"%s\": %c : %s Misc Control Bits Null Command %02x\n", owner()->tag(), 'A' + m_index, FUNCNAME, data);
break;
case WR14_CMD_ESM:
/* Issuing this command causes the DPLL to enter the Search mode, where the DPLL searches for a locking edge in the
@ -2119,41 +2119,41 @@ void z80scc_channel::do_sccreg_wr14(uint8_t data)
see an edge during the expected window, the one clock missing bit in RR10 is set. If the DPLL does not see an edge
after two successive attempts, the two clocks missing bits in RR10 are set and the DPLL automatically enters the
Search mode. This command resets both clocks missing latches.*/
LOG("\"%s\": %c : %s Misc Control Bits Enter Search Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME);
LOG("\"%s\": %c : %s Misc Control Bits Enter Search Mode Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME);
break;
case WR14_CMD_RMC:
/* Issuing this command disables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state */
LOG("\"%s\": %c : %s Misc Control Bits Reset Missing Clocks Command - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME);
LOG("\"%s\": %c : %s Misc Control Bits Reset Missing Clocks Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME);
break;
case WR14_CMD_DISABLE_DPLL:
/* Issuing this command disables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state.*/
LOG("\"%s\": %c : %s Misc Control Bits Disable DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME);
LOG("\"%s\": %c : %s Misc Control Bits Disable DPLL Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME);
break;
case WR14_CMD_SS_BRG:
/* Issuing this command forces the clock for the DPLL to come from the output of the BRG. */
LOG("\"%s\": %c : %s Misc Control Bits Baudrate Generator Input DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME);
LOG("\"%s\": %c : %s Misc Control Bits Baudrate Generator Input DPLL Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME);
break;
case WR14_CMD_SS_RTXC:
/* Issuing the command forces the clock for the DPLL to come from the /RTxC pin or the crystal oscillator, depending on
the state of the XTAL/no XTAL bit in WR11. This mode is selected by a channel or hardware reset*/
LOG("\"%s\": %c : %s Misc Control Bits RTxC Input DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME);
LOG("\"%s\": %c : %s Misc Control Bits RTxC Input DPLL Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME);
break;
case WR14_CMD_SET_FM:
/* This command forces the DPLL to operate in the FM mode and is used to recover the clock from FM or Manchester-Encoded
data. (Manchester is decoded by placing the receiver in NRZ mode while the DPLL is in FM mode.)*/
LOG("\"%s\": %c : %s Misc Control Bits Set FM Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME);
LOG("\"%s\": %c : %s Misc Control Bits Set FM Mode Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME);
break;
case WR14_CMD_SET_NRZI:
/* Issuing this command forces the DPLL to operate in the NRZI mode. This mode is also selected by a hardware or channel reset.*/
LOG("\"%s\": %c : %s Mics Control Bits Set NRZI Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, FUNCNAME);
LOG("\"%s\": %c : %s Mics Control Bits Set NRZI Mode Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME);
break;
default:
logerror("\"%s\": %c : %s Mics Control Bits command %02x - not implemented \n", m_owner->tag(), 'A' + m_index, FUNCNAME, data);
logerror("\"%s\": %c : %s Mics Control Bits command %02x - not implemented \n", owner()->tag(), 'A' + m_index, FUNCNAME, data);
}
/* Based on baudrate code from 8530scc.cpp */
if ( !(m_wr14 & WR14_BRG_ENABLE) && (data & WR14_BRG_ENABLE) ) // baud rate generator being enabled?
{
LOG("\"%s\": %c : %s Mics Control Bits Baudrate generator enabled with ", m_owner->tag(), 'A' + m_index, FUNCNAME);
LOG("\"%s\": %c : %s Mics Control Bits Baudrate generator enabled with ", owner()->tag(), 'A' + m_index, FUNCNAME);
if (data & WR14_BRG_SOURCE) // Do we use the PCLK as baudrate source
{
LOG(" - PCLK as source\n");
@ -2191,7 +2191,7 @@ void z80scc_channel::do_sccreg_wr14(uint8_t data)
void z80scc_channel::do_sccreg_wr15(uint8_t data)
{
LOG("%s(%02x) \"%s\": %c : External/Status Control Bits\n",
FUNCNAME, data, m_owner->tag(), 'A' + m_index);
FUNCNAME, data, owner()->tag(), 'A' + m_index);
LOG("WR7 prime ints : %s\n", data & WR15_WR7PRIME ? WR15NO : "disabled");
LOG("Zero count ints : %s\n", data & WR15_ZEROCOUNT ? WR15NO : "disabled");
LOG("14 bit Status FIFO : %s\n", data & WR15_STATUS_FIFO ? WR15NO : "disabled");
@ -2224,7 +2224,7 @@ void z80scc_channel::scc_register_write(uint8_t reg, uint8_t data)
case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break;
case REG_WR15_EXT_ST_INT_CTRL: do_sccreg_wr15(data); break;
default:
logerror("\"%s\": %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
logerror("\"%s\": %c : Unsupported WRx register:%02x\n", owner()->tag(), 'A' + m_index, reg);
}
}
@ -2264,7 +2264,7 @@ void z80scc_channel::control_write(uint8_t data)
m_wr0 &= ~regmask;
}
LOGSETUP(" * %s %c Reg %02x <- %02x - %s\n", m_owner->tag(), 'A' + m_index, reg, data, std::array<char const *, 16>
LOGSETUP(" * %s %c Reg %02x <- %02x - %s\n", owner()->tag(), 'A' + m_index, reg, data, std::array<char const *, 16>
{{ "Command register", "Tx/Rx Interrupt and Data Transfer Modes", "Interrupt Vector", "Rx Parameters and Control",
"Tx/Rx Misc Parameters and Modes", "Tx Parameters and Controls", "Sync Characters or SDLC Address Field","Sync Character or SDLC Flag/Prime",
"Tx Buffer", "Master Interrupt Control", "Miscellaneous Tx/Rx Control Bits", "Clock Mode Control",
@ -2282,7 +2282,7 @@ uint8_t z80scc_channel::data_read()
{
uint8_t data = 0;
LOG("%s \"%s\": %c : Data Register Read: ", FUNCNAME, m_owner->tag(), 'A' + m_index);
LOG("%s \"%s\": %c : Data Register Read: ", FUNCNAME, owner()->tag(), 'A' + m_index);
if (m_rx_fifo_wp != m_rx_fifo_rp)
{
@ -2366,7 +2366,7 @@ WRITE8_MEMBER (z80scc_device::db_w) { m_chanB->data_write(data); }
void z80scc_channel::data_write(uint8_t data)
{
/* Tx FIFO is full or...? */
LOGTX("%s \"%s\": %c : Data Register Write: %02d '%c'\n", FUNCNAME, m_owner->tag(), 'A' + m_index, data, isprint(data) ? data : ' ');
LOGTX("%s \"%s\": %c : Data Register Write: %02d '%c'\n", FUNCNAME, owner()->tag(), 'A' + m_index, data, isprint(data) ? data : ' ');
if ( !(m_rr0 & RR0_TX_BUFFER_EMPTY) && // NMOS/CMOS 1 slot "FIFO" is controlled by the TBE bit instead of fifo logic
( (m_tx_fifo_wp + 1 == m_tx_fifo_rp) || ( (m_tx_fifo_wp + 1 == m_tx_fifo_sz) && (m_tx_fifo_rp == 0) )))
@ -2456,7 +2456,7 @@ void z80scc_channel::data_write(uint8_t data)
void z80scc_channel::receive_data(uint8_t data)
{
LOG("\"%s\": %c : Received Data Byte '%c'/%02x put into FIFO\n", m_owner->tag(), 'A' + m_index, isprint(data) ? data : ' ', data);
LOG("\"%s\": %c : Received Data Byte '%c'/%02x put into FIFO\n", owner()->tag(), 'A' + m_index, isprint(data) ? data : ' ', data);
if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) ))
{
@ -2509,7 +2509,7 @@ void z80scc_channel::receive_data(uint8_t data)
WRITE_LINE_MEMBER( z80scc_channel::cts_w )
{
LOG("\"%s\" %s: %c : CTS %u\n", m_owner->tag(), FUNCNAME, 'A' + m_index, state);
LOG("\"%s\" %s: %c : CTS %u\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
if ((m_rr0 & RR0_CTS) != (state ? RR0_CTS : 0)) // SCC change detection logic
{
@ -2546,7 +2546,7 @@ WRITE_LINE_MEMBER( z80scc_channel::cts_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( z80scc_channel::dcd_w )
{
LOGDCD("\"%s\": %c : DCD %u\n", m_owner->tag(), 'A' + m_index, state);
LOGDCD("\"%s\": %c : DCD %u\n", owner()->tag(), 'A' + m_index, state);
if ((m_rr0 & RR0_DCD) != (state ? RR0_DCD : 0)) // SCC change detection logic
{
@ -2586,7 +2586,7 @@ WRITE_LINE_MEMBER( z80scc_channel::dcd_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( z80scc_channel::ri_w )
{
LOGINT("\"%s\": %c : RI %u - not implemented\n", m_owner->tag(), 'A' + m_index, state);
LOGINT("\"%s\": %c : RI %u - not implemented\n", owner()->tag(), 'A' + m_index, state);
#if 0 // TODO: This code is inherited from another device driver and not correct for SCC
if (m_ri != state)
@ -2619,7 +2619,7 @@ WRITE_LINE_MEMBER( z80scc_channel::ri_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( z80scc_channel::sync_w )
{
LOGSYNC("\"%s\": %c : SYNC %u\n", m_owner->tag(), 'A' + m_index, state);
LOGSYNC("\"%s\": %c : SYNC %u\n", owner()->tag(), 'A' + m_index, state);
if ((m_rr0 & RR0_SYNC_HUNT) != (state ? RR0_SYNC_HUNT : 0)) // SCC change detection logic
{
if (state) m_rr0 |= RR0_SYNC_HUNT; else m_rr0 &= ~RR0_SYNC_HUNT; // Raw pin/status value
@ -2633,7 +2633,7 @@ WRITE_LINE_MEMBER( z80scc_channel::rxc_w )
{
/* Support for external clock as source for BRG yet to be finished */
#if 0
//LOG("\"%s\": %c : Receiver Clock Pulse\n", m_owner->tag(), m_index + 'A');
//LOG("\"%s\": %c : Receiver Clock Pulse\n", owner()->tag(), m_index + 'A');
if ( ((m_wr3 & WR3_RX_ENABLE) | (m_wr5 & WR5_TX_ENABLE)) && m_wr14 & WR14_BRG_ENABLE)
{
if (!(m_wr14 & WR14_BRG_SOURCE)) // Is the Baud rate Generator driven by RTxC?
@ -2683,7 +2683,7 @@ WRITE_LINE_MEMBER( z80scc_channel::rxc_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( z80scc_channel::txc_w )
{
//LOG("\"%s\": %c : Transmitter Clock Pulse\n", m_owner->tag(), m_index + 'A');
//LOG("\"%s\": %c : Transmitter Clock Pulse\n", owner()->tag(), m_index + 'A');
if (m_wr5 & WR5_TX_ENABLE)
{
int clocks = get_clock_mode();
@ -2732,8 +2732,8 @@ unsigned int z80scc_channel::get_brg_rate()
brg_const = 2 + (m_wr13 << 8 | m_wr12);
if (m_wr14 & WR14_BRG_SOURCE) // Do we use the PCLK as baudrate source
{
rate = m_owner->clock() / (brg_const == 0 ? 1 : brg_const);
LOG(" - Source bit rate (%d) = PCLK (%d) / (%d)\n", rate, m_owner->clock(), brg_const);
rate = owner()->clock() / (brg_const == 0 ? 1 : brg_const);
LOG(" - Source bit rate (%d) = PCLK (%d) / (%d)\n", rate, owner()->clock(), brg_const);
}
else // Else we use the RTxC as BRG source
{
@ -2766,7 +2766,7 @@ void z80scc_channel::update_serial()
parity = PARITY_NONE;
}
LOG(" %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", FUNCNAME, m_owner->tag(), 'A' + m_index, 1,
LOG(" %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", FUNCNAME, owner()->tag(), 'A' + m_index, 1,
data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2);
set_data_frame(1, data_bit_count, parity, stop_bits);

110
src/devices/machine/z80sio.cpp
View File

@ -545,7 +545,7 @@ void z80sio_channel::device_start()
LOG("%s\n",FUNCNAME);
m_uart = downcast<z80sio_device *>(owner());
m_index = m_uart->get_channel_index(this);
m_variant = ((z80sio_device *)m_owner)->m_variant;
m_variant = ((z80sio_device *)owner())->m_variant;
// state saving
save_item(NAME(m_rr0));
@ -619,7 +619,7 @@ void z80sio_channel::tra_callback()
{
if (!(m_wr5 & WR5_TX_ENABLE))
{
LOGBIT("%s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOGBIT("%s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// transmit mark
if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(1);
@ -628,7 +628,7 @@ void z80sio_channel::tra_callback()
}
else if (m_wr5 & WR5_SEND_BREAK)
{
LOGBIT("%s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOGBIT("%s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// transmit break
if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(0);
@ -639,7 +639,7 @@ void z80sio_channel::tra_callback()
{
int db = transmit_register_get_data_bit();
LOGBIT("%s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5);
LOGBIT("%s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, db, m_wr5);
// transmit data
if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(db);
@ -648,8 +648,8 @@ void z80sio_channel::tra_callback()
}
else
{
LOGBIT("%s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, m_owner->tag(), 'A' + m_index);
LOGBIT("%s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, owner()->tag(), 'A' + m_index);
}
}
@ -662,7 +662,7 @@ void z80sio_channel::tra_complete()
LOG("%s %s\n",FUNCNAME, tag());
if ((m_wr5 & WR5_TX_ENABLE) && !(m_wr5 & WR5_SEND_BREAK) && !(m_rr0 & RR0_TX_BUFFER_EMPTY))
{
LOGTX("%s() \"%s \"Channel %c Transmit Data Byte '%02x' m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_tx_data, m_wr5);
LOGTX("%s() \"%s \"Channel %c Transmit Data Byte '%02x' m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_tx_data, m_wr5);
transmit_register_setup(m_tx_data);
@ -674,7 +674,7 @@ void z80sio_channel::tra_complete()
}
else if (m_wr5 & WR5_SEND_BREAK)
{
LOGTX("%s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOGTX("%s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// transmit break
if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(0);
@ -683,7 +683,7 @@ void z80sio_channel::tra_complete()
}
else
{
LOGTX("%s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOGTX("%s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// transmit mark
if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(1);
@ -694,7 +694,7 @@ void z80sio_channel::tra_complete()
// if transmit buffer is empty
if (m_rr0 & RR0_TX_BUFFER_EMPTY)
{
LOGTX("%s() \"%s \"Channel %c Transmit buffer empty m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
LOGTX("%s() \"%s \"Channel %c Transmit buffer empty m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
// then all characters have been sent
m_rr1 |= RR1_ALL_SENT;
@ -712,7 +712,7 @@ void z80sio_channel::rcv_callback()
{
if (m_wr3 & WR3_RX_ENABLE)
{
LOGBIT("%s() \"%s \"Channel %c Received Data Bit %d\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_rxd);
LOGBIT("%s() \"%s \"Channel %c Received Data Bit %d\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_rxd);
receive_register_update_bit(m_rxd);
}
}
@ -727,7 +727,7 @@ void z80sio_channel::rcv_complete()
receive_register_extract();
data = get_received_char();
LOGRCV("%s() \"%s \"Channel %c Received Data %02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, data);
LOGRCV("%s() \"%s \"Channel %c Received Data %02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, data);
receive_data(data);
}
@ -763,7 +763,7 @@ int z80sio_channel::get_clock_mode()
*/
void z80sio_channel::set_rts(int state)
{
LOG("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index);
LOG("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, owner()->tag(), 'A' + m_index);
if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_rtsa_cb(state);
else
@ -772,8 +772,8 @@ void z80sio_channel::set_rts(int state)
void z80sio_channel::update_rts()
{
// LOG("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index);
LOG("%s() \"%s\" Channel %c \n", FUNCNAME, m_owner->tag(), 'A' + m_index);
// LOG("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, owner()->tag(), 'A' + m_index);
LOG("%s() \"%s\" Channel %c \n", FUNCNAME, owner()->tag(), 'A' + m_index);
if (m_wr5 & WR5_RTS)
{
// when the RTS bit is set, the _RTS output goes low
@ -950,7 +950,7 @@ uint8_t z80sio_channel::control_read()
case REG_RR1_SPEC_RCV_COND: data = do_sioreg_rr1(); break;
case REG_RR2_INTERRUPT_VECT: data = do_sioreg_rr2(); break;
default:
logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", owner()->tag(), 'A' + m_index, reg);
LOG("%s %s unsupported register:%02x\n",FUNCNAME, tag(), reg);
}
@ -967,19 +967,19 @@ void z80sio_channel::do_sioreg_wr0_resets(uint8_t data)
switch (data & WR0_CRC_RESET_CODE_MASK)
{
case WR0_CRC_RESET_NULL:
LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_NULL\n", m_owner->tag(), 'A' + m_index);
LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_NULL\n", owner()->tag(), 'A' + m_index);
break;
case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */
LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_RX - not implemented\n", m_owner->tag(), 'A' + m_index);
LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_RX - not implemented\n", owner()->tag(), 'A' + m_index);
break;
case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */
LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_TX - not implemented\n", m_owner->tag(), 'A' + m_index);
LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_TX - not implemented\n", owner()->tag(), 'A' + m_index);
break;
case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the SRO register) */
LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_TX_UNDERRUN - not implemented\n", m_owner->tag(), 'A' + m_index);
LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_TX_UNDERRUN - not implemented\n", owner()->tag(), 'A' + m_index);
break;
default: /* Will not happen unless someone messes with the mask */
logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK);
logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", owner()->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK);
}
}
@ -988,7 +988,7 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data)
m_wr0 = data;
if ((data & WR0_COMMAND_MASK) != WR0_NULL)
LOGSETUP(" * %s %c Reg %02x <- %02x \n", m_owner->tag(), 'A' + m_index, 0, data);
LOGSETUP(" * %s %c Reg %02x <- %02x \n", owner()->tag(), 'A' + m_index, 0, data);
switch (data & WR0_COMMAND_MASK)
{
case WR0_NULL:
@ -1066,7 +1066,7 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data)
}
break;
default:
LOG("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK);
LOG("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", owner()->tag(), 'A' + m_index, data, WR0_REGISTER_MASK);
}
do_sioreg_wr0_resets(data);
@ -1076,29 +1076,29 @@ void z80sio_channel::do_sioreg_wr1(uint8_t data)
{
/* TODO: implement vector modifications when WR1 bit D2 is changed */
m_wr1 = data;
LOG("Z80SIO \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait");
LOG("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit");
LOG("Z80SIO \"%s\" Channel %c : External Interrupt Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Transmit Interrupt Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Status Affects Vector %u\n", owner()->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", owner()->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait");
LOG("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", owner()->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit");
switch (data & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_DISABLE:
LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index);
LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", owner()->tag(), 'A' + m_index);
break;
case WR1_RX_INT_FIRST:
LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index);
LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", owner()->tag(), 'A' + m_index);
break;
case WR1_RX_INT_ALL_PARITY:
LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index);
LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", owner()->tag(), 'A' + m_index);
break;
case WR1_RX_INT_ALL:
LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index);
LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", owner()->tag(), 'A' + m_index);
break;
}
}
@ -1106,45 +1106,45 @@ void z80sio_channel::do_sioreg_wr1(uint8_t data)
void z80sio_channel::do_sioreg_wr2(uint8_t data)
{
m_wr2 = data;
LOG("Z80SIO \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80SIO \"%s\" Channel %c : Interrupt Vector %02x\n", owner()->tag(), 'A' + m_index, data);
}
void z80sio_channel::do_sioreg_wr3(uint8_t data)
{
m_wr3 = data;
LOG("Z80SIO \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length());
LOG("Z80SIO \"%s\" Channel %c : Receiver Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Auto Enables %u\n", owner()->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Receiver Bits/Character %u\n", owner()->tag(), 'A' + m_index, get_rx_word_length());
}
void z80sio_channel::do_sioreg_wr4(uint8_t data)
{
m_wr4 = data;
LOG("Z80SIO \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd");
LOG("Z80SIO \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits()));
LOG("Z80SIO \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode());
LOG("Z80SIO \"%s\" Channel %c : Parity Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Parity %s\n", owner()->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd");
LOG("Z80SIO \"%s\" Channel %c : Stop Bits %s\n", owner()->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits()));
LOG("Z80SIO \"%s\" Channel %c : Clock Mode %uX\n", owner()->tag(), 'A' + m_index, get_clock_mode());
}
void z80sio_channel::do_sioreg_wr5(uint8_t data)
{
m_wr5 = data;
LOG("Z80SIO \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length());
LOG("Z80SIO \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Transmitter Enable %u\n", owner()->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Transmitter Bits/Character %u\n", owner()->tag(), 'A' + m_index, get_tx_word_length());
LOG("Z80SIO \"%s\" Channel %c : Send Break %u\n", owner()->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Request to Send %u\n", owner()->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0);
LOG("Z80SIO \"%s\" Channel %c : Data Terminal Ready %u\n", owner()->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0);
}
void z80sio_channel::do_sioreg_wr6(uint8_t data)
{
LOG("Z80SIO \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80SIO \"%s\" Channel %c : Transmit Sync %02x\n", owner()->tag(), 'A' + m_index, data);
m_sync = (m_sync & 0xff00) | data;
}
void z80sio_channel::do_sioreg_wr7(uint8_t data)
{
LOG("Z80SIO \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80SIO \"%s\" Channel %c : Receive Sync %02x\n", owner()->tag(), 'A' + m_index, data);
m_sync = (data << 8) | (m_sync & 0xff);
}
@ -1176,7 +1176,7 @@ void z80sio_channel::control_write(uint8_t data)
case REG_WR6_SYNC_OR_SDLC_A: do_sioreg_wr6(data); break;
case REG_WR7_SYNC_OR_SDLC_F: do_sioreg_wr7(data); break;
default:
logerror("Z80SIO \"%s\" Channel %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
logerror("Z80SIO \"%s\" Channel %c : Unsupported WRx register:%02x\n", owner()->tag(), 'A' + m_index, reg);
}
}
@ -1203,7 +1203,7 @@ uint8_t z80sio_channel::data_read()
}
}
LOG("Z80SIO \"%s\" Channel %c : Data Register Read '%02x'\n", m_owner->tag(), 'A' + m_index, data);
LOG("Z80SIO \"%s\" Channel %c : Data Register Read '%02x'\n", owner()->tag(), 'A' + m_index, data);
return data;
}
@ -1218,7 +1218,7 @@ void z80sio_channel::data_write(uint8_t data)
if ((m_wr5 & WR5_TX_ENABLE) && is_transmit_register_empty())
{
LOGTX("Z80SIO \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data);
LOGTX("Z80SIO \"%s\" Channel %c : Transmit Data Byte '%02x'\n", owner()->tag(), 'A' + m_index, m_tx_data);
transmit_register_setup(m_tx_data);
@ -1340,7 +1340,7 @@ WRITE_LINE_MEMBER( z80sio_channel::cts_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( z80sio_channel::dcd_w )
{
LOG("Z80SIO \"%s\" Channel %c : DCD %u\n", m_owner->tag(), 'A' + m_index, state);
LOG("Z80SIO \"%s\" Channel %c : DCD %u\n", owner()->tag(), 'A' + m_index, state);
if (m_dcd != state)
{
@ -1377,7 +1377,7 @@ WRITE_LINE_MEMBER( z80sio_channel::dcd_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( z80sio_channel::sync_w )
{
LOG("Z80SIO \"%s\" Channel %c : Sync %u\n", m_owner->tag(), 'A' + m_index, state);
LOG("Z80SIO \"%s\" Channel %c : Sync %u\n", owner()->tag(), 'A' + m_index, state);
if (m_sh != state)
{
@ -1409,7 +1409,7 @@ WRITE_LINE_MEMBER( z80sio_channel::sync_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( z80sio_channel::rxc_w )
{
//LOG("Z80SIO \"%s\" Channel %c : Receiver Clock Pulse\n", m_owner->tag(), m_index + 'A');
//LOG("Z80SIO \"%s\" Channel %c : Receiver Clock Pulse\n", owner()->tag(), m_index + 'A');
int clocks = get_clock_mode();
if (clocks == 1)
rx_clock_w(state);
@ -1430,7 +1430,7 @@ WRITE_LINE_MEMBER( z80sio_channel::rxc_w )
//-------------------------------------------------
WRITE_LINE_MEMBER( z80sio_channel::txc_w )
{
//LOG("Z80SIO \"%s\" Channel %c : Transmitter Clock Pulse\n", m_owner->tag(), m_index + 'A');
//LOG("Z80SIO \"%s\" Channel %c : Transmitter Clock Pulse\n", owner()->tag(), m_index + 'A');
int clocks = get_clock_mode();
if (clocks == 1)
tx_clock_w(state);

2
src/devices/video/i82730.cpp
View File

@ -107,7 +107,7 @@ void i82730_device::device_start()
void i82730_device::device_reset()
{
cpu_device *cpu = m_owner->subdevice<cpu_device>(m_cpu_tag);
cpu_device *cpu = owner()->subdevice<cpu_device>(m_cpu_tag);
m_program = &cpu->space(AS_PROGRAM);
m_initialized = false;