diff --git a/src/emu/cpu/mcs51/mcs51.c b/src/emu/cpu/mcs51/mcs51.c index d0f1f0d5e58..f889cf7fc1b 100644 --- a/src/emu/cpu/mcs51/mcs51.c +++ b/src/emu/cpu/mcs51/mcs51.c @@ -246,8 +246,8 @@ struct _mcs51_uart UINT8 delay_cycles; //Gross Hack; }; -typedef struct _mcs51_regs mcs51_regs; -struct _mcs51_regs +typedef struct _mcs51_state_t mcs51_state_t; +struct _mcs51_state_t { //Internal stuff UINT16 ppc; //previous pc @@ -277,8 +277,8 @@ struct _mcs51_regs UINT8 *sfr_ram; /* 128 SFR - these are in 0x80 - 0xFF */ /* SFR Callbacks */ - void (*sfr_write)(mcs51_regs *mcs51, size_t offset, UINT8 data); - UINT8 (*sfr_read)(mcs51_regs *mcs51, size_t offset); + void (*sfr_write)(mcs51_state_t *mcs51_state, size_t offset, UINT8 data); + UINT8 (*sfr_read)(mcs51_state_t *mcs51_state, size_t offset); /* Interrupt Callback */ cpu_irq_callback irq_callback; @@ -322,21 +322,21 @@ struct _mcs51_regs /* Read/Write a byte from/to the Internal RAM */ -#define IRAM_R(a) iram_read(mcs51, a) -#define IRAM_W(a, d) iram_write(mcs51, a, d) +#define IRAM_R(a) iram_read(mcs51_state, a) +#define IRAM_W(a, d) iram_write(mcs51_state, a, d) /* Read/Write a byte from/to the Internal RAM indirectly */ /* (called from indirect addressing) */ -#define IRAM_IR(a) data_read_byte_8le((a) & mcs51->ram_mask) -#define IRAM_IW(a, d) data_write_byte_8le((a) & mcs51->ram_mask, d) +#define IRAM_IR(a) data_read_byte_8le((a) & mcs51_state->ram_mask) +#define IRAM_IW(a, d) data_write_byte_8le((a) & mcs51_state->ram_mask, d) /* Form an Address to Read/Write to External RAM indirectly */ /* (called from indirect addressing) */ -#define ERAM_ADDR(a,m) external_ram_iaddr(mcs51, a,m) +#define ERAM_ADDR(a,m) external_ram_iaddr(mcs51_state, a,m) /* Read/Write a bit from Bit Addressable Memory */ -#define BIT_R(a) bit_address_r(mcs51, a) -#define BIT_W(a,v) bit_address_w(mcs51, a, v) +#define BIT_R(a) bit_address_r(mcs51_state, a) +#define BIT_W(a,v) bit_address_w(mcs51_state, a, v) /* Input/Output a byte from given I/O port */ #define IN(port) ((UINT8)io_read_byte(port)) @@ -347,14 +347,14 @@ struct _mcs51_regs SHORTCUTS ***************************************************************************/ -#define PPC mcs51->ppc -#define PC mcs51->pc -#define RWM mcs51->rwm +#define PPC mcs51_state->ppc +#define PC mcs51_state->pc +#define RWM mcs51_state->rwm /* SFR Registers - These are accessed directly for speed on read */ /* Read accessors */ -#define SFR_A(a) mcs51->sfr_ram[(a)] +#define SFR_A(a) mcs51_state->sfr_ram[(a)] #define SET_SFR_A(a,v) do { SFR_A(a) = (v); } while (0) #define ACC ((const UINT8) SFR_A(ADDR_ACC)) @@ -381,7 +381,7 @@ struct _mcs51_regs #define B SFR_A(ADDR_B) #define SBUF SFR_A(ADDR_SBUF) -#define R_REG(r) mcs51->internal_ram[(r) | (PSW & 0x18)] +#define R_REG(r) mcs51_state->internal_ram[(r) | (PSW & 0x18)] #define DPTR ((DPH<<8) | DPL) /* 8052 Only registers */ @@ -440,7 +440,7 @@ struct _mcs51_regs #define SET_SBUF(v) SET_SFR_A(ADDR_SBUF, v) /* No actions triggered on write */ -#define SET_REG(r, v) do { mcs51->internal_ram[(r) | (PSW & 0x18)] = (v); } while (0) +#define SET_REG(r, v) do { mcs51_state->internal_ram[(r) | (PSW & 0x18)] = (v); } while (0) #define SET_DPTR(n) do { DPH = ((n) >> 8) & 0xff; DPL = (n) & 0xff; } while (0) @@ -622,15 +622,15 @@ struct _mcs51_regs /*Add and Subtract Flag settings*/ -#define DO_ADD_FLAGS(a,d,c) do_add_flags(mcs51, a, d, c) -#define DO_SUB_FLAGS(a,d,c) do_sub_flags(mcs51, a, d, c) +#define DO_ADD_FLAGS(a,d,c) do_add_flags(mcs51_state, a, d, c) +#define DO_SUB_FLAGS(a,d,c) do_sub_flags(mcs51_state, a, d, c) -#define SET_PARITY() do {mcs51->recalc_parity |= 1;} while (0) -#define PUSH_PC() push_pc(mcs51) -#define POP_PC() pop_pc(mcs51) +#define SET_PARITY() do {mcs51_state->recalc_parity |= 1;} while (0) +#define PUSH_PC() push_pc(mcs51_state) +#define POP_PC() pop_pc(mcs51_state) /* Clear Current IRQ */ -#define CLEAR_CURRENT_IRQ() clear_current_irq(mcs51) +#define CLEAR_CURRENT_IRQ() clear_current_irq(mcs51_state) /*************************************************************************** GLOBAL VARIABLES @@ -645,8 +645,8 @@ static int (*hold_serial_rx_callback)(void); FUNCTION PROTOTYPES ***************************************************************************/ -static void check_irqs(mcs51_regs *mcs51); -INLINE void serial_transmit(mcs51_regs *mcs51, UINT8 data); +static void check_irqs(mcs51_state_t *mcs51_state); +INLINE void serial_transmit(mcs51_state_t *mcs51_state, UINT8 data); /* Hold callback functions so they can be set by caller (before the cpu reset) */ @@ -654,29 +654,29 @@ INLINE void serial_transmit(mcs51_regs *mcs51, UINT8 data); INLINE FUNCTIONS ***************************************************************************/ -INLINE void clear_current_irq(mcs51_regs *mcs51) +INLINE void clear_current_irq(mcs51_state_t *mcs51_state) { - if (mcs51->cur_irq_prio >= 0) - mcs51->irq_active &= ~(1 << mcs51->cur_irq_prio); - if (mcs51->irq_active & 4) - mcs51->cur_irq_prio = 2; - else if (mcs51->irq_active & 2) - mcs51->cur_irq_prio = 1; - else if (mcs51->irq_active & 1) - mcs51->cur_irq_prio = 0; + if (mcs51_state->cur_irq_prio >= 0) + mcs51_state->irq_active &= ~(1 << mcs51_state->cur_irq_prio); + if (mcs51_state->irq_active & 4) + mcs51_state->cur_irq_prio = 2; + else if (mcs51_state->irq_active & 2) + mcs51_state->cur_irq_prio = 1; + else if (mcs51_state->irq_active & 1) + mcs51_state->cur_irq_prio = 0; else - mcs51->cur_irq_prio = -1; - LOG(("New: %d %02x\n", mcs51->cur_irq_prio, mcs51->irq_active)); + mcs51_state->cur_irq_prio = -1; + LOG(("New: %d %02x\n", mcs51_state->cur_irq_prio, mcs51_state->irq_active)); } -INLINE UINT8 r_acc(mcs51_regs *mcs51) { return SFR_A(ADDR_ACC); } +INLINE UINT8 r_acc(mcs51_state_t *mcs51_state) { return SFR_A(ADDR_ACC); } -INLINE UINT8 r_psw(mcs51_regs *mcs51) { return SFR_A(ADDR_PSW); } +INLINE UINT8 r_psw(mcs51_state_t *mcs51_state) { return SFR_A(ADDR_PSW); } -INLINE void update_ptrs(mcs51_regs *mcs51) +INLINE void update_ptrs(mcs51_state_t *mcs51_state) { - mcs51->internal_ram = memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_DATA, 0x00); - mcs51->sfr_ram = memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_DATA, 0x100); + mcs51_state->internal_ram = memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_DATA, 0x00); + mcs51_state->sfr_ram = memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_DATA, 0x100); } @@ -711,7 +711,7 @@ INLINE void update_ptrs(mcs51_regs *mcs51) 0x0000-0xffff -> data memory (the bus used to access it does not matter) */ -INLINE offs_t external_ram_iaddr(mcs51_regs *mcs51, offs_t offset, offs_t mem_mask) +INLINE offs_t external_ram_iaddr(mcs51_state_t *mcs51_state, offs_t offset, offs_t mem_mask) { /* Memory Range (RG1 and RG0 @ MCON and RPCTL registers) */ static const UINT16 ds5002fp_ranges[4] = { 0x1fff, 0x3fff, 0x7fff, 0xffff }; @@ -721,11 +721,11 @@ INLINE offs_t external_ram_iaddr(mcs51_regs *mcs51, offs_t offset, offs_t mem_ma 0x8000, 0x9000, 0xa000, 0xb000, 0xc000, 0xd000, 0xe000, 0x10000 }; /* if partition mode is set, adjust offset based on the bus */ - if (mcs51->features & FEATURE_DS5002FP) + if (mcs51_state->features & FEATURE_DS5002FP) { if (!GET_PM) { if (!GET_EXBS) { - if ((offset >= ds5002fp_partitions[GET_PA]) && (offset <= ds5002fp_ranges[mcs51->ds5002fp.range])) { + if ((offset >= ds5002fp_partitions[GET_PA]) && (offset <= ds5002fp_ranges[mcs51_state->ds5002fp.range])) { offset += 0x10000; } } @@ -741,21 +741,21 @@ INLINE offs_t external_ram_iaddr(mcs51_regs *mcs51, offs_t offset, offs_t mem_ma /* Internal ram read/write */ -INLINE UINT8 iram_read(mcs51_regs *mcs51, size_t offset) +INLINE UINT8 iram_read(mcs51_state_t *mcs51_state, size_t offset) { - return (((offset) < 0x80) ? data_read_byte_8le(offset) : mcs51->sfr_read(mcs51, offset)); + return (((offset) < 0x80) ? data_read_byte_8le(offset) : mcs51_state->sfr_read(mcs51_state, offset)); } -INLINE void iram_write(mcs51_regs *mcs51, size_t offset, UINT8 data) +INLINE void iram_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 data) { if ((offset) < 0x80) data_write_byte_8le(offset, data); else - mcs51->sfr_write(mcs51, offset, data); + mcs51_state->sfr_write(mcs51_state, offset, data); } /*Push the current PC to the stack*/ -INLINE void push_pc(mcs51_regs *mcs51) +INLINE void push_pc(mcs51_state_t *mcs51_state) { UINT8 tmpSP = SP+1; //Grab and Increment Stack Pointer IRAM_IW(tmpSP, (PC & 0xff)); //Store low byte of PC to Internal Ram (Use IRAM_IW to store stack above 128 bytes) @@ -765,7 +765,7 @@ INLINE void push_pc(mcs51_regs *mcs51) } /*Pop the current PC off the stack and into the pc*/ -INLINE void pop_pc(mcs51_regs *mcs51) +INLINE void pop_pc(mcs51_state_t *mcs51_state) { UINT8 tmpSP = SP; //Grab Stack Pointer PC = (IRAM_IR(tmpSP--) & 0xff) << 8; //Store hi byte to PC (must use IRAM_IR to access stack pointing above 128 bytes) @@ -775,7 +775,7 @@ INLINE void pop_pc(mcs51_regs *mcs51) } //Set the PSW Parity Flag -INLINE void set_parity(mcs51_regs *mcs51) +INLINE void set_parity(mcs51_state_t *mcs51_state) { //This flag will be set when the accumulator contains an odd # of bits set.. UINT8 p = 0; @@ -790,7 +790,7 @@ INLINE void set_parity(mcs51_regs *mcs51) SET_P(p & 1); } -INLINE UINT8 bit_address_r(mcs51_regs *mcs51, UINT8 offset) +INLINE UINT8 bit_address_r(mcs51_state_t *mcs51_state, UINT8 offset) { UINT8 word; UINT8 mask; @@ -817,7 +817,7 @@ INLINE UINT8 bit_address_r(mcs51_regs *mcs51, UINT8 offset) } -INLINE void bit_address_w(mcs51_regs *mcs51, UINT8 offset, UINT8 bit) +INLINE void bit_address_w(mcs51_state_t *mcs51_state, UINT8 offset, UINT8 bit) { int word; UINT8 mask; @@ -849,7 +849,7 @@ INLINE void bit_address_w(mcs51_regs *mcs51, UINT8 offset, UINT8 bit) } } -INLINE void do_add_flags(mcs51_regs *mcs51, UINT8 a, UINT8 data, UINT8 c) +INLINE void do_add_flags(mcs51_state_t *mcs51_state, UINT8 a, UINT8 data, UINT8 c) { UINT16 result = a+data+c; INT16 result1 = (INT8)a+(INT8)data+c; @@ -860,7 +860,7 @@ INLINE void do_add_flags(mcs51_regs *mcs51, UINT8 a, UINT8 data, UINT8 c) SET_OV(result1 < -128 || result1 > 127); } -INLINE void do_sub_flags(mcs51_regs *mcs51, UINT8 a, UINT8 data, UINT8 c) +INLINE void do_sub_flags(mcs51_state_t *mcs51_state, UINT8 a, UINT8 data, UINT8 c) { UINT16 result = a-(data+c); INT16 result1 = (INT8)a-(INT8)(data+c); @@ -871,50 +871,50 @@ INLINE void do_sub_flags(mcs51_regs *mcs51, UINT8 a, UINT8 data, UINT8 c) SET_OV((result1 < -128 || result1 > 127)); } -INLINE void transmit_receive(mcs51_regs *mcs51, int source) +INLINE void transmit_receive(mcs51_state_t *mcs51_state, int source) { int mode = (GET_SM0<<1) | GET_SM1; if (source == 1) /* timer1 */ - mcs51->uart.smod_div = (mcs51->uart.smod_div + 1) & (2-GET_SMOD); + mcs51_state->uart.smod_div = (mcs51_state->uart.smod_div + 1) & (2-GET_SMOD); switch(mode) { //8 bit shifter ( + start,stop bit ) - baud set by clock freq / 12 case 0: - mcs51->uart.rx_clk += (source == 0) ? 16 : 0; /* clock / 12 */ - mcs51->uart.tx_clk += (source == 0) ? 16 : 0; /* clock / 12 */ + mcs51_state->uart.rx_clk += (source == 0) ? 16 : 0; /* clock / 12 */ + mcs51_state->uart.tx_clk += (source == 0) ? 16 : 0; /* clock / 12 */ break; //8 bit uart ( + start,stop bit ) - baud set by timer1 or timer2 case 1: case 3: if (source == 1) { - mcs51->uart.tx_clk += (GET_TCLK ? 0 : !mcs51->uart.smod_div); - mcs51->uart.rx_clk += (GET_RCLK ? 0 : !mcs51->uart.smod_div); + mcs51_state->uart.tx_clk += (GET_TCLK ? 0 : !mcs51_state->uart.smod_div); + mcs51_state->uart.rx_clk += (GET_RCLK ? 0 : !mcs51_state->uart.smod_div); } if (source == 2) { - mcs51->uart.tx_clk += (GET_TCLK ? 1 : 0); - mcs51->uart.rx_clk += (GET_RCLK ? 1 : 0); + mcs51_state->uart.tx_clk += (GET_TCLK ? 1 : 0); + mcs51_state->uart.rx_clk += (GET_RCLK ? 1 : 0); } break; //9 bit uart case 2: - mcs51->uart.rx_clk += (source == 0) ? (GET_SMOD ? 6 : 3) : 0; /* clock / 12 * 3 / 8 (16) = clock / 32 (64)*/ - mcs51->uart.tx_clk += (source == 0) ? (GET_SMOD ? 6 : 3) : 0; /* clock / 12 */ + mcs51_state->uart.rx_clk += (source == 0) ? (GET_SMOD ? 6 : 3) : 0; /* clock / 12 * 3 / 8 (16) = clock / 32 (64)*/ + mcs51_state->uart.tx_clk += (source == 0) ? (GET_SMOD ? 6 : 3) : 0; /* clock / 12 */ break; } /* transmit ? */ - if (mcs51->uart.tx_clk >= 16) + if (mcs51_state->uart.tx_clk >= 16) { - mcs51->uart.tx_clk &= 0x0f; - if(mcs51->uart.bits_to_send) + mcs51_state->uart.tx_clk &= 0x0f; + if(mcs51_state->uart.bits_to_send) { - mcs51->uart.bits_to_send--; - if(mcs51->uart.bits_to_send == 0) { + mcs51_state->uart.bits_to_send--; + if(mcs51_state->uart.bits_to_send == 0) { //Call the callback function - if(mcs51->serial_tx_callback) - mcs51->serial_tx_callback(mcs51->uart.data_out); + if(mcs51_state->serial_tx_callback) + mcs51_state->serial_tx_callback(mcs51_state->uart.data_out); //Set Interrupt Flag SET_TI(1); } @@ -922,18 +922,18 @@ INLINE void transmit_receive(mcs51_regs *mcs51, int source) } /* receive */ - if (mcs51->uart.rx_clk >= 16) + if (mcs51_state->uart.rx_clk >= 16) { - mcs51->uart.rx_clk &= 0x0f; - if (mcs51->uart.delay_cycles>0) + mcs51_state->uart.rx_clk &= 0x0f; + if (mcs51_state->uart.delay_cycles>0) { - mcs51->uart.delay_cycles--; - if (mcs51->uart.delay_cycles == 0) + mcs51_state->uart.delay_cycles--; + if (mcs51_state->uart.delay_cycles == 0) { int data = 0; //Call our callball function to retrieve the data - if(mcs51->serial_rx_callback) - data = mcs51->serial_rx_callback(); + if(mcs51_state->serial_rx_callback) + data = mcs51_state->serial_rx_callback(); LOG(("RX Deliver %d\n", data)); SET_SBUF(data); //Flag the IRQ @@ -944,7 +944,7 @@ INLINE void transmit_receive(mcs51_regs *mcs51, int source) } -INLINE void update_timer_t0(mcs51_regs *mcs51, int cycles) +INLINE void update_timer_t0(mcs51_state_t *mcs51_state, int cycles) { int mode = (GET_M0_1<<1) | GET_M0_0; UINT32 count = 0; @@ -954,9 +954,9 @@ INLINE void update_timer_t0(mcs51_regs *mcs51, int cycles) UINT32 delta; /* counter / external input */ - delta = GET_CT0 ? mcs51->t0_cnt : cycles; + delta = GET_CT0 ? mcs51_state->t0_cnt : cycles; /* taken, reset */ - mcs51->t0_cnt = 0; + mcs51_state->t0_cnt = 0; /* TODO: Not sure about IE0. The manual specifies INT0=high, * which in turn means CLEAR_LINE. * IE0 may be edge triggered depending on IT0 */ @@ -1030,7 +1030,7 @@ switching it into or out of Mode 3 or it can be assigned as a baud rate generato * overflow flag */ -INLINE void update_timer_t1(mcs51_regs *mcs51, int cycles) +INLINE void update_timer_t1(mcs51_state_t *mcs51_state, int cycles) { UINT8 mode = (GET_M1_1<<1) | GET_M1_0; UINT8 mode_0 = (GET_M0_1<<1) | GET_M0_0; @@ -1044,9 +1044,9 @@ INLINE void update_timer_t1(mcs51_regs *mcs51, int cycles) UINT32 overflow = 0; /* counter / external input */ - delta = GET_CT1 ? mcs51->t1_cnt : cycles; + delta = GET_CT1 ? mcs51_state->t1_cnt : cycles; /* taken, reset */ - mcs51->t1_cnt = 0; + mcs51_state->t1_cnt = 0; /* TODO: Not sure about IE0. The manual specifies INT0=high, * which in turn means CLEAR_LINE. Change to access last_state? * IE0 may be edge triggered depending on IT0 */ @@ -1085,7 +1085,7 @@ INLINE void update_timer_t1(mcs51_regs *mcs51, int cycles) if (overflow) { SET_TF1(1); - transmit_receive(mcs51, 1); + transmit_receive(mcs51_state, 1); } } } @@ -1096,7 +1096,7 @@ INLINE void update_timer_t1(mcs51_regs *mcs51, int cycles) delta = cycles; /* taken, reset */ - mcs51->t1_cnt = 0; + mcs51_state->t1_cnt = 0; switch(mode) { case 0: /* 13 Bit Timer Mode */ count = ((TH1<<5) | ( TL1 & 0x1f ) ); @@ -1128,20 +1128,20 @@ INLINE void update_timer_t1(mcs51_regs *mcs51, int cycles) } if (overflow) { - transmit_receive(mcs51, 1); + transmit_receive(mcs51_state, 1); } } } -INLINE void update_timer_t2(mcs51_regs *mcs51, int cycles) +INLINE void update_timer_t2(mcs51_state_t *mcs51_state, int cycles) { /* Update Timer 2 */ if(GET_TR2) { int mode = ((GET_TCLK | GET_RCLK) << 1) | GET_CP; - int delta = GET_CT2 ? mcs51->t2_cnt : (mode & 2) ? cycles * (12/2) : cycles; + int delta = GET_CT2 ? mcs51_state->t2_cnt : (mode & 2) ? cycles * (12/2) : cycles; UINT32 count = ((TH2<<8) | TL2) + delta; - mcs51->t2_cnt = 0; + mcs51_state->t2_cnt = 0; switch (mode) { @@ -1151,10 +1151,10 @@ INLINE void update_timer_t2(mcs51_regs *mcs51, int cycles) SET_TF2(1); count += ((RCAP2H<<8) | RCAP2L); } - else if (GET_EXEN2 && mcs51->t2ex_cnt>0) + else if (GET_EXEN2 && mcs51_state->t2ex_cnt>0) { count += ((RCAP2H<<8) | RCAP2L); - mcs51->t2ex_cnt = 0; + mcs51_state->t2ex_cnt = 0; } TH2 = (count>>8) & 0xff; TL2 = count & 0xff; @@ -1165,11 +1165,11 @@ INLINE void update_timer_t2(mcs51_regs *mcs51, int cycles) TH2 = (count>>8) & 0xff; TL2 = count & 0xff; - if (GET_EXEN2 && mcs51->t2ex_cnt>0) + if (GET_EXEN2 && mcs51_state->t2ex_cnt>0) { RCAP2H = TH2; RCAP2L = TL2; - mcs51->t2ex_cnt = 0; + mcs51_state->t2ex_cnt = 0; } break; case 2: @@ -1177,7 +1177,7 @@ INLINE void update_timer_t2(mcs51_regs *mcs51, int cycles) if ( count & 0xffff0000 ) { count += ((RCAP2H<<8) | RCAP2L); - transmit_receive(mcs51, 2); + transmit_receive(mcs51_state, 2); } TH2 = (count>>8) & 0xff; TL2 = count & 0xff; @@ -1186,36 +1186,36 @@ INLINE void update_timer_t2(mcs51_regs *mcs51, int cycles) } } -INLINE void update_timers(mcs51_regs *mcs51, int cycles) +INLINE void update_timers(mcs51_state_t *mcs51_state, int cycles) { /* Update Timer 0 */ - update_timer_t0(mcs51, cycles); - update_timer_t1(mcs51, cycles); + update_timer_t0(mcs51_state, cycles); + update_timer_t1(mcs51_state, cycles); - if (mcs51->features & FEATURE_I8052) + if (mcs51_state->features & FEATURE_I8052) { - update_timer_t2(mcs51, cycles); + update_timer_t2(mcs51_state, cycles); } } //Set up to transmit data out of serial port //NOTE: Enable Serial Port Interrupt bit is NOT required to send/receive data! -INLINE void serial_transmit(mcs51_regs *mcs51, UINT8 data) +INLINE void serial_transmit(mcs51_state_t *mcs51_state, UINT8 data) { int mode = (GET_SM0<<1) | GET_SM1; //Flag that we're sending data - mcs51->uart.data_out = data; + mcs51_state->uart.data_out = data; LOG(("serial_tansmit: %x %x\n", mode, data)); switch(mode) { //8 bit shifter ( + start,stop bit ) - baud set by clock freq / 12 case 0: - mcs51->uart.bits_to_send = 8+2; + mcs51_state->uart.bits_to_send = 8+2; break; //8 bit uart ( + start,stop bit ) - baud set by timer1 or timer2 case 1: - mcs51->uart.bits_to_send = 8+2; + mcs51_state->uart.bits_to_send = 8+2; break; //9 bit uart case 2: @@ -1225,7 +1225,7 @@ INLINE void serial_transmit(mcs51_regs *mcs51, UINT8 data) } } -INLINE void serial_receive(mcs51_regs *mcs51) +INLINE void serial_receive(mcs51_state_t *mcs51_state) { int mode = (GET_SM0<<1) | GET_SM1; @@ -1233,11 +1233,11 @@ INLINE void serial_receive(mcs51_regs *mcs51) switch(mode) { //8 bit shifter ( + start,stop bit ) - baud set by clock freq / 12 case 0: - mcs51->uart.delay_cycles = 8+2; + mcs51_state->uart.delay_cycles = 8+2; break; //8 bit uart ( + start,stop bit ) - baud set by timer1 or timer2 case 1: - mcs51->uart.delay_cycles = 8+2; + mcs51_state->uart.delay_cycles = 8+2; break; //9 bit uart case 2: @@ -1249,18 +1249,18 @@ INLINE void serial_receive(mcs51_regs *mcs51) } /* Check and update status of serial port */ -INLINE void update_serial(mcs51_regs *mcs51, int cycles) +INLINE void update_serial(mcs51_state_t *mcs51_state, int cycles) { while (--cycles>=0) - transmit_receive(mcs51, 0); + transmit_receive(mcs51_state, 0); } /* Check and update status of serial port */ -INLINE void update_irq_prio(mcs51_regs *mcs51, UINT8 ipl, UINT8 iph) +INLINE void update_irq_prio(mcs51_state_t *mcs51_state, UINT8 ipl, UINT8 iph) { int i; for (i=0; i<8; i++) - mcs51->irq_prio[i] = ((ipl >> i) & 1) | (((iph >>i ) & 1) << 1); + mcs51_state->irq_prio[i] = ((ipl >> i) & 1) | (((iph >>i ) & 1) << 1); } /*************************************************************************** @@ -1284,31 +1284,31 @@ void i8051_set_serial_rx_callback(int (*callback)(void)) OPCODES ***************************************************************************/ -#define OPHANDLER( _name ) INLINE void _name (mcs51_regs *mcs51, UINT8 r) +#define OPHANDLER( _name ) INLINE void _name (mcs51_state_t *mcs51_state, UINT8 r) #include "mcs51ops.c" -static void execute_op(mcs51_regs *mcs51, UINT8 op) +static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) { - if (mcs51->recalc_parity) + if (mcs51_state->recalc_parity) { - set_parity(mcs51); - mcs51->recalc_parity = 0; + set_parity(mcs51_state); + mcs51_state->recalc_parity = 0; } switch( op ) { - case 0x00: nop(mcs51, op); break; //NOP - case 0x01: ajmp(mcs51, op); break; //AJMP code addr - case 0x02: ljmp(mcs51, op); break; //LJMP code addr - case 0x03: rr_a(mcs51, op); break; //RR A - case 0x04: inc_a(mcs51, op); break; //INC A - case 0x05: RWM=1; inc_mem(mcs51, op); RWM=0; break; //INC data addr + case 0x00: nop(mcs51_state, op); break; //NOP + case 0x01: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x02: ljmp(mcs51_state, op); break; //LJMP code addr + case 0x03: rr_a(mcs51_state, op); break; //RR A + case 0x04: inc_a(mcs51_state, op); break; //INC A + case 0x05: RWM=1; inc_mem(mcs51_state, op); RWM=0; break; //INC data addr case 0x06: - case 0x07: inc_ir(mcs51,op&1); break; //INC @R0/@R1 + case 0x07: inc_ir(mcs51_state,op&1); break; //INC @R0/@R1 case 0x08: case 0x09: @@ -1317,17 +1317,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x0c: case 0x0d: case 0x0e: - case 0x0f: inc_r(mcs51, op&7); break; //INC R0 to R7 + case 0x0f: inc_r(mcs51_state, op&7); break; //INC R0 to R7 - case 0x10: RWM=1; jbc(mcs51, op); RWM=0; break; //JBC bit addr, code addr - case 0x11: acall(mcs51, op); break; //ACALL code addr - case 0x12: lcall(mcs51, op); break; //LCALL code addr - case 0x13: rrc_a(mcs51, op); break; //RRC A - case 0x14: dec_a(mcs51, op); break; //DEC A - case 0x15: RWM=1; dec_mem(mcs51, op); RWM=0; break; //DEC data addr + case 0x10: RWM=1; jbc(mcs51_state, op); RWM=0; break; //JBC bit addr, code addr + case 0x11: acall(mcs51_state, op); break; //ACALL code addr + case 0x12: lcall(mcs51_state, op); break; //LCALL code addr + case 0x13: rrc_a(mcs51_state, op); break; //RRC A + case 0x14: dec_a(mcs51_state, op); break; //DEC A + case 0x15: RWM=1; dec_mem(mcs51_state, op); RWM=0; break; //DEC data addr case 0x16: - case 0x17: dec_ir(mcs51, op&1); break; //DEC @R0/@R1 + case 0x17: dec_ir(mcs51_state, op&1); break; //DEC @R0/@R1 case 0x18: case 0x19: @@ -1336,17 +1336,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x1c: case 0x1d: case 0x1e: - case 0x1f: dec_r(mcs51, op&7); break; //DEC R0 to R7 + case 0x1f: dec_r(mcs51_state, op&7); break; //DEC R0 to R7 - case 0x20: jb(mcs51, op); break; //JB bit addr, code addr - case 0x21: ajmp(mcs51, op); break; //AJMP code addr - case 0x22: ret(mcs51, op); break; //RET - case 0x23: rl_a(mcs51, op); break; //RL A - case 0x24: add_a_byte(mcs51, op); break; //ADD A, #data - case 0x25: add_a_mem(mcs51, op); break; //ADD A, data addr + case 0x20: jb(mcs51_state, op); break; //JB bit addr, code addr + case 0x21: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x22: ret(mcs51_state, op); break; //RET + case 0x23: rl_a(mcs51_state, op); break; //RL A + case 0x24: add_a_byte(mcs51_state, op); break; //ADD A, #data + case 0x25: add_a_mem(mcs51_state, op); break; //ADD A, data addr case 0x26: - case 0x27: add_a_ir(mcs51, op&1); break; //ADD A, @R0/@R1 + case 0x27: add_a_ir(mcs51_state, op&1); break; //ADD A, @R0/@R1 case 0x28: case 0x29: @@ -1355,17 +1355,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x2c: case 0x2d: case 0x2e: - case 0x2f: add_a_r(mcs51, op&7); break; //ADD A, R0 to R7 + case 0x2f: add_a_r(mcs51_state, op&7); break; //ADD A, R0 to R7 - case 0x30: jnb(mcs51, op); break; //JNB bit addr, code addr - case 0x31: acall(mcs51, op); break; //ACALL code addr - case 0x32: reti(mcs51, op); break; //RETI - case 0x33: rlc_a(mcs51, op); break; //RLC A - case 0x34: addc_a_byte(mcs51, op); break; //ADDC A, #data - case 0x35: addc_a_mem(mcs51, op); break; //ADDC A, data addr + case 0x30: jnb(mcs51_state, op); break; //JNB bit addr, code addr + case 0x31: acall(mcs51_state, op); break; //ACALL code addr + case 0x32: reti(mcs51_state, op); break; //RETI + case 0x33: rlc_a(mcs51_state, op); break; //RLC A + case 0x34: addc_a_byte(mcs51_state, op); break; //ADDC A, #data + case 0x35: addc_a_mem(mcs51_state, op); break; //ADDC A, data addr case 0x36: - case 0x37: addc_a_ir(mcs51, op&1); break; //ADDC A, @R0/@R1 + case 0x37: addc_a_ir(mcs51_state, op&1); break; //ADDC A, @R0/@R1 case 0x38: case 0x39: @@ -1374,17 +1374,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x3c: case 0x3d: case 0x3e: - case 0x3f: addc_a_r(mcs51, op&7); break; //ADDC A, R0 to R7 + case 0x3f: addc_a_r(mcs51_state, op&7); break; //ADDC A, R0 to R7 - case 0x40: jc(mcs51, op); break; //JC code addr - case 0x41: ajmp(mcs51, op); break; //AJMP code addr - case 0x42: RWM=1; orl_mem_a(mcs51, op); RWM=0; break; //ORL data addr, A - case 0x43: RWM=1; orl_mem_byte(mcs51, op); RWM=0; break; //ORL data addr, #data - case 0x44: orl_a_byte(mcs51, op); break; - case 0x45: orl_a_mem(mcs51, op); break; //ORL A, data addr + case 0x40: jc(mcs51_state, op); break; //JC code addr + case 0x41: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x42: RWM=1; orl_mem_a(mcs51_state, op); RWM=0; break; //ORL data addr, A + case 0x43: RWM=1; orl_mem_byte(mcs51_state, op); RWM=0; break; //ORL data addr, #data + case 0x44: orl_a_byte(mcs51_state, op); break; + case 0x45: orl_a_mem(mcs51_state, op); break; //ORL A, data addr case 0x46: - case 0x47: orl_a_ir(mcs51, op&1); break; //ORL A, @RO/@R1 + case 0x47: orl_a_ir(mcs51_state, op&1); break; //ORL A, @RO/@R1 case 0x48: case 0x49: @@ -1393,17 +1393,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x4c: case 0x4d: case 0x4e: - case 0x4f: orl_a_r(mcs51, op&7); break; //ORL A, RO to R7 + case 0x4f: orl_a_r(mcs51_state, op&7); break; //ORL A, RO to R7 - case 0x50: jnc(mcs51, op); break; //JNC code addr - case 0x51: acall(mcs51, op); break; //ACALL code addr - case 0x52: RWM=1; anl_mem_a(mcs51, op); RWM=0; break; //ANL data addr, A - case 0x53: RWM=1; anl_mem_byte(mcs51, op); RWM=0; break; //ANL data addr, #data - case 0x54: anl_a_byte(mcs51, op); break; //ANL A, #data - case 0x55: anl_a_mem(mcs51, op); break; //ANL A, data addr + case 0x50: jnc(mcs51_state, op); break; //JNC code addr + case 0x51: acall(mcs51_state, op); break; //ACALL code addr + case 0x52: RWM=1; anl_mem_a(mcs51_state, op); RWM=0; break; //ANL data addr, A + case 0x53: RWM=1; anl_mem_byte(mcs51_state, op); RWM=0; break; //ANL data addr, #data + case 0x54: anl_a_byte(mcs51_state, op); break; //ANL A, #data + case 0x55: anl_a_mem(mcs51_state, op); break; //ANL A, data addr case 0x56: - case 0x57: anl_a_ir(mcs51, op&1); break; //ANL A, @RO/@R1 + case 0x57: anl_a_ir(mcs51_state, op&1); break; //ANL A, @RO/@R1 case 0x58: case 0x59: @@ -1412,17 +1412,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x5c: case 0x5d: case 0x5e: - case 0x5f: anl_a_r(mcs51, op&7); break; //ANL A, RO to R7 + case 0x5f: anl_a_r(mcs51_state, op&7); break; //ANL A, RO to R7 - case 0x60: jz(mcs51, op); break; //JZ code addr - case 0x61: ajmp(mcs51, op); break; //AJMP code addr - case 0x62: RWM=1; xrl_mem_a(mcs51, op); RWM=0; break; //XRL data addr, A - case 0x63: RWM=1; xrl_mem_byte(mcs51, op); RWM=0; break; //XRL data addr, #data - case 0x64: xrl_a_byte(mcs51, op); break; //XRL A, #data - case 0x65: xrl_a_mem(mcs51, op); break; //XRL A, data addr + case 0x60: jz(mcs51_state, op); break; //JZ code addr + case 0x61: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x62: RWM=1; xrl_mem_a(mcs51_state, op); RWM=0; break; //XRL data addr, A + case 0x63: RWM=1; xrl_mem_byte(mcs51_state, op); RWM=0; break; //XRL data addr, #data + case 0x64: xrl_a_byte(mcs51_state, op); break; //XRL A, #data + case 0x65: xrl_a_mem(mcs51_state, op); break; //XRL A, data addr case 0x66: - case 0x67: xrl_a_ir(mcs51, op&1); break; //XRL A, @R0/@R1 + case 0x67: xrl_a_ir(mcs51_state, op&1); break; //XRL A, @R0/@R1 case 0x68: case 0x69: @@ -1431,17 +1431,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x6c: case 0x6d: case 0x6e: - case 0x6f: xrl_a_r(mcs51, op&7); break; //XRL A, R0 to R7 + case 0x6f: xrl_a_r(mcs51_state, op&7); break; //XRL A, R0 to R7 - case 0x70: jnz(mcs51, op); break; //JNZ code addr - case 0x71: acall(mcs51, op); break; //ACALL code addr - case 0x72: orl_c_bitaddr(mcs51, op); break; //ORL C, bit addr - case 0x73: jmp_iadptr(mcs51, op); break; //JMP @A+DPTR - case 0x74: mov_a_byte(mcs51, op); break; //MOV A, #data - case 0x75: mov_mem_byte(mcs51, op); break; //MOV data addr, #data + case 0x70: jnz(mcs51_state, op); break; //JNZ code addr + case 0x71: acall(mcs51_state, op); break; //ACALL code addr + case 0x72: orl_c_bitaddr(mcs51_state, op); break; //ORL C, bit addr + case 0x73: jmp_iadptr(mcs51_state, op); break; //JMP @A+DPTR + case 0x74: mov_a_byte(mcs51_state, op); break; //MOV A, #data + case 0x75: mov_mem_byte(mcs51_state, op); break; //MOV data addr, #data case 0x76: - case 0x77: mov_ir_byte(mcs51, op&1); break; //MOV @R0/@R1, #data + case 0x77: mov_ir_byte(mcs51_state, op&1); break; //MOV @R0/@R1, #data case 0x78: case 0x79: @@ -1450,17 +1450,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x7c: case 0x7d: case 0x7e: - case 0x7f: mov_r_byte(mcs51, op&7); break; //MOV R0 to R7, #data + case 0x7f: mov_r_byte(mcs51_state, op&7); break; //MOV R0 to R7, #data - case 0x80: sjmp(mcs51, op); break; //SJMP code addr - case 0x81: ajmp(mcs51, op); break; //AJMP code addr - case 0x82: anl_c_bitaddr(mcs51, op); break; //ANL C, bit addr - case 0x83: movc_a_iapc(mcs51, op); break; //MOVC A, @A + PC - case 0x84: div_ab(mcs51, op); break; //DIV AB - case 0x85: mov_mem_mem(mcs51, op); break; //MOV data addr, data addr + case 0x80: sjmp(mcs51_state, op); break; //SJMP code addr + case 0x81: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x82: anl_c_bitaddr(mcs51_state, op); break; //ANL C, bit addr + case 0x83: movc_a_iapc(mcs51_state, op); break; //MOVC A, @A + PC + case 0x84: div_ab(mcs51_state, op); break; //DIV AB + case 0x85: mov_mem_mem(mcs51_state, op); break; //MOV data addr, data addr case 0x86: - case 0x87: mov_mem_ir(mcs51, op&1); break; //MOV data addr, @R0/@R1 + case 0x87: mov_mem_ir(mcs51_state, op&1); break; //MOV data addr, @R0/@R1 case 0x88: case 0x89: @@ -1469,17 +1469,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x8c: case 0x8d: case 0x8e: - case 0x8f: mov_mem_r(mcs51, op&7); break; //MOV data addr,R0 to R7 + case 0x8f: mov_mem_r(mcs51_state, op&7); break; //MOV data addr,R0 to R7 - case 0x90: mov_dptr_byte(mcs51, op); break; //MOV DPTR, #data - case 0x91: acall(mcs51, op); break; //ACALL code addr - case 0x92: RWM = 1; mov_bitaddr_c(mcs51, op); RWM = 0; break; //MOV bit addr, C - case 0x93: movc_a_iadptr(mcs51, op); break; //MOVC A, @A + DPTR - case 0x94: subb_a_byte(mcs51, op); break; //SUBB A, #data - case 0x95: subb_a_mem(mcs51, op); break; //SUBB A, data addr + case 0x90: mov_dptr_byte(mcs51_state, op); break; //MOV DPTR, #data + case 0x91: acall(mcs51_state, op); break; //ACALL code addr + case 0x92: RWM = 1; mov_bitaddr_c(mcs51_state, op); RWM = 0; break; //MOV bit addr, C + case 0x93: movc_a_iadptr(mcs51_state, op); break; //MOVC A, @A + DPTR + case 0x94: subb_a_byte(mcs51_state, op); break; //SUBB A, #data + case 0x95: subb_a_mem(mcs51_state, op); break; //SUBB A, data addr case 0x96: - case 0x97: subb_a_ir(mcs51, op&1); break; //SUBB A, @R0/@R1 + case 0x97: subb_a_ir(mcs51_state, op&1); break; //SUBB A, @R0/@R1 case 0x98: case 0x99: @@ -1488,17 +1488,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0x9c: case 0x9d: case 0x9e: - case 0x9f: subb_a_r(mcs51, op&7); break; //SUBB A, R0 to R7 + case 0x9f: subb_a_r(mcs51_state, op&7); break; //SUBB A, R0 to R7 - case 0xa0: orl_c_nbitaddr(mcs51, op); break; //ORL C, /bit addr - case 0xa1: ajmp(mcs51, op); break; //AJMP code addr - case 0xa2: mov_c_bitaddr(mcs51, op); break; //MOV C, bit addr - case 0xa3: inc_dptr(mcs51, op); break; //INC DPTR - case 0xa4: mul_ab(mcs51, op); break; //MUL AB - case 0xa5: illegal(mcs51, op); break; //reserved + case 0xa0: orl_c_nbitaddr(mcs51_state, op); break; //ORL C, /bit addr + case 0xa1: ajmp(mcs51_state, op); break; //AJMP code addr + case 0xa2: mov_c_bitaddr(mcs51_state, op); break; //MOV C, bit addr + case 0xa3: inc_dptr(mcs51_state, op); break; //INC DPTR + case 0xa4: mul_ab(mcs51_state, op); break; //MUL AB + case 0xa5: illegal(mcs51_state, op); break; //reserved case 0xa6: - case 0xa7: mov_ir_mem(mcs51, op&1); break; //MOV @R0/@R1, data addr + case 0xa7: mov_ir_mem(mcs51_state, op&1); break; //MOV @R0/@R1, data addr case 0xa8: case 0xa9: @@ -1507,17 +1507,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0xac: case 0xad: case 0xae: - case 0xaf: mov_r_mem(mcs51, op&7); break; //MOV R0 to R7, data addr + case 0xaf: mov_r_mem(mcs51_state, op&7); break; //MOV R0 to R7, data addr - case 0xb0: anl_c_nbitaddr(mcs51, op); break; //ANL C,/bit addr - case 0xb1: acall(mcs51, op); break; //ACALL code addr - case 0xb2: RWM=1; cpl_bitaddr(mcs51, op); RWM=0; break; //CPL bit addr - case 0xb3: cpl_c(mcs51, op); break; //CPL C - case 0xb4: cjne_a_byte(mcs51, op); break; //CJNE A, #data, code addr - case 0xb5: cjne_a_mem(mcs51, op); break; //CJNE A, data addr, code addr + case 0xb0: anl_c_nbitaddr(mcs51_state, op); break; //ANL C,/bit addr + case 0xb1: acall(mcs51_state, op); break; //ACALL code addr + case 0xb2: RWM=1; cpl_bitaddr(mcs51_state, op); RWM=0; break; //CPL bit addr + case 0xb3: cpl_c(mcs51_state, op); break; //CPL C + case 0xb4: cjne_a_byte(mcs51_state, op); break; //CJNE A, #data, code addr + case 0xb5: cjne_a_mem(mcs51_state, op); break; //CJNE A, data addr, code addr case 0xb6: - case 0xb7: cjne_ir_byte(mcs51, op&1); break; //CJNE @R0/@R1, #data, code addr + case 0xb7: cjne_ir_byte(mcs51_state, op&1); break; //CJNE @R0/@R1, #data, code addr case 0xb8: case 0xb9: @@ -1526,17 +1526,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0xbc: case 0xbd: case 0xbe: - case 0xbf: cjne_r_byte(mcs51, op&7); break; //CJNE R0 to R7, #data, code addr + case 0xbf: cjne_r_byte(mcs51_state, op&7); break; //CJNE R0 to R7, #data, code addr - case 0xc0: push(mcs51, op); break; //PUSH data addr - case 0xc1: ajmp(mcs51, op); break; //AJMP code addr - case 0xc2: RWM=1; clr_bitaddr(mcs51, op); RWM=0; break; //CLR bit addr - case 0xc3: clr_c(mcs51, op); break; //CLR C - case 0xc4: swap_a(mcs51, op); break; //SWAP A - case 0xc5: xch_a_mem(mcs51, op); break; //XCH A, data addr + case 0xc0: push(mcs51_state, op); break; //PUSH data addr + case 0xc1: ajmp(mcs51_state, op); break; //AJMP code addr + case 0xc2: RWM=1; clr_bitaddr(mcs51_state, op); RWM=0; break; //CLR bit addr + case 0xc3: clr_c(mcs51_state, op); break; //CLR C + case 0xc4: swap_a(mcs51_state, op); break; //SWAP A + case 0xc5: xch_a_mem(mcs51_state, op); break; //XCH A, data addr case 0xc6: - case 0xc7: xch_a_ir(mcs51, op&1); break; //XCH A, @RO/@R1 + case 0xc7: xch_a_ir(mcs51_state, op&1); break; //XCH A, @RO/@R1 case 0xc8: case 0xc9: @@ -1545,17 +1545,17 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0xcc: case 0xcd: case 0xce: - case 0xcf: xch_a_r(mcs51, op&7); break; //XCH A, RO to R7 + case 0xcf: xch_a_r(mcs51_state, op&7); break; //XCH A, RO to R7 - case 0xd0: pop(mcs51, op); break; //POP data addr - case 0xd1: acall(mcs51, op); break; //ACALL code addr - case 0xd2: RWM=1; setb_bitaddr(mcs51, op); RWM=0; break; //SETB bit addr - case 0xd3: setb_c(mcs51, op); break; //SETB C - case 0xd4: da_a(mcs51, op); break; //DA A - case 0xd5: RWM=1; djnz_mem(mcs51, op); RWM=0; break; //DJNZ data addr, code addr + case 0xd0: pop(mcs51_state, op); break; //POP data addr + case 0xd1: acall(mcs51_state, op); break; //ACALL code addr + case 0xd2: RWM=1; setb_bitaddr(mcs51_state, op); RWM=0; break; //SETB bit addr + case 0xd3: setb_c(mcs51_state, op); break; //SETB C + case 0xd4: da_a(mcs51_state, op); break; //DA A + case 0xd5: RWM=1; djnz_mem(mcs51_state, op); RWM=0; break; //DJNZ data addr, code addr case 0xd6: - case 0xd7: xchd_a_ir(mcs51, op&1); break; //XCHD A, @R0/@R1 + case 0xd7: xchd_a_ir(mcs51_state, op&1); break; //XCHD A, @R0/@R1 case 0xd8: case 0xd9: @@ -1564,18 +1564,18 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0xdc: case 0xdd: case 0xde: - case 0xdf: djnz_r(mcs51, op&7); break; //DJNZ R0 to R7,code addr + case 0xdf: djnz_r(mcs51_state, op&7); break; //DJNZ R0 to R7,code addr - case 0xe0: movx_a_idptr(mcs51, op); break; //MOVX A,@DPTR - case 0xe1: ajmp(mcs51, op); break; //AJMP code addr + case 0xe0: movx_a_idptr(mcs51_state, op); break; //MOVX A,@DPTR + case 0xe1: ajmp(mcs51_state, op); break; //AJMP code addr case 0xe2: - case 0xe3: movx_a_ir(mcs51, op&1); break; //MOVX A, @R0/@R1 + case 0xe3: movx_a_ir(mcs51_state, op&1); break; //MOVX A, @R0/@R1 - case 0xe4: clr_a(mcs51, op); break; //CLR A - case 0xe5: mov_a_mem(mcs51, op); break; //MOV A, data addr + case 0xe4: clr_a(mcs51_state, op); break; //CLR A + case 0xe5: mov_a_mem(mcs51_state, op); break; //MOV A, data addr case 0xe6: - case 0xe7: mov_a_ir(mcs51, op&1); break; //MOV A,@RO/@R1 + case 0xe7: mov_a_ir(mcs51_state, op&1); break; //MOV A,@RO/@R1 case 0xe8: case 0xe9: @@ -1584,19 +1584,19 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0xec: case 0xed: case 0xee: - case 0xef: mov_a_r(mcs51, op&7); break; //MOV A,R0 to R7 + case 0xef: mov_a_r(mcs51_state, op&7); break; //MOV A,R0 to R7 - case 0xf0: movx_idptr_a(mcs51, op); break; //MOVX @DPTR,A - case 0xf1: acall(mcs51, op); break; //ACALL code addr + case 0xf0: movx_idptr_a(mcs51_state, op); break; //MOVX @DPTR,A + case 0xf1: acall(mcs51_state, op); break; //ACALL code addr case 0xf2: - case 0xf3: movx_ir_a(mcs51, op&1); break; //MOVX @R0/@R1,A + case 0xf3: movx_ir_a(mcs51_state, op&1); break; //MOVX @R0/@R1,A - case 0xf4: cpl_a(mcs51, op); break; //CPL A - case 0xf5: mov_mem_a(mcs51, op); break; //MOV data addr, A + case 0xf4: cpl_a(mcs51_state, op); break; //CPL A + case 0xf5: mov_mem_a(mcs51_state, op); break; //MOV data addr, A case 0xf6: - case 0xf7: mov_ir_a(mcs51, op&1); break; //MOV @R0/@R1, A + case 0xf7: mov_ir_a(mcs51_state, op&1); break; //MOV @R0/@R1, A case 0xf8: case 0xf9: @@ -1605,9 +1605,9 @@ static void execute_op(mcs51_regs *mcs51, UINT8 op) case 0xfc: case 0xfd: case 0xfe: - case 0xff: mov_r_a(mcs51, op&7); break; //MOV R0 to R7, A + case 0xff: mov_r_a(mcs51_state, op&7); break; //MOV R0 to R7, A default: - illegal(mcs51, op); + illegal(mcs51_state, op); } } @@ -1652,7 +1652,7 @@ static const UINT8 mcs51_cycles[] = { e) RI+TI f) TF2+EXF2 **********************************************************************************/ -static void check_irqs(mcs51_regs *mcs51) +static void check_irqs(mcs51_state_t *mcs51_state) { UINT8 ints = (GET_IE0 | (GET_TF0<<1) | (GET_IE1<<2) | (GET_TF1<<3) | ((GET_RI|GET_TI)<<4)); @@ -1664,13 +1664,13 @@ static void check_irqs(mcs51_regs *mcs51) //If All Inerrupts Disabled or no pending abort.. int_mask = (GET_EA ? IE : 0x00); - if (mcs51->features & FEATURE_I8052) + if (mcs51_state->features & FEATURE_I8052) ints |= ((GET_TF2|GET_EXF2)<<5); - if (mcs51->features & FEATURE_DS5002FP) + if (mcs51_state->features & FEATURE_DS5002FP) { ints |= ((GET_PFW)<<5); - mcs51->irq_prio[6] = 3; /* force highest priority */ + mcs51_state->irq_prio[6] = 3; /* force highest priority */ /* mask out interrupts not enabled */ ints &= ((int_mask & 0x1f) | ((GET_EPFW)<<5)); } @@ -1683,24 +1683,24 @@ static void check_irqs(mcs51_regs *mcs51) if (!ints) return; /* CLear IDL - got enabled interrupt */ - if (mcs51->features & FEATURE_CMOS) + if (mcs51_state->features & FEATURE_CMOS) { /* any interrupt terminates idle mode */ SET_IDL(0); /* external interrupt wakes up */ if (ints & (GET_IE0 | GET_IE1)) /* but not the DS5002FP */ - if (!(mcs51->features & FEATURE_DS5002FP)) + if (!(mcs51_state->features & FEATURE_DS5002FP)) SET_PD(0); } - for (i=0; inum_interrupts; i++) + for (i=0; inum_interrupts; i++) { if (ints & (1<irq_prio[i] > priority_request) + if (mcs51_state->irq_prio[i] > priority_request) { - priority_request = mcs51->irq_prio[i]; + priority_request = mcs51_state->irq_prio[i]; int_vec = (i<<3) | 3; } } @@ -1711,25 +1711,25 @@ static void check_irqs(mcs51_regs *mcs51) */ LOG(("Request: %d\n", priority_request)); - if (mcs51->irq_active && (priority_request <= mcs51->cur_irq_prio)) + if (mcs51_state->irq_active && (priority_request <= mcs51_state->cur_irq_prio)) { LOG(("higher or equal priority irq in progress already, skipping ...\n")); return; } //Save current pc to stack, set pc to new interrupt vector - push_pc(mcs51); + push_pc(mcs51_state); PC = int_vec; change_pc(PC); /* interrupts take 24 cycles */ - mcs51->inst_cycles += 2; + mcs51_state->inst_cycles += 2; //Set current Irq & Priority being serviced - mcs51->cur_irq_prio = priority_request; - mcs51->irq_active |= (1 << priority_request); + mcs51_state->cur_irq_prio = priority_request; + mcs51_state->irq_active |= (1 << priority_request); - LOG(("Take: %d %02x\n", mcs51->cur_irq_prio, mcs51->irq_active)); + LOG(("Take: %d %02x\n", mcs51_state->cur_irq_prio, mcs51_state->irq_active)); //Clear any interrupt flags that should be cleared since we're servicing the irq! switch(int_vec) { @@ -1739,8 +1739,8 @@ static void check_irqs(mcs51_regs *mcs51) SET_IE0(0); /* indicate we took the external IRQ */ - if (mcs51->irq_callback != NULL) - (*mcs51->irq_callback)(mcs51->device, 0); + if (mcs51_state->irq_callback != NULL) + (*mcs51_state->irq_callback)(mcs51_state->device, 0); break; case V_TF0: @@ -1752,8 +1752,8 @@ static void check_irqs(mcs51_regs *mcs51) if(GET_IT1) /* for some reason having this, breaks alving dmd games */ SET_IE1(0); /* indicate we took the external IRQ */ - if (mcs51->irq_callback != NULL) - (*mcs51->irq_callback)(mcs51->device, 1); + if (mcs51_state->irq_callback != NULL) + (*mcs51_state->irq_callback)(mcs51_state->device, 1); break; case V_TF1: @@ -1776,19 +1776,19 @@ static void check_irqs(mcs51_regs *mcs51) } } -INLINE void burn_cycles(mcs51_regs *mcs51, int cycles) +INLINE void burn_cycles(mcs51_state_t *mcs51_state, int cycles) { /* Update Timer (if any timers are running) */ - update_timers(mcs51, cycles); + update_timers(mcs51_state, cycles); /* Update Serial (only for mode 0) */ - update_serial(mcs51, cycles); + update_serial(mcs51_state, cycles); /* check_irqs */ - check_irqs(mcs51); + check_irqs(mcs51_state); } -static void mcs51_set_irq_line(mcs51_regs *mcs51, int irqline, int state) +static void mcs51_set_irq_line(mcs51_state_t *mcs51_state, int irqline, int state) { /* From the manual: * @@ -1801,9 +1801,9 @@ static void mcs51_set_irq_line(mcs51_regs *mcs51, int irqline, int state) * for at least one cycle (12 states) * */ - UINT32 new_state = (mcs51->last_line_state & ~(1 << irqline)) | ((state != CLEAR_LINE) << irqline); + UINT32 new_state = (mcs51_state->last_line_state & ~(1 << irqline)) | ((state != CLEAR_LINE) << irqline); /* detect 0->1 transistions */ - UINT32 tr_state = (~mcs51->last_line_state) & new_state; + UINT32 tr_state = (~mcs51_state->last_line_state) & new_state; switch( irqline ) { @@ -1849,31 +1849,31 @@ static void mcs51_set_irq_line(mcs51_regs *mcs51, int irqline, int state) case MCS51_T0_LINE: if (GET_BIT(tr_state, MCS51_T0_LINE)) - mcs51->t0_cnt++; + mcs51_state->t0_cnt++; break; case MCS51_T1_LINE: if (GET_BIT(tr_state, MCS51_T1_LINE)) - mcs51->t1_cnt++; + mcs51_state->t1_cnt++; break; case MCS51_T2_LINE: - if (mcs51->features & FEATURE_I8052) + if (mcs51_state->features & FEATURE_I8052) { if (GET_BIT(tr_state, MCS51_T2_LINE)) - mcs51->t2_cnt++; + mcs51_state->t2_cnt++; } else fatalerror("mcs51: Trying to set T2_LINE on a non I8052 type cpu.\n"); break; case MCS51_T2EX_LINE: - if (mcs51->features & FEATURE_I8052) + if (mcs51_state->features & FEATURE_I8052) { if (GET_BIT(tr_state, MCS51_T2EX_LINE)) { SET_EXF2(1); - mcs51->t2ex_cnt++; + mcs51_state->t2ex_cnt++; } } else @@ -1884,13 +1884,13 @@ static void mcs51_set_irq_line(mcs51_regs *mcs51, int irqline, int state) /* Is the enable flags for this interrupt set? */ if (state != CLEAR_LINE) { - serial_receive(mcs51); + serial_receive(mcs51_state); } break; /* Power Fail Interrupt */ case DS5002FP_PFI_LINE: - if (mcs51->features & FEATURE_DS5002FP) + if (mcs51_state->features & FEATURE_DS5002FP) { /* Need cleared->active line transition? (Logical 1-0 Pulse on the line) - CLEAR->ASSERT Transition since INT1 active lo! */ if (GET_BIT(tr_state, MCS51_INT1_LINE)) @@ -1900,40 +1900,40 @@ static void mcs51_set_irq_line(mcs51_regs *mcs51, int irqline, int state) fatalerror("mcs51: Trying to set DS5002FP_PFI_LINE on a non DS5002FP type cpu.\n"); break; } - mcs51->last_line_state = new_state; + mcs51_state->last_line_state = new_state; } /* Execute cycles - returns number of cycles actually run */ static CPU_EXECUTE( mcs51 ) { - mcs51_regs *mcs51 = device->token; + mcs51_state_t *mcs51_state = device->token; UINT8 op; - mcs51->icount = cycles; + mcs51_state->icount = cycles; /* external interrupts may have been set since we last checked */ - mcs51->inst_cycles = 0; - check_irqs(mcs51); + mcs51_state->inst_cycles = 0; + check_irqs(mcs51_state); /* if in powerdown, just return */ - if ((mcs51->features & FEATURE_CMOS) && GET_PD) + if ((mcs51_state->features & FEATURE_CMOS) && GET_PD) { - mcs51->icount = 0; + mcs51_state->icount = 0; return cycles; } - mcs51->icount -= mcs51->inst_cycles; - burn_cycles(mcs51, mcs51->inst_cycles); + mcs51_state->icount -= mcs51_state->inst_cycles; + burn_cycles(mcs51_state, mcs51_state->inst_cycles); - if ((mcs51->features & FEATURE_CMOS) && GET_IDL) + if ((mcs51_state->features & FEATURE_CMOS) && GET_IDL) { do { /* burn the cycles */ - mcs51->icount--; - burn_cycles(mcs51, 1); - } while( mcs51->icount > 0 ); - return cycles - mcs51->icount; + mcs51_state->icount--; + burn_cycles(mcs51_state, 1); + } while( mcs51_state->icount > 0 ); + return cycles - mcs51_state->icount; } do @@ -1944,29 +1944,29 @@ static CPU_EXECUTE( mcs51 ) op = cpu_readop(PC++); /* process opcode and count cycles */ - mcs51->inst_cycles = mcs51_cycles[op]; - execute_op(mcs51, op); + mcs51_state->inst_cycles = mcs51_cycles[op]; + execute_op(mcs51_state, op); /* burn the cycles */ - mcs51->icount -= mcs51->inst_cycles; + mcs51_state->icount -= mcs51_state->inst_cycles; /* if in powerdown, just return */ - if ((mcs51->features & FEATURE_CMOS) && GET_PD) - return cycles - mcs51->icount; + if ((mcs51_state->features & FEATURE_CMOS) && GET_PD) + return cycles - mcs51_state->icount; - burn_cycles(mcs51, mcs51->inst_cycles); + burn_cycles(mcs51_state, mcs51_state->inst_cycles); /* decrement the timed access window */ - if (mcs51->features & FEATURE_DS5002FP) - mcs51->ds5002fp.ta_window = (mcs51->ds5002fp.ta_window ? mcs51->ds5002fp.ta_window-- : 0x00); + if (mcs51_state->features & FEATURE_DS5002FP) + mcs51_state->ds5002fp.ta_window = (mcs51_state->ds5002fp.ta_window ? mcs51_state->ds5002fp.ta_window-- : 0x00); /* If the chip entered in idle mode, end the loop */ - if ((mcs51->features & FEATURE_CMOS) && GET_IDL) - return cycles - mcs51->icount; + if ((mcs51_state->features & FEATURE_CMOS) && GET_IDL) + return cycles - mcs51_state->icount; - } while( mcs51->icount > 0 ); + } while( mcs51_state->icount > 0 ); - return cycles - mcs51->icount; + return cycles - mcs51_state->icount; } @@ -1974,7 +1974,7 @@ static CPU_EXECUTE( mcs51 ) * MCS51/8051 Section ****************************************************************************/ -static void mcs51_sfr_write(mcs51_regs *mcs51, size_t offset, UINT8 data) +static void mcs51_sfr_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 data) { /* update register */ assert(offset >= 0x80 && offset <= 0xff); @@ -1985,10 +1985,10 @@ static void mcs51_sfr_write(mcs51_regs *mcs51, size_t offset, UINT8 data) case ADDR_P1: OUT(MCS51_PORT_P1,data); break; case ADDR_P2: OUT(MCS51_PORT_P2,data); break; case ADDR_P3: OUT(MCS51_PORT_P3,data); break; - case ADDR_SBUF: serial_transmit(mcs51, data); break; + case ADDR_SBUF: serial_transmit(mcs51_state, data); break; case ADDR_PSW: SET_PARITY(); break; case ADDR_ACC: SET_PARITY(); break; - case ADDR_IP: update_irq_prio(mcs51, data, 0); break; + case ADDR_IP: update_irq_prio(mcs51_state, data, 0); break; /* R_SBUF = data; //This register is used only for "Receiving data coming in!" */ case ADDR_B: @@ -2013,7 +2013,7 @@ static void mcs51_sfr_write(mcs51_regs *mcs51, size_t offset, UINT8 data) data_write_byte_8le((size_t)offset | 0x100, data); } -static UINT8 mcs51_sfr_read(mcs51_regs *mcs51, size_t offset) +static UINT8 mcs51_sfr_read(mcs51_state_t *mcs51_state, size_t offset) { assert(offset >= 0x80 && offset <= 0xff); @@ -2055,61 +2055,61 @@ static UINT8 mcs51_sfr_read(mcs51_regs *mcs51, size_t offset) static CPU_INIT( mcs51 ) { - mcs51_regs *mcs51 = device->token; + mcs51_state_t *mcs51_state = device->token; token = device->token; // temporary - mcs51->irq_callback = irqcallback; - mcs51->device = device; + mcs51_state->irq_callback = irqcallback; + mcs51_state->device = device; - mcs51->features = FEATURE_NONE; - mcs51->ram_mask = 0x7F; /* 128 bytes of ram */ - mcs51->num_interrupts = 5; /* 5 interrupts */ - mcs51->sfr_read = mcs51_sfr_read; - mcs51->sfr_write = mcs51_sfr_write; + mcs51_state->features = FEATURE_NONE; + mcs51_state->ram_mask = 0x7F; /* 128 bytes of ram */ + mcs51_state->num_interrupts = 5; /* 5 interrupts */ + mcs51_state->sfr_read = mcs51_sfr_read; + mcs51_state->sfr_write = mcs51_sfr_write; /* Save states */ - state_save_register_item("mcs51", index, mcs51->ppc); - state_save_register_item("mcs51", index, mcs51->pc); - state_save_register_item("mcs51", index, mcs51->rwm ); - state_save_register_item("mcs51", index, mcs51->cur_irq_prio ); - state_save_register_item("mcs51", index, mcs51->last_line_state ); - state_save_register_item("mcs51", index, mcs51->t0_cnt ); - state_save_register_item("mcs51", index, mcs51->t1_cnt ); - state_save_register_item("mcs51", index, mcs51->t2_cnt ); - state_save_register_item("mcs51", index, mcs51->t2ex_cnt ); - state_save_register_item("mcs51", index, mcs51->recalc_parity ); - state_save_register_item_array("mcs51", index, mcs51->irq_prio ); - state_save_register_item("mcs51", index, mcs51->irq_active ); + state_save_register_item("mcs51", index, mcs51_state->ppc); + state_save_register_item("mcs51", index, mcs51_state->pc); + state_save_register_item("mcs51", index, mcs51_state->rwm ); + state_save_register_item("mcs51", index, mcs51_state->cur_irq_prio ); + state_save_register_item("mcs51", index, mcs51_state->last_line_state ); + state_save_register_item("mcs51", index, mcs51_state->t0_cnt ); + state_save_register_item("mcs51", index, mcs51_state->t1_cnt ); + state_save_register_item("mcs51", index, mcs51_state->t2_cnt ); + state_save_register_item("mcs51", index, mcs51_state->t2ex_cnt ); + state_save_register_item("mcs51", index, mcs51_state->recalc_parity ); + state_save_register_item_array("mcs51", index, mcs51_state->irq_prio ); + state_save_register_item("mcs51", index, mcs51_state->irq_active ); } static CPU_INIT( i80c51 ) { - mcs51_regs *mcs51 = device->token; + mcs51_state_t *mcs51_state = device->token; CPU_INIT_CALL(mcs51); - mcs51->features |= FEATURE_CMOS; + mcs51_state->features |= FEATURE_CMOS; } /* Reset registers to the initial values */ static CPU_RESET( mcs51 ) { - mcs51_regs *mcs51 = device->token; + mcs51_state_t *mcs51_state = device->token; - update_ptrs(mcs51); + update_ptrs(mcs51_state); //Set up serial call back handlers - mcs51->serial_tx_callback = hold_serial_tx_callback; + mcs51_state->serial_tx_callback = hold_serial_tx_callback; hold_serial_tx_callback = NULL; - mcs51->serial_rx_callback = hold_serial_rx_callback; + mcs51_state->serial_rx_callback = hold_serial_rx_callback; hold_serial_rx_callback = NULL; - mcs51->last_line_state = 0; - mcs51->t0_cnt = 0; - mcs51->t1_cnt = 0; - mcs51->t2_cnt = 0; - mcs51->t2ex_cnt = 0; + mcs51_state->last_line_state = 0; + mcs51_state->t0_cnt = 0; + mcs51_state->t1_cnt = 0; + mcs51_state->t2_cnt = 0; + mcs51_state->t2ex_cnt = 0; /* Flag as NO IRQ in Progress */ - mcs51->irq_active = 0; - mcs51->cur_irq_prio = -1; + mcs51_state->irq_active = 0; + mcs51_state->cur_irq_prio = -1; /* these are all defined reset states */ PC = 0; @@ -2120,7 +2120,7 @@ static CPU_RESET( mcs51 ) DPL = 0; B = 0; IP = 0; - update_irq_prio(mcs51, IP, 0); + update_irq_prio(mcs51_state, IP, 0); IE = 0; SCON = 0; TCON = 0; @@ -2137,7 +2137,7 @@ static CPU_RESET( mcs51 ) SET_P0(0xff); /* 8052 Only registers */ - if (mcs51->features & FEATURE_I8052) + if (mcs51_state->features & FEATURE_I8052) { T2CON = 0; RCAP2L = 0; @@ -2147,32 +2147,32 @@ static CPU_RESET( mcs51 ) } /* 80C52 Only registers */ - if (mcs51->features & FEATURE_I80C52) + if (mcs51_state->features & FEATURE_I80C52) { IPH = 0; - update_irq_prio(mcs51, IP, IPH); + update_irq_prio(mcs51_state, IP, IPH); SADDR = 0; SADEN = 0; } /* DS5002FP Only registers */ - if (mcs51->features & FEATURE_DS5002FP) + if (mcs51_state->features & FEATURE_DS5002FP) { // set initial values (some of them are set using the bootstrap loader) PCON = 0; - MCON = mcs51->ds5002fp.config->mcon & 0xfb; - RPCTL = mcs51->ds5002fp.config->rpctl & 0x01; + MCON = mcs51_state->ds5002fp.config->mcon & 0xfb; + RPCTL = mcs51_state->ds5002fp.config->rpctl & 0x01; RPS = 0; RNR = 0; - CRCR = mcs51->ds5002fp.config->crc & 0xf0; + CRCR = mcs51_state->ds5002fp.config->crc & 0xf0; CRCL = 0; CRCH = 0; TA = 0; // set internal CPU state - mcs51->ds5002fp.previous_ta = 0; - mcs51->ds5002fp.ta_window = 0; - mcs51->ds5002fp.range = (GET_RG1 << 1) | GET_RG0; + mcs51_state->ds5002fp.previous_ta = 0; + mcs51_state->ds5002fp.ta_window = 0; + mcs51_state->ds5002fp.range = (GET_RG1 << 1) | GET_RG0; } } @@ -2187,7 +2187,7 @@ static CPU_EXIT( mcs51 ) * 8052 Section ****************************************************************************/ -static void i8052_sfr_write(mcs51_regs *mcs51, size_t offset, UINT8 data) +static void i8052_sfr_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 data) { switch (offset) { @@ -2201,11 +2201,11 @@ static void i8052_sfr_write(mcs51_regs *mcs51, size_t offset, UINT8 data) break; default: - mcs51_sfr_write(mcs51, offset, data); + mcs51_sfr_write(mcs51_state, offset, data); } } -static UINT8 i8052_sfr_read(mcs51_regs *mcs51, size_t offset) +static UINT8 i8052_sfr_read(mcs51_state_t *mcs51_state, size_t offset) { switch (offset) { @@ -2217,50 +2217,50 @@ static UINT8 i8052_sfr_read(mcs51_regs *mcs51, size_t offset) case ADDR_TH2: return data_read_byte_8le((size_t) offset | 0x100); default: - return mcs51_sfr_read(mcs51, offset); + return mcs51_sfr_read(mcs51_state, offset); } } static CPU_INIT( i8052 ) { - mcs51_regs *mcs51 = device->token; + mcs51_state_t *mcs51_state = device->token; CPU_INIT_CALL(mcs51); - mcs51->ram_mask = 0xFF; /* 256 bytes of ram */ - mcs51->num_interrupts = 6; /* 6 interrupts */ + mcs51_state->ram_mask = 0xFF; /* 256 bytes of ram */ + mcs51_state->num_interrupts = 6; /* 6 interrupts */ - mcs51->features |= FEATURE_I8052; - mcs51->sfr_read = i8052_sfr_read; - mcs51->sfr_write = i8052_sfr_write; + mcs51_state->features |= FEATURE_I8052; + mcs51_state->sfr_read = i8052_sfr_read; + mcs51_state->sfr_write = i8052_sfr_write; } /**************************************************************************** * 80C52 Section ****************************************************************************/ -static void i80c52_sfr_write(mcs51_regs *mcs51, size_t offset, UINT8 data) +static void i80c52_sfr_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 data) { switch (offset) { /* 80c52 family specific */ case ADDR_IP: - update_irq_prio(mcs51, data, IPH); + update_irq_prio(mcs51_state, data, IPH); break; case ADDR_IPH: - update_irq_prio(mcs51, IP, data); + update_irq_prio(mcs51_state, IP, data); break; case ADDR_SADDR: case ADDR_SADEN: break; default: - i8052_sfr_write(mcs51, offset, data); + i8052_sfr_write(mcs51_state, offset, data); return; } data_write_byte_8le((size_t) offset | 0x100, data); } -static UINT8 i80c52_sfr_read(mcs51_regs *mcs51, size_t offset) +static UINT8 i80c52_sfr_read(mcs51_state_t *mcs51_state, size_t offset) { switch (offset) { @@ -2270,26 +2270,26 @@ static UINT8 i80c52_sfr_read(mcs51_regs *mcs51, size_t offset) case ADDR_SADEN: return data_read_byte_8le((size_t) offset | 0x100); default: - return i8052_sfr_read(mcs51, offset); + return i8052_sfr_read(mcs51_state, offset); } } static CPU_INIT( i80c52 ) { - mcs51_regs *mcs51 = device->token; + mcs51_state_t *mcs51_state = device->token; CPU_INIT_CALL(i8052); - mcs51->features |= (FEATURE_I80C52 | FEATURE_CMOS); - mcs51->sfr_read = i80c52_sfr_read; - mcs51->sfr_write = i80c52_sfr_write; + mcs51_state->features |= (FEATURE_I80C52 | FEATURE_CMOS); + mcs51_state->sfr_read = i80c52_sfr_read; + mcs51_state->sfr_write = i80c52_sfr_write; } static CPU_INIT( i80c31 ) { - mcs51_regs *mcs51 = device->token; + mcs51_state_t *mcs51_state = device->token; CPU_INIT_CALL(i8052); - mcs51->ram_mask = 0x7F; /* 128 bytes of ram */ + mcs51_state->ram_mask = 0x7F; /* 128 bytes of ram */ } /**************************************************************************** @@ -2301,50 +2301,50 @@ static CPU_INIT( i80c31 ) #define DS5_LOGW(a, d) LOG(("ds5002fp #%d: write to " # a " register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, d)) #define DS5_LOGR(a, d) LOG(("ds5002fp #%d: read from " # a " register at 0x%04x\n", cpu_getactivecpu(), PC)) -INLINE UINT8 ds5002fp_protected(mcs51_regs *mcs51, size_t offset, UINT8 data, UINT8 ta_mask, UINT8 mask) +INLINE UINT8 ds5002fp_protected(mcs51_state_t *mcs51_state, size_t offset, UINT8 data, UINT8 ta_mask, UINT8 mask) { UINT8 is_timed_access; - is_timed_access = (mcs51->ds5002fp.ta_window > 0) && (TA == 0x55); + is_timed_access = (mcs51_state->ds5002fp.ta_window > 0) && (TA == 0x55); if (is_timed_access) { ta_mask = 0xff; } - data = (mcs51->sfr_ram[offset] & (~ta_mask)) | (data & ta_mask); - return (mcs51->sfr_ram[offset] & (~mask)) | (data & mask); + data = (mcs51_state->sfr_ram[offset] & (~ta_mask)) | (data & ta_mask); + return (mcs51_state->sfr_ram[offset] & (~mask)) | (data & mask); } -static void ds5002fp_sfr_write(mcs51_regs *mcs51, size_t offset, UINT8 data) +static void ds5002fp_sfr_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 data) { switch (offset) { case ADDR_TA: - mcs51->ds5002fp.previous_ta = TA; + mcs51_state->ds5002fp.previous_ta = TA; /* init the time window after having wrote 0xaa */ - if ((data == 0xaa) && (mcs51->ds5002fp.ta_window == 0)) + if ((data == 0xaa) && (mcs51_state->ds5002fp.ta_window == 0)) { - mcs51->ds5002fp.ta_window = 6; /* 4*12 + 2*12 */ + mcs51_state->ds5002fp.ta_window = 6; /* 4*12 + 2*12 */ LOG(("ds5002fp #%d: TA window initiated at 0x%04x\n", cpu_getactivecpu(), PC)); } break; - case ADDR_MCON: data = ds5002fp_protected(mcs51, ADDR_MCON, data, 0x0f, 0xf7); DS5_LOGW(MCON, data); break; - case ADDR_RPCTL: data = ds5002fp_protected(mcs51, ADDR_RPCTL, data, 0xef, 0xfe); DS5_LOGW(RPCTL, data); break; - case ADDR_CRCR: data = ds5002fp_protected(mcs51, ADDR_CRCR, data, 0xff, 0x0f); DS5_LOGW(CRCR, data); break; - case ADDR_PCON: data = ds5002fp_protected(mcs51, ADDR_PCON, data, 0xb9, 0xff); break; - case ADDR_IP: data = ds5002fp_protected(mcs51, ADDR_IP, data, 0x7f, 0xff); break; + case ADDR_MCON: data = ds5002fp_protected(mcs51_state, ADDR_MCON, data, 0x0f, 0xf7); DS5_LOGW(MCON, data); break; + case ADDR_RPCTL: data = ds5002fp_protected(mcs51_state, ADDR_RPCTL, data, 0xef, 0xfe); DS5_LOGW(RPCTL, data); break; + case ADDR_CRCR: data = ds5002fp_protected(mcs51_state, ADDR_CRCR, data, 0xff, 0x0f); DS5_LOGW(CRCR, data); break; + case ADDR_PCON: data = ds5002fp_protected(mcs51_state, ADDR_PCON, data, 0xb9, 0xff); break; + case ADDR_IP: data = ds5002fp_protected(mcs51_state, ADDR_IP, data, 0x7f, 0xff); break; case ADDR_CRCL: DS5_LOGW(CRCL, data); break; case ADDR_CRCH: DS5_LOGW(CRCH, data); break; case ADDR_RNR: DS5_LOGW(RNR, data); break; case ADDR_RPS: DS5_LOGW(RPS, data); break; default: - mcs51_sfr_write(mcs51, offset, data); + mcs51_sfr_write(mcs51_state, offset, data); return; } data_write_byte_8le((size_t) offset | 0x100, data); } -static UINT8 ds5002fp_sfr_read(mcs51_regs *mcs51, size_t offset) +static UINT8 ds5002fp_sfr_read(mcs51_state_t *mcs51_state, size_t offset) { switch (offset) { @@ -2358,9 +2358,9 @@ static UINT8 ds5002fp_sfr_read(mcs51_regs *mcs51, size_t offset) case ADDR_RPS: DS5_LOGR(RPS, data); break; case ADDR_PCON: SET_PFW(0); /* reset PFW flag */ - return mcs51_sfr_read(mcs51, offset); + return mcs51_sfr_read(mcs51_state, offset); default: - return mcs51_sfr_read(mcs51, offset); + return mcs51_sfr_read(mcs51_state, offset); } return data_read_byte_8le((size_t) offset | 0x100); } @@ -2370,18 +2370,18 @@ static CPU_INIT( ds5002fp ) /* default configuration */ static const ds5002fp_config default_config = { 0x00, 0x00, 0x00 }; const ds5002fp_config *sconfig = device->static_config ? device->static_config : &default_config; - mcs51_regs *mcs51 = device->token; + mcs51_state_t *mcs51_state = device->token; CPU_INIT_CALL( mcs51 ); - mcs51->ds5002fp.config = sconfig; - mcs51->features |= (FEATURE_DS5002FP | FEATURE_CMOS); - mcs51->sfr_read = ds5002fp_sfr_read; - mcs51->sfr_write = ds5002fp_sfr_write; + mcs51_state->ds5002fp.config = sconfig; + mcs51_state->features |= (FEATURE_DS5002FP | FEATURE_CMOS); + mcs51_state->sfr_read = ds5002fp_sfr_read; + mcs51_state->sfr_write = ds5002fp_sfr_write; - state_save_register_item("mcs51", index, mcs51->ds5002fp.previous_ta ); - state_save_register_item("mcs51", index, mcs51->ds5002fp.ta_window ); - state_save_register_item("mcs51", index, mcs51->ds5002fp.range ); + state_save_register_item("mcs51", index, mcs51_state->ds5002fp.previous_ta ); + state_save_register_item("mcs51", index, mcs51_state->ds5002fp.ta_window ); + state_save_register_item("mcs51", index, mcs51_state->ds5002fp.range ); } #endif @@ -2419,14 +2419,14 @@ static CPU_GET_CONTEXT( mcs51 ) static CPU_SET_CONTEXT( mcs51 ) { - mcs51_regs *mcs51; + mcs51_state_t *mcs51_state; if( src ) token = src; - mcs51 = token; + mcs51_state = token; change_pc(PC); - update_ptrs(mcs51); + update_ptrs(mcs51_state); } /************************************************************************** @@ -2435,7 +2435,7 @@ static CPU_SET_CONTEXT( mcs51 ) static CPU_SET_INFO( mcs51 ) { - mcs51_regs *mcs51 = token; + mcs51_state_t *mcs51_state = token; switch (state) { @@ -2443,11 +2443,11 @@ static CPU_SET_INFO( mcs51 ) case CPUINFO_INT_PC: PC = info->i; break; case CPUINFO_INT_SP: SP = info->i; break; - case CPUINFO_INT_INPUT_STATE + MCS51_INT0_LINE: mcs51_set_irq_line(mcs51, MCS51_INT0_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MCS51_INT1_LINE: mcs51_set_irq_line(mcs51, MCS51_INT1_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MCS51_T0_LINE: mcs51_set_irq_line(mcs51, MCS51_T0_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MCS51_T1_LINE: mcs51_set_irq_line(mcs51, MCS51_T1_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MCS51_RX_LINE: mcs51_set_irq_line(mcs51, MCS51_RX_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_INT0_LINE: mcs51_set_irq_line(mcs51_state, MCS51_INT0_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_INT1_LINE: mcs51_set_irq_line(mcs51_state, MCS51_INT1_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_T0_LINE: mcs51_set_irq_line(mcs51_state, MCS51_T0_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_T1_LINE: mcs51_set_irq_line(mcs51_state, MCS51_T1_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_RX_LINE: mcs51_set_irq_line(mcs51_state, MCS51_RX_LINE, info->i); break; case CPUINFO_INT_REGISTER + MCS51_PC: PC = info->i; break; case CPUINFO_INT_REGISTER + MCS51_SP: SP = info->i; break; @@ -2477,12 +2477,12 @@ static CPU_SET_INFO( mcs51 ) static CPU_GET_INFO( mcs51 ) { - mcs51_regs *mcs51 = token; + mcs51_state_t *mcs51_state = token; switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mcs51_regs); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mcs51_state_t); break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; @@ -2535,7 +2535,7 @@ static CPU_GET_INFO( mcs51 ) case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(mcs51); break; case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8051); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mcs51->icount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mcs51_state->icount; break; case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = NULL; break; case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = NULL; break; @@ -2559,7 +2559,7 @@ static CPU_GET_INFO( mcs51 ) PSW & 0x01 ? 'P':'.'); break; - case CPUINFO_STR_REGISTER + MCS51_PC: sprintf(info->s, "PC:%04X", mcs51->pc); break; + case CPUINFO_STR_REGISTER + MCS51_PC: sprintf(info->s, "PC:%04X", mcs51_state->pc); break; case CPUINFO_STR_REGISTER + MCS51_SP: sprintf(info->s, "SP:%02X", SP); break; case CPUINFO_STR_REGISTER + MCS51_PSW: sprintf(info->s, "PSW:%02X", PSW); break; case CPUINFO_STR_REGISTER + MCS51_ACC: sprintf(info->s, "A:%02X", ACC); break;