risc2500: update note

This commit is contained in:
hap 2021-04-23 18:55:16 +02:00
parent 5f977adf3f
commit cf00ff3a96
3 changed files with 14 additions and 11 deletions

View File

@ -33,7 +33,11 @@ Undocumented buttons:
TODO:
- bootrom disable timer shouldn't be needed, real ARM has already fetched the next opcode
- more accurate dynamic cpu clock divider (without the cost of emulation speed)
- More accurate dynamic cpu clock divider, without the cost of emulation speed.
The current implementation catches almost everything, luckily ARM opcodes have a
fixed length. It only fails to detect ALU opcodes that directly modify pc(R15).
It also possibly has problems with very short subroutine calls from ROM to RAM,
but I tested for those and the shortest one is more than 50 cycles.
******************************************************************************/
@ -224,7 +228,7 @@ u32 risc2500_state::disable_boot_rom_r()
{
// disconnect bootrom from the bus after next opcode
if (m_bootrom_enabled && !m_disable_bootrom->enabled() && !machine().side_effects_disabled())
m_disable_bootrom->adjust(m_maincpu->cycles_to_attotime(5));
m_disable_bootrom->adjust(m_maincpu->cycles_to_attotime(10));
return 0;
}
@ -326,7 +330,7 @@ u32 risc2500_state::rom_r(offs_t offset)
if (diff >= 0)
{
static constexpr int arm_branch_cycles = 3;
static constexpr int arm_max_cycles = 17; // block data transfer
static constexpr int arm_max_cycles = 17; // datablock transfer
static constexpr int divider = -8 + 1;
// this takes care of almost all cases, otherwise, total cycles taken can't be determined

View File

@ -240,15 +240,16 @@ The sprites are mapped into RAM locations $F000-$FFFF using only the first
4 bytes from each 32-byte slice. Intervening addresses appear to be
conventional RAM. See the memory map for sprite data format.
****************************************************************************
******************************************************************************
TODO:
- handle transparency in text layer properly (how?)
- second bank of sf02 is this used? (probably NOT)
- empcity/stfight never writes the YM2203s' divider registers but it expects
0x2f, there's a workaround for it in machine_start
- empcity/stfight has an NMI handler, but it's not hooked up in MAME, missing
comms somewhere?
- if empcity turns out to really be a bootleg, maybe it doesn't have an MCU,
and instead does the ADPCM with the audiocpu? (see the driver notes above
mentioning an unused NMI handler)
- Each version of empcity/stfight has a different protection code stored in the
MCU (at $1D2) so each 68705 will need to be dumped.
We currently use hacked versions of the empcityu MCU for each different set.
@ -266,7 +267,6 @@ TODO:
#include "includes/stfight.h"
#include "cpu/z80/z80.h"
#include "sound/ym2203.h"
#include "speaker.h"
@ -457,7 +457,6 @@ INPUT_PORTS_END
void stfight_state::stfight_base(machine_config &config)
{
/* basic machine hardware */
@ -496,7 +495,7 @@ void stfight_state::stfight_base(machine_config &config)
MSM5205(config, m_msm, 384_kHz_XTAL);
m_msm->vck_callback().set(FUNC(stfight_state::stfight_adpcm_int)); // Interrupt function
m_msm->set_prescaler_selector(msm5205_device::S48_4B); // 8KHz, 4-bit
m_msm->set_prescaler_selector(msm5205_device::S48_4B); // 8KHz, 4-bit
m_msm->add_route(ALL_OUTPUTS, "mono", 0.50);
}

View File

@ -180,7 +180,7 @@ u32 tasc_state::input_r()
{
// disconnect bootrom from the bus after next opcode
if (m_bootrom_enabled && !m_disable_bootrom->enabled())
m_disable_bootrom->adjust(m_maincpu->cycles_to_attotime(5));
m_disable_bootrom->adjust(m_maincpu->cycles_to_attotime(10));
m_maincpu->set_input_line(ARM_FIRQ_LINE, CLEAR_LINE);
}
@ -234,7 +234,7 @@ u32 tasc_state::rom_r(offs_t offset)
if (diff >= 0)
{
static constexpr int arm_branch_cycles = 3;
static constexpr int arm_max_cycles = 17; // block data transfer
static constexpr int arm_max_cycles = 17; // datablock transfer
static constexpr int divider = -7 + 1;
// this takes care of almost all cases, otherwise, total cycles taken can't be determined