diff --git a/src/emu/cpu/mn10200/mn10200.c b/src/emu/cpu/mn10200/mn10200.c
index 1131b186bbc..b8bb990d3aa 100644
--- a/src/emu/cpu/mn10200/mn10200.c
+++ b/src/emu/cpu/mn10200/mn10200.c
@@ -50,13 +50,13 @@ mn10200_device::mn10200_device(const machine_config &mconfig, const char *tag, d
 
 void mn10200_device::take_irq(int level, int group)
 {
-	if(!(m_psw & FLAG_IE))
+	if (!(m_psw & FLAG_IE))
 	{
-//      if (group != 8) printf("MN10200: Dropping irq L %d G %d pc=%x, a3=%x\n", level, group, m_pc, m_a[3]);
+		// if (group != 8) printf("MN10200: Dropping irq L %d G %d pc=%x, a3=%x\n", level, group, m_pc, m_a[3]);
 		return;
 	}
 
-//  if (group != 8) printf("MN10200: Taking irq L %d G %d pc=%x, a3=%x\n", level, group, m_pc, m_a[3]);
+	// if (group != 8) printf("MN10200: Taking irq L %d G %d pc=%x, a3=%x\n", level, group, m_pc, m_a[3]);
 
 	m_a[3] -= 6;
 	write_mem24(m_a[3] + 2, m_pc);
@@ -457,17 +457,12 @@ void mn10200_device::do_jsr(UINT32 to, UINT32 ret)
 	write_mem24(m_a[3], ret);
 }
 
-void mn10200_device::do_branch(int offset, bool state)
+void mn10200_device::do_branch(bool state)
 {
 	if (state)
 	{
-		m_cycles -= offset + 1;
-		change_pc(m_pc + offset + 1 + (INT8)read_arg8(m_pc + offset));
-	}
-	else
-	{
-		m_cycles -= offset;
-		m_pc += offset + 1;
+		m_cycles -= 1;
+		change_pc(m_pc + (INT8)read_arg8(m_pc));
 	}
 }
 
@@ -477,7 +472,7 @@ void mn10200_device::execute_set_input(int irqnum, int state)
 {
 	int level = (m_icrh[7]>>4)&0x7;
 
-//  printf("mn102_extirq: irq %d status %d G8 ICRL %x\n", irqnum, status, m_icrl[7]);
+	// printf("mn102_extirq: irq %d status %d G8 ICRL %x\n", irqnum, status, m_icrl[7]);
 
 	// if interrupt is enabled, handle it
 	if (state)
@@ -505,1165 +500,1013 @@ void mn10200_device::execute_run()
 
 		debugger_instruction_hook(this, m_pc);
 
+		m_cycles -= 1;
 		opcode = read_arg8(m_pc);
+		m_pc += 1;
+
 		switch (opcode)
 		{
 			// mov dm, (an)
 			case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
 			case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-				m_cycles -= 1;
 				write_mem16(m_a[opcode >> 2 & 3], (UINT16)m_d[opcode & 3]);
-				m_pc += 1;
 				break;
 
 			// movb dm, (an)
 			case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
 			case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-				m_cycles -= 1;
 				write_mem8(m_a[opcode >> 2 & 3], (UINT8)m_d[opcode & 3]); // note: typo in manual
-				m_pc += 1;
 				break;
 
 			// mov (an), dm
 			case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
 			case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
-				m_cycles -= 1;
 				m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3]);
-				m_pc += 1;
 				break;
 
 			// movbu (an), dm
 			case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
 			case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
-				m_cycles -= 1;
 				m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3]);
-				m_pc += 1;
 				break;
 
 			// mov dm, (d8, an)
 			case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
 			case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
-				m_cycles -= 1;
-				write_mem16((m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 1)), m_d[opcode & 3]);
-				m_pc += 2;
+				write_mem16((m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc)), m_d[opcode & 3]);
+				m_pc += 1;
 				break;
 
 			// mov am, (d8, an)
 			case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
 			case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
-				m_cycles -= 2;
-				write_mem24((m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 1)), m_a[opcode & 3]);
-				m_pc += 2;
+				m_cycles -= 1;
+				write_mem24((m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc)), m_a[opcode & 3]);
+				m_pc += 1;
 				break;
 
 			// mov (d8, an), dm
 			case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
 			case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
-				m_cycles -= 1;
-				m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 1));
-				m_pc += 2;
+				m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc));
+				m_pc += 1;
 				break;
 
 			// mov (d8, an), am
 			case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
 			case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-				m_cycles -= 2;
-				m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 1));
-				m_pc += 2;
+				m_cycles -= 1;
+				m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc));
+				m_pc += 1;
 				break;
 
 			// mov dm, dn
 			case 0x81: case 0x82: case 0x83: case 0x84: case 0x86: case 0x87:
 			case 0x88: case 0x89: case 0x8b: case 0x8c: case 0x8d: case 0x8e:
-				m_cycles -= 1;
 				m_d[opcode & 3] = m_d[opcode >> 2 & 3];
-				m_pc += 1;
 				break;
 
 			// mov imm8, dn
 			case 0x80: case 0x85: case 0x8a: case 0x8f:
-				m_cycles -= 1;
-				m_d[opcode & 3] = (INT8)read_arg8(m_pc + 1);
-				m_pc += 2;
+				m_d[opcode & 3] = (INT8)read_arg8(m_pc);
+				m_pc += 1;
 				break;
 
 			// add dn, dm
 			case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
 			case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
-				m_cycles -= 1;
 				m_d[opcode & 3] = do_add(m_d[opcode & 3], m_d[opcode >> 2 & 3], 0);
-				m_pc += 1;
 				break;
 
 			// sub dn, dm
 			case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
 			case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
-				m_cycles -= 1;
 				m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_d[opcode >> 2 & 3], 0);
-				m_pc += 1;
 				break;
 
 			// extx dn
 			case 0xb0: case 0xb1: case 0xb2: case 0xb3:
-				m_cycles -= 1;
 				m_d[opcode & 3] = (INT16)m_d[opcode & 3];
-				m_pc += 1;
 				break;
 
 			// extxu dn
 			case 0xb4: case 0xb5: case 0xb6: case 0xb7:
-				m_cycles -= 1;
 				m_d[opcode & 3] = (UINT16)m_d[opcode & 3];
-				m_pc += 1;
 				break;
 
 			// extxb dn
 			case 0xb8: case 0xb9: case 0xba: case 0xbb:
-				m_cycles -= 1;
 				m_d[opcode & 3] = (INT8)m_d[opcode & 3];
-				m_pc += 1;
 				break;
 
 			// extxbu dn
 			case 0xbc: case 0xbd: case 0xbe: case 0xbf:
-				m_cycles -= 1;
 				m_d[opcode & 3] = (UINT8)m_d[opcode & 3];
-				m_pc += 1;
 				break;
 
 			// mov dn, (imm16)
 			case 0xc0: case 0xc1: case 0xc2: case 0xc3:
-				m_cycles -= 1;
-				write_mem16(read_arg16(m_pc + 1), m_d[opcode & 3]);
-				m_pc += 3;
+				write_mem16(read_arg16(m_pc), m_d[opcode & 3]);
+				m_pc += 2;
 				break;
 
 			// movb dn, (imm16)
 			case 0xc4: case 0xc5: case 0xc6: case 0xc7:
-				m_cycles -= 1;
-				write_mem8(read_arg16(m_pc + 1), m_d[opcode & 3]);
-				m_pc += 3;
+				write_mem8(read_arg16(m_pc), m_d[opcode & 3]);
+				m_pc += 2;
 				break;
 
 			// mov (abs16), dn
 			case 0xc8: case 0xc9: case 0xca: case 0xcb:
-				m_cycles -= 1;
-				m_d[opcode & 3] = (INT16)read_mem16(read_arg16(m_pc + 1));
-				m_pc += 3;
+				m_d[opcode & 3] = (INT16)read_mem16(read_arg16(m_pc));
+				m_pc += 2;
 				break;
 
 			// movbu (abs16), dn
 			case 0xcc: case 0xcd: case 0xce: case 0xcf:
-				m_cycles -= 1;
-				m_d[opcode & 3] = read_mem8(read_arg16(m_pc + 1));
-				m_pc += 3;
+				m_d[opcode & 3] = read_mem8(read_arg16(m_pc));
+				m_pc += 2;
 				break;
 
 			// add imm8, an
 			case 0xd0: case 0xd1: case 0xd2: case 0xd3:
-				m_cycles -= 1;
-				m_a[opcode & 3] = do_add(m_a[opcode & 3], (INT8)read_arg8(m_pc + 1), 0);
-				m_pc += 2;
+				m_a[opcode & 3] = do_add(m_a[opcode & 3], (INT8)read_arg8(m_pc), 0);
+				m_pc += 1;
 				break;
 
 			// add imm8, dn
 			case 0xd4: case 0xd5: case 0xd6: case 0xd7:
-				m_cycles -= 1;
-				m_d[opcode & 3] = do_add(m_d[opcode & 3], (INT8)read_arg8(m_pc + 1), 0);
-				m_pc += 2;
+				m_d[opcode & 3] = do_add(m_d[opcode & 3], (INT8)read_arg8(m_pc), 0);
+				m_pc += 1;
 				break;
 
 			// cmp imm8, dn
 			case 0xd8: case 0xd9: case 0xda: case 0xdb:
-				m_cycles -= 1;
-				do_sub(m_d[opcode & 3], (INT8)read_arg8(m_pc + 1), 0);
-				m_pc += 2;
+				do_sub(m_d[opcode & 3], (INT8)read_arg8(m_pc), 0);
+				m_pc += 1;
 				break;
 
 			// mov imm16, an
 			case 0xdc: case 0xdd: case 0xde: case 0xdf:
+				m_a[opcode & 3] = read_arg16(m_pc);
+				m_pc += 2;
+				break;
+
+			// blt label8
+			case 0xe0:
+				do_branch(((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_NF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_VF)); // (VF^NF)=1
+				m_pc += 1;
+				break;
+
+			// bgt label8
+			case 0xe1:
+				do_branch(((m_psw & (FLAG_ZF|FLAG_NF|FLAG_VF)) == 0) || ((m_psw & (FLAG_ZF|FLAG_NF|FLAG_VF)) == (FLAG_NF|FLAG_VF))); // ((VF^NF)|ZF)=0
+				m_pc += 1;
+				break;
+
+			// bge label8
+			case 0xe2:
+				do_branch(((m_psw & (FLAG_NF|FLAG_VF)) == 0) || ((m_psw & (FLAG_NF|FLAG_VF)) == (FLAG_NF|FLAG_VF))); // (VF^NF)=0
+				m_pc += 1;
+				break;
+
+			// ble label8
+			case 0xe3:
+				do_branch((m_psw & FLAG_ZF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_NF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_VF)); // ((VF^NF)|ZF)=1
+				m_pc += 1;
+				break;
+
+			// bcs label8
+			case 0xe4:
+				do_branch(m_psw & FLAG_CF); // CF=1
+				m_pc += 1;
+				break;
+
+			// bhi label8
+			case 0xe5:
+				do_branch(!(m_psw & (FLAG_ZF|FLAG_CF))); // (CF|ZF)=0
+				m_pc += 1;
+				break;
+
+			// bcc label8
+			case 0xe6:
+				do_branch(!(m_psw & FLAG_CF)); // CF=0
+				m_pc += 1;
+				break;
+
+			// bls label8
+			case 0xe7:
+				do_branch(m_psw & (FLAG_ZF|FLAG_CF)); // (CF|ZF)=1
+				m_pc += 1;
+				break;
+
+			// beq label8
+			case 0xe8:
+				do_branch(m_psw & FLAG_ZF); // ZF=1
+				m_pc += 1;
+				break;
+
+			// bne label8
+			case 0xe9:
+				do_branch(!(m_psw & FLAG_ZF)); // ZF=0
+				m_pc += 1;
+				break;
+
+			// bra label8
+			case 0xea:
+				do_branch(true);
+				m_pc += 1;
+				break;
+
+			// rti
+			case 0xeb:
+				m_cycles -= 5;
+				m_psw = read_mem16(m_a[3]);
+				change_pc(read_mem24(m_a[3] + 2));
+				m_a[3] += 6;
+				break;
+
+			// cmp imm16, an
+			case 0xec: case 0xed: case 0xee: case 0xef:
+				do_sub(m_a[opcode & 3], read_arg16(m_pc), 0);
+				m_pc += 2;
+				break;
+
+			// extended code f0 (2 bytes)
+			case 0xf0:
 				m_cycles -= 1;
-				m_a[opcode & 3] = read_arg16(m_pc + 1);
+				opcode = read_arg8(m_pc);
+				m_pc += 1;
+
+				switch (opcode)
+				{
+					// jmp (an)
+					case 0x00: case 0x04: case 0x08: case 0x0c:
+						m_cycles -= 1;
+						change_pc(m_a[opcode >> 2 & 3]);
+						break;
+
+					// jsr (an)
+					case 0x01: case 0x05: case 0x09: case 0x0d:
+						m_cycles -= 3;
+						do_jsr(m_a[opcode >> 2 & 3], m_pc);
+						break;
+
+					// bset dm, (an)
+					case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+					case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+					{
+						m_cycles -= 3;
+						UINT8 v = read_mem8(m_a[opcode >> 2 & 3]);
+						test_nz16(v & m_d[opcode & 3]);
+						write_mem8(m_a[opcode >> 2 & 3], v | m_d[opcode & 3]);
+						break;
+					}
+
+					// bclr dm, (an)
+					case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+					case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+					{
+						m_cycles -= 3;
+						UINT8 v = read_mem8(m_a[opcode >> 2 & 3]);
+						test_nz16(v & m_d[opcode & 3]);
+						write_mem8(m_a[opcode >> 2 & 3], v & ~m_d[opcode & 3]);
+						break;
+					}
+
+					// movb (di, an), dm
+					case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+					case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+					case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+					case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+					case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+					case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+					case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
+					case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+						m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
+						break;
+
+					// movbu (di, an), dm
+					case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
+					case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+					case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+					case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+					case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
+					case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+					case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
+					case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
+						m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
+						break;
+
+					// movb dm, (di, an)
+					case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
+					case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
+					case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
+					case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
+					case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
+					case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
+					case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
+					case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
+						write_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_d[opcode & 3]);
+						break;
+
+					default:
+						unemul();
+						break;
+				}
+				break;
+
+			// extended code f1 (2 bytes)
+			case 0xf1:
+				m_cycles -= 1;
+				opcode = read_arg8(m_pc);
+				m_pc += 1;
+
+				switch (opcode >> 6)
+				{
+					// mov (di, an), am
+					case 0:
+						m_cycles -= 1;
+						m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
+						break;
+
+					// mov (di, an), dm
+					case 1:
+						m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
+						break;
+
+					// mov am, (di, an)
+					case 2:
+						m_cycles -= 1;
+						write_mem24(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_a[opcode & 3]);
+						break;
+
+					// mov dm, (di, an)
+					case 3:
+						write_mem16(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_d[opcode & 3]);
+						break;
+				}
+				break;
+
+			// extended code f2 (2 bytes)
+			case 0xf2:
+				m_cycles -= 1;
+				opcode = read_arg8(m_pc);
+				m_pc += 1;
+
+				switch (opcode >> 4)
+				{
+					// add dm, an
+					case 0x0:
+						m_a[opcode & 3] = do_add(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
+						break;
+
+					// sub dm, an
+					case 0x1:
+						m_a[opcode & 3] = do_sub(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
+						break;
+
+					// cmp dm, an
+					case 0x2:
+						do_sub(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
+						break;
+
+					// mov am, dn
+					case 0x3:
+						m_a[opcode & 3] = m_d[opcode >> 2 & 3];
+						break;
+
+					// add am, an
+					case 0x4:
+						m_a[opcode & 3] = do_add(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
+						break;
+
+					// sub am, an
+					case 0x5:
+						m_a[opcode & 3] = do_sub(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
+						break;
+
+					// cmp am, an
+					case 0x6:
+						do_sub(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
+						break;
+
+					// mov am, an
+					case 0x7:
+						m_a[opcode & 3] = m_a[opcode >> 2 & 3];
+						break;
+
+					// addc dm, dn
+					case 0x8:
+						m_d[opcode & 3] = do_add(m_d[opcode & 3], m_d[opcode >> 2 & 3], (m_psw & FLAG_CF) ? 1 : 0);
+						break;
+
+					// subc dm, dn
+					case 0x9:
+						m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_d[opcode >> 2 & 3], (m_psw & FLAG_CF) ? 1 : 0);
+						break;
+
+					// add am, dn
+					case 0xc:
+						m_d[opcode & 3] = do_add(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
+						break;
+
+					// sub am, dn
+					case 0xd:
+						m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
+						break;
+
+					// cmp am, dn
+					case 0xe:
+						do_sub(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
+						break;
+
+					// mov an, dm
+					case 0xf:
+						m_d[opcode & 3] = m_a[opcode >> 2 & 3];
+						break;
+
+					default:
+						unemul();
+						break;
+				}
+				break;
+
+			// extended code f3 (2 bytes)
+			case 0xf3:
+				m_cycles -= 1;
+				opcode = read_arg8(m_pc);
+				m_pc += 1;
+
+				switch (opcode)
+				{
+					// and dm, dn
+					case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
+					case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+						test_nz16(m_d[opcode & 3] &= 0xff0000 | m_d[opcode >> 2 & 3]);
+						break;
+
+					// or dm, dn
+					case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
+					case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+						test_nz16(m_d[opcode & 3] |= 0x00ffff & m_d[opcode >> 2 & 3]);
+						break;
+
+					// xor dm, dn
+					case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+					case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+						test_nz16(m_d[opcode & 3] ^= 0x00ffff & m_d[opcode >> 2 & 3]);
+						break;
+
+					// rol dn
+					case 0x30: case 0x31: case 0x32: case 0x33:
+					{
+						UINT32 d = m_d[opcode & 3];
+						test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d << 1) & 0x00fffe) | ((m_psw & FLAG_CF) ? 1 : 0));
+						if (d & 0x8000)
+							m_psw |= FLAG_CF;
+						break;
+					}
+
+					// ror dn
+					case 0x34: case 0x35: case 0x36: case 0x37:
+					{
+						UINT32 d = m_d[opcode & 3];
+						test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d >> 1) & 0x007fff) | ((m_psw & FLAG_CF) ? 0x8000 : 0));
+						if (d & 1)
+							m_psw |= FLAG_CF;
+						break;
+					}
+
+					// asr dn
+					case 0x38: case 0x39: case 0x3a: case 0x3b:
+					{
+						UINT32 d = m_d[opcode & 3];
+						test_nz16(m_d[opcode & 3] = (d & 0xff8000) | ((d >> 1) & 0x007fff));
+						if (d & 1)
+							m_psw |= FLAG_CF;
+						break;
+					}
+
+					// lsr dn
+					case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+					{
+						UINT32 d = m_d[opcode & 3];
+						test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d >> 1) & 0x007fff));
+						if (d & 1)
+							m_psw |= FLAG_CF;
+						break;
+					}
+
+					// mul dn, dm
+					case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+					case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+					{
+						m_cycles -= 10;
+						UINT32 res = ((INT16)m_d[opcode & 3]) * ((INT16)m_d[opcode >> 2 & 3]);
+						m_d[opcode & 3] = res & 0xffffff;
+						m_psw &= 0xff00; // f4 is undefined
+						if (res & 0x80000000)
+							m_psw |= FLAG_NF;
+						else if (res == 0)
+							m_psw |= FLAG_ZF;
+						m_mdr = res >> 16;
+						break;
+					}
+
+					// mulu dn, dm
+					case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+					case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+					{
+						m_cycles -= 10;
+						UINT32 res = ((UINT16)m_d[opcode & 3]) * ((UINT16)m_d[opcode >> 2 & 3]);
+						m_d[opcode & 3] = res & 0xffffff;
+						m_psw &= 0xff00; // f4 is undefined
+						if (res & 0x80000000)
+							m_psw |= FLAG_NF;
+						else if (res == 0)
+							m_psw |= FLAG_ZF;
+						m_mdr = res >> 16;
+						break;
+					}
+
+					// divu dn, dm
+					case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+					case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+					{
+						UINT32 n, d, q, r;
+						m_cycles -= 11;
+						m_psw &= 0xff00; // f7 may be undefined
+
+						n = (m_mdr << 16) | (UINT16)m_d[opcode & 3];
+						d = (UINT16)m_d[opcode >> 2 & 3];
+						if (d == 0)
+						{
+							// divide by 0
+							m_psw |= FLAG_VF;
+							break;
+						}
+						q = n / d;
+						r = n % d;
+						if (q >= 0x10000)
+						{
+							// overflow (Dm and MDR are undefined)
+							m_psw |= FLAG_VF;
+							break;
+						}
+						m_d[opcode & 3] = q;
+						m_mdr = r;
+						if (q == 0)
+							m_psw |= FLAG_ZF | FLAG_ZX;
+						if (q & 0x8000)
+							m_psw |= FLAG_NF;
+						break;
+					}
+
+					// cmp dm, dn
+					case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+					case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+						do_sub(m_d[opcode & 3], m_d[opcode >> 2 & 3], 0);
+						break;
+
+					// mov mdr, dn
+					case 0xc0: case 0xc4: case 0xc8: case 0xcc:
+						m_mdr = m_d[opcode >> 2 & 3];
+						break;
+
+					// ext dn
+					case 0xc1: case 0xc5: case 0xc9: case 0xcd:
+						m_cycles -= 1;
+						m_mdr = (m_d[opcode >> 2 & 3] & 0x8000) ? 0xffff : 0x0000;
+						break;
+
+					// mov dn, psw
+					case 0xd0: case 0xd4: case 0xd8: case 0xdc:
+						m_cycles -= 1;
+						m_psw = m_d[opcode >> 2 & 3];
+						break;
+
+					// mov dn, mdr
+					case 0xe0: case 0xe1: case 0xe2: case 0xe3:
+						m_d[opcode & 3] = m_mdr;
+						break;
+
+					// not dn
+					case 0xe4: case 0xe5: case 0xe6: case 0xe7:
+						test_nz16(m_d[opcode & 3] ^= 0x00ffff);
+						break;
+
+					// mov psw, dn
+					case 0xf0: case 0xf1: case 0xf2: case 0xf3:
+						m_d[opcode & 3] = m_psw;
+						break;
+
+					default:
+						unemul();
+						break;
+				}
+				break;
+
+			// extended code f4 (5 bytes)
+			case 0xf4:
+				m_cycles -= 1;
+				opcode = read_arg8(m_pc);
+				m_pc += 1;
+				m_cycles -= 1;
+
+				switch (opcode)
+				{
+					// mov dm, (abs24, an)
+					case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
+					case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+						write_mem16(read_arg24(m_pc) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
+						break;
+
+					// mov am, (abs24, an)
+					case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
+					case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+						m_cycles -= 1;
+						write_mem24(read_arg24(m_pc) + m_a[opcode >> 2 & 3], m_a[opcode & 3]);
+						break;
+
+					// movb dm, (abs24, an)
+					case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+					case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+						write_mem8(read_arg24(m_pc) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
+						break;
+
+					// movx dm, (abs24, an)
+					case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+					case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+						m_cycles -= 1;
+						write_mem24(read_arg24(m_pc) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
+						break;
+
+					// mov dn, (abs24)
+					case 0x40: case 0x41: case 0x42: case 0x43:
+						write_mem16(read_arg24(m_pc), m_d[opcode & 3]);
+						break;
+
+					// movb dn, (abs24)
+					case 0x44: case 0x45: case 0x46: case 0x47:
+						write_mem8(read_arg24(m_pc), m_d[opcode & 3]);
+						break;
+
+					// mov an, (abs24)
+					case 0x50: case 0x51: case 0x52: case 0x53:
+						write_mem24(read_arg24(m_pc), m_a[opcode & 3]);
+						break;
+
+					// add abs24, dn
+					case 0x60: case 0x61: case 0x62: case 0x63:
+						m_d[opcode & 3] = do_add(m_d[opcode & 3], read_arg24(m_pc), 0);
+						break;
+
+					// add abs24, an
+					case 0x64: case 0x65: case 0x66: case 0x67:
+						m_a[opcode & 3] = do_add(m_a[opcode & 3], read_arg24(m_pc), 0);
+						break;
+
+					// sub abs24, dn
+					case 0x68: case 0x69: case 0x6a: case 0x6b:
+						m_d[opcode & 3] = do_sub(m_d[opcode & 3], read_arg24(m_pc), 0);
+						break;
+
+					// sub abs24, an
+					case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+						m_a[opcode & 3] = do_sub(m_a[opcode & 3], read_arg24(m_pc), 0);
+						break;
+
+					// mov imm24, dn
+					case 0x70: case 0x71: case 0x72: case 0x73:
+						m_d[opcode & 3] = read_arg24(m_pc);
+						break;
+
+					// mov imm24, an
+					case 0x74: case 0x75: case 0x76: case 0x77:
+						m_a[opcode & 3] = read_arg24(m_pc);
+						break;
+
+					// cmp abs24, dn
+					case 0x78: case 0x79: case 0x7a: case 0x7b:
+						do_sub(m_d[opcode & 3], read_arg24(m_pc), 0);
+						break;
+
+					// cmp abs24, an
+					case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+						do_sub(m_a[opcode & 3], read_arg24(m_pc), 0);
+						break;
+
+					// mov (abs24, an), dm
+					case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
+					case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+						m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + read_arg24(m_pc));
+						break;
+
+					// movbu (abs24, an), dm
+					case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+					case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+						m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + read_arg24(m_pc));
+						break;
+
+					// movb (abs24, an), dm
+					case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
+					case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+						m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + read_arg24(m_pc));
+						break;
+
+					// movx (abs24, an), dm
+					case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
+					case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
+						m_cycles -= 1;
+						m_d[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + read_arg24(m_pc));
+						break;
+
+					// mov (abs24), dn
+					case 0xc0: case 0xc1: case 0xc2: case 0xc3:
+						m_d[opcode & 3] = (INT16)read_mem16(read_arg24(m_pc));
+						break;
+
+					// movb (abs24), dn
+					case 0xc4: case 0xc5: case 0xc6: case 0xc7:
+						m_d[opcode & 3] = (INT8)read_mem8(read_arg24(m_pc));
+						break;
+
+					// movbu (abs24), dn
+					case 0xc8: case 0xc9: case 0xca: case 0xcb:
+						m_d[opcode & 3] = read_mem8(read_arg24(m_pc));
+						break;
+
+					// mov (abs24), an
+					case 0xd0: case 0xd1: case 0xd2: case 0xd3:
+						m_a[opcode & 3] = read_mem24(read_arg24(m_pc));
+						break;
+
+					// jmp imm24
+					case 0xe0:
+						m_cycles -= 1;
+						change_pc(m_pc + read_arg24(m_pc));
+						break;
+
+					// jsr label24
+					case 0xe1:
+						m_cycles -= 2;
+						do_jsr(m_pc + read_arg24(m_pc), m_pc + 3);
+						break;
+
+					// mov (abs24, an), am
+					case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
+					case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
+						m_cycles -= 1;
+						m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + read_arg24(m_pc));
+						break;
+
+					default:
+						unemul();
+						break;
+				}
 				m_pc += 3;
 				break;
 
-		// blt label8
-		case 0xe0:
-			do_branch(1, ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_NF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_VF)); // (VF^NF)=1
-			break;
+			// extended code f5 (3 bytes)
+			case 0xf5:
+				m_cycles -= 1;
+				opcode = read_arg8(m_pc);
+				m_pc += 1;
 
-		// bgt label8
-		case 0xe1:
-			do_branch(1, ((m_psw & (FLAG_ZF|FLAG_NF|FLAG_VF)) == 0) || ((m_psw & (FLAG_ZF|FLAG_NF|FLAG_VF)) == (FLAG_NF|FLAG_VF))); // ((VF^NF)|ZF)=0
-			break;
-
-		// bge label8
-		case 0xe2:
-			do_branch(1, ((m_psw & (FLAG_NF|FLAG_VF)) == 0) || ((m_psw & (FLAG_NF|FLAG_VF)) == (FLAG_NF|FLAG_VF))); // (VF^NF)=0
-			break;
-
-		// ble label8
-		case 0xe3:
-			do_branch(1, (m_psw & FLAG_ZF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_NF) || ((m_psw & (FLAG_NF|FLAG_VF)) == FLAG_VF)); // ((VF^NF)|ZF)=1
-			break;
-
-		// bcs label8
-		case 0xe4:
-			do_branch(1, m_psw & FLAG_CF); // CF=1
-			break;
-
-		// bhi label8
-		case 0xe5:
-			do_branch(1, !(m_psw & (FLAG_ZF|FLAG_CF))); // (CF|ZF)=0
-			break;
-
-		// bcc label8
-		case 0xe6:
-			do_branch(1, !(m_psw & FLAG_CF)); // CF=0
-			break;
-
-		// bls label8
-		case 0xe7:
-			do_branch(1, m_psw & (FLAG_ZF|FLAG_CF)); // (CF|ZF)=1
-			break;
-
-		// beq label8
-		case 0xe8:
-			do_branch(1, m_psw & FLAG_ZF); // ZF=1
-			break;
-
-		// bne label8
-		case 0xe9:
-			do_branch(1, !(m_psw & FLAG_ZF)); // ZF=0
-			break;
-
-		// bra label8
-		case 0xea:
-			do_branch(1, true);
-			break;
-
-		// rti
-		case 0xeb:
-			m_cycles -= 6;
-			m_psw = read_mem16(m_a[3]);
-			change_pc(read_mem24(m_a[3] + 2));
-			m_a[3] += 6;
-			break;
-
-		// cmp imm16, an
-		case 0xec: case 0xed: case 0xee: case 0xef:
-			m_cycles -= 1;
-			do_sub(m_a[opcode & 3], read_arg16(m_pc + 1), 0);
-			m_pc += 3;
-			break;
-
-		// extended code f0 (2 bytes)
-		case 0xf0:
-			opcode = read_arg8(m_pc + 1);
-			switch (opcode)
-			{
-				// jmp (an)
-				case 0x00: case 0x04: case 0x08: case 0x0c:
-					m_cycles -= 3;
-					change_pc(m_a[opcode >> 2 & 3]);
-					break;
-
-				// jsr (an)
-				case 0x01: case 0x05: case 0x09: case 0x0d:
-					m_cycles -= 5;
-					do_jsr(m_a[opcode >> 2 & 3], m_pc + 2);
-					break;
-
-				// bset dm, (an)
-				case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
-				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+				switch (opcode)
 				{
-					m_cycles -= 5;
-					UINT8 v = read_mem8(m_a[opcode >> 2 & 3]);
-					test_nz16(v & m_d[opcode & 3]);
-					write_mem8(m_a[opcode >> 2 & 3], v | m_d[opcode & 3]);
-					m_pc += 2;
-					break;
+					// and imm8, dn
+					case 0x00: case 0x01: case 0x02: case 0x03:
+						test_nz16(m_d[opcode & 3] &= 0xff0000 | read_arg8(m_pc));
+						break;
+
+					// btst imm8, dn
+					case 0x04: case 0x05: case 0x06: case 0x07:
+						test_nz16(m_d[opcode & 3] & read_arg8(m_pc));
+						break;
+
+					// or imm8, dn
+					case 0x08: case 0x09: case 0x0a: case 0x0b:
+						test_nz16(m_d[opcode & 3] |= read_arg8(m_pc));
+						break;
+
+					// addnf imm8, an
+					case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+						m_a[opcode & 3] = m_a[opcode & 3] + (INT8)read_arg8(m_pc);
+						break;
+
+					// movb dm, (d8, an)
+					case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
+					case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+						write_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc), m_d[opcode & 3]);
+						break;
+
+					// movb (d8, an), dm
+					case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+					case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+						m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc));
+						break;
+
+					// movbu (d8, an), dm
+					case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+					case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+						m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc));
+						break;
+
+					// movx dm, (d8, an)
+					case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+					case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+						m_cycles -= 1;
+						write_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc), m_d[opcode & 3]);
+						break;
+
+					// movx (d8, an), dm
+					case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
+					case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+						m_cycles -= 1;
+						m_d[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc));
+						break;
+
+					// bltx label8
+					case 0xe0:
+						do_branch(((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_NX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_VX)); // (VX^NX)=1
+						break;
+
+					// bgtx label8
+					case 0xe1:
+						do_branch(((m_psw & (FLAG_ZX|FLAG_NX|FLAG_VX)) == 0) || ((m_psw & (FLAG_ZX|FLAG_NX|FLAG_VX)) == (FLAG_NX|FLAG_VX))); // ((VX^NX)|ZX)=0
+						break;
+
+					// bgex label8
+					case 0xe2:
+						do_branch(((m_psw & (FLAG_NX|FLAG_VX)) == 0) || ((m_psw & (FLAG_NX|FLAG_VX)) == (FLAG_NX|FLAG_VX))); // (VX^NX)=0
+						break;
+
+					// blex label8
+					case 0xe3:
+						do_branch((m_psw & FLAG_ZX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_NX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_VX)); // ((VX^NX)|ZX)=1
+						break;
+
+					// bcsx label8
+					case 0xe4:
+						do_branch(m_psw & FLAG_CX); // CX=1
+						break;
+
+					// bhix label8
+					case 0xe5:
+						do_branch(!(m_psw & (FLAG_ZX|FLAG_CX))); // (CX|ZX)=0
+						break;
+
+					// bccx label8
+					case 0xe6:
+						do_branch(!(m_psw & FLAG_CX)); // CX=0
+						break;
+
+					// blsx label8
+					case 0xe7:
+						do_branch(m_psw & (FLAG_ZX|FLAG_CX)); // (CX|ZX)=1
+						break;
+
+					// beqx label8
+					case 0xe8:
+						do_branch(m_psw & FLAG_ZX); // ZX=1
+						break;
+
+					// bnex label8
+					case 0xe9:
+						do_branch(!(m_psw & FLAG_ZX)); // ZX=0
+						break;
+
+					// bnc label8
+					case 0xfe:
+						do_branch(!(m_psw & FLAG_NF)); // NF=0
+						break;
+
+					default:
+						unemul();
+						break;
 				}
-
-				// bclr dm, (an)
-				case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
-				case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
-				{
-					m_cycles -= 5;
-					UINT8 v = read_mem8(m_a[opcode >> 2 & 3]);
-					test_nz16(v & m_d[opcode & 3]);
-					write_mem8(m_a[opcode >> 2 & 3], v & ~m_d[opcode & 3]);
-					m_pc += 2;
-					break;
-				}
-
-				// movb (di, an), dm
-				case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
-				case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
-				case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
-				case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
-				case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
-				case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
-				case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
-				case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-					m_cycles -= 2;
-					m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
-					m_pc += 2;
-					break;
-
-				// movbu (di, an), dm
-				case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
-				case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
-				case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
-				case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
-				case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
-				case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
-				case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
-				case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
-					m_cycles -= 2;
-					m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
-					m_pc += 2;
-					break;
-
-				// movb dm, (di, an)
-				case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
-				case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
-				case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
-				case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
-				case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
-				case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
-				case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
-				case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
-					m_cycles -= 2;
-					write_mem8(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_d[opcode & 3]);
-					m_pc += 2;
-					break;
-
-				default:
-					unemul();
-					break;
-			}
-			break;
-
-		// extended code f1 (2 bytes)
-		case 0xf1:
-			opcode = read_arg8(m_pc + 1);
-			switch (opcode >> 6)
-			{
-				// mov (di, an), am
-				case 0:
-					m_cycles -= 3;
-					m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
-					m_pc += 2;
-					break;
-
-				// mov (di, an), dm
-				case 1:
-					m_cycles -= 2;
-					m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3]);
-					m_pc += 2;
-					break;
-
-				// mov am, (di, an)
-				case 2:
-					m_cycles -= 3;
-					write_mem24(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_a[opcode & 3]);
-					m_pc += 2;
-					break;
-
-				// mov dm, (di, an)
-				case 3:
-					m_cycles -= 2;
-					write_mem16(m_a[opcode >> 2 & 3] + m_d[opcode >> 4 & 3], m_d[opcode & 3]);
-					m_pc += 2;
-					break;
-			}
-			break;
-
-		// extended code f2 (2 bytes)
-		case 0xf2:
-			opcode = read_arg8(m_pc + 1);
-			switch (opcode >> 4)
-			{
-				// add dm, an
-				case 0x0:
-					m_cycles -= 2;
-					m_a[opcode & 3] = do_add(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// sub dm, an
-				case 0x1:
-					m_cycles -= 2;
-					m_a[opcode & 3] = do_sub(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// cmp dm, an
-				case 0x2:
-					m_cycles -= 2;
-					do_sub(m_a[opcode & 3], m_d[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// mov am, dn
-				case 0x3:
-					m_cycles -= 2;
-					m_a[opcode & 3] = m_d[opcode >> 2 & 3];
-					m_pc += 2;
-					break;
-
-				// add am, an
-				case 0x4:
-					m_cycles -= 2;
-					m_a[opcode & 3] = do_add(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// sub am, an
-				case 0x5:
-					m_cycles -= 2;
-					m_a[opcode & 3] = do_sub(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// cmp am, an
-				case 0x6:
-					m_cycles -= 2;
-					do_sub(m_a[opcode & 3], m_a[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// mov am, an
-				case 0x7:
-					m_cycles -= 2;
-					m_a[opcode & 3] = m_a[opcode >> 2 & 3];
-					m_pc += 2;
-					break;
-
-				// addc dm, dn
-				case 0x8:
-					m_cycles -= 2;
-					m_d[opcode & 3] = do_add(m_d[opcode & 3], m_d[opcode >> 2 & 3], (m_psw & FLAG_CF) ? 1 : 0);
-					m_pc += 2;
-					break;
-
-				// subc dm, dn
-				case 0x9:
-					m_cycles -= 2;
-					m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_d[opcode >> 2 & 3], (m_psw & FLAG_CF) ? 1 : 0);
-					m_pc += 2;
-					break;
-
-				// add am, dn
-				case 0xc:
-					m_cycles -= 2;
-					m_d[opcode & 3] = do_add(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// sub am, dn
-				case 0xd:
-					m_cycles -= 2;
-					m_d[opcode & 3] = do_sub(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// cmp am, dn
-				case 0xe:
-					m_cycles -= 2;
-					do_sub(m_d[opcode & 3], m_a[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// mov an, dm
-				case 0xf:
-					m_cycles -= 2;
-					m_d[opcode & 3] = m_a[opcode >> 2 & 3];
-					m_pc += 2;
-					break;
-
-				default:
-					unemul();
-					break;
-			}
-			break;
-
-		// extended code f3 (2 bytes)
-		case 0xf3:
-			opcode = read_arg8(m_pc + 1);
-			switch (opcode)
-			{
-				// and dm, dn
-				case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
-				case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] &= 0xff0000 | m_d[opcode >> 2 & 3]);
-					m_pc += 2;
-					break;
-
-				// or dm, dn
-				case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
-				case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] |= 0x00ffff & m_d[opcode >> 2 & 3]);
-					m_pc += 2;
-					break;
-
-				// xor dm, dn
-				case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
-				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] ^= 0x00ffff & m_d[opcode >> 2 & 3]);
-					m_pc += 2;
-					break;
-
-				// rol dn
-				case 0x30: case 0x31: case 0x32: case 0x33:
-				{
-					UINT32 d = m_d[opcode & 3];
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d << 1) & 0x00fffe) | ((m_psw & FLAG_CF) ? 1 : 0));
-					if (d & 0x8000)
-						m_psw |= FLAG_CF;
-					m_pc += 2;
-					break;
-				}
-
-				// ror dn
-				case 0x34: case 0x35: case 0x36: case 0x37:
-				{
-					UINT32 d = m_d[opcode & 3];
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d >> 1) & 0x007fff) | ((m_psw & FLAG_CF) ? 0x8000 : 0));
-					if (d & 1)
-						m_psw |= FLAG_CF;
-					m_pc += 2;
-					break;
-				}
-
-				// asr dn
-				case 0x38: case 0x39: case 0x3a: case 0x3b:
-				{
-					UINT32 d = m_d[opcode & 3];
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] = (d & 0xff8000) | ((d >> 1) & 0x007fff));
-					if (d & 1)
-						m_psw |= FLAG_CF;
-					m_pc += 2;
-					break;
-				}
-
-				// lsr dn
-				case 0x3c: case 0x3d: case 0x3e: case 0x3f:
-				{
-					UINT32 d = m_d[opcode & 3];
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] = (d & 0xff0000) | ((d >> 1) & 0x007fff));
-					if (d & 1)
-						m_psw |= FLAG_CF;
-					m_pc += 2;
+				m_pc += 1;
 				break;
-				}
 
-				// mul dn, dm
-				case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
-				case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+			// nop
+			case 0xf6:
+				break;
+
+			// extended code f7 (4 bytes)
+			case 0xf7:
+				m_cycles -= 1;
+				opcode = read_arg8(m_pc);
+				m_pc += 1;
+
+				switch (opcode)
 				{
-					m_cycles -= 12;
-					UINT32 res = ((INT16)m_d[opcode & 3]) * ((INT16)m_d[opcode >> 2 & 3]);
-					m_d[opcode & 3] = res & 0xffffff;
-					m_psw &= 0xff00; // f4 is undefined
-					if (res & 0x80000000)
-						m_psw |= FLAG_NF;
-					else if (res == 0)
-						m_psw |= FLAG_ZF;
-					m_mdr = res >> 16;
-					m_pc += 2;
-					break;
-				}
-
-				// mulu dn, dm
-				case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
-				case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
-				{
-					m_cycles -= 12;
-					UINT32 res = ((UINT16)m_d[opcode & 3]) * ((UINT16)m_d[opcode >> 2 & 3]);
-					m_d[opcode & 3] = res & 0xffffff;
-					m_psw &= 0xff00; // f4 is undefined
-					if (res & 0x80000000)
-						m_psw |= FLAG_NF;
-					else if (res == 0)
-						m_psw |= FLAG_ZF;
-					m_mdr = res >> 16;
-					m_pc += 2;
-					break;
-				}
-
-				// divu dn, dm
-				case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
-				case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
-				{
-					UINT32 n, d, q, r;
-					m_cycles -= 13;
-					m_pc += 2;
-					m_psw &= 0xff00; // f7 may be undefined
-
-					n = (m_mdr << 16) | (UINT16)m_d[opcode & 3];
-					d = (UINT16)m_d[opcode >> 2 & 3];
-					if (d == 0)
-					{
-						// divide by 0
-						m_psw |= FLAG_VF;
+					// and imm16, dn
+					case 0x00: case 0x01: case 0x02: case 0x03:
+						test_nz16(m_d[opcode & 3] &= 0xff0000 | read_arg16(m_pc));
 						break;
-					}
-					q = n / d;
-					r = n % d;
-					if (q >= 0x10000)
-					{
-						// overflow (Dm and MDR are undefined)
-						m_psw |= FLAG_VF;
+
+					// btst imm16, dn
+					case 0x04: case 0x05: case 0x06: case 0x07:
+						test_nz16(m_d[opcode & 3] & read_arg16(m_pc));
+						break;
+
+					// add imm16, an
+					case 0x08: case 0x09: case 0x0a: case 0x0b:
+						m_a[opcode & 3] = do_add(m_a[opcode & 3], (INT16)read_arg16(m_pc), 0);
+						break;
+
+					// sub imm16, an
+					case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+						m_a[opcode & 3] = do_sub(m_a[opcode & 3], (INT16)read_arg16(m_pc), 0);
+						break;
+
+					// and imm16, psw
+					case 0x10:
+						m_cycles -= 1;
+						m_psw &= read_arg16(m_pc);
+						break;
+
+					// or imm16, psw
+					case 0x14:
+						m_cycles -= 1;
+						m_psw |= read_arg16(m_pc);
+						break;
+
+					// add imm16, dn
+					case 0x18: case 0x19: case 0x1a: case 0x1b:
+						m_d[opcode & 3] = do_add(m_d[opcode & 3], (INT16)read_arg16(m_pc), 0);
+						break;
+
+					// sub imm16, dn
+					case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+						m_d[opcode & 3] = do_sub(m_d[opcode & 3], (INT16)read_arg16(m_pc), 0);
+						break;
+
+					// or imm16, dn
+					case 0x40: case 0x41: case 0x42: case 0x43:
+						test_nz16(m_d[opcode & 3] |= read_arg16(m_pc));
+						break;
+
+					// cmp imm16, dn
+					case 0x48: case 0x49: case 0x4a: case 0x4b:
+						do_sub(m_d[opcode & 3], (INT16)read_arg16(m_pc), 0);
+						break;
+
+					// xor imm16, dn
+					case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+						m_cycles -= 1;
+						test_nz16(m_d[opcode & 3] ^= read_arg16(m_pc));
+						break;
+
+					// mov dm, (imm16, an)
+					case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
+					case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+						write_mem16(m_a[opcode >> 2 & 3] + (INT16)read_arg16(m_pc), (UINT16)m_d[opcode & 3]);
+						break;
+
+					// mov (imm16, an), dm
+					case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
+					case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
+						m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + (INT16)read_arg16(m_pc));
+						break;
+
+					default:
+						unemul();
 						break;
-					}
-					m_d[opcode & 3] = q;
-					m_mdr = r;
-					if (q == 0)
-						m_psw |= FLAG_ZF | FLAG_ZX;
-					if (q & 0x8000)
-						m_psw |= FLAG_NF;
-					break;
 				}
-
-				// cmp dm, dn
-				case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
-				case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
-					m_cycles -= 2;
-					do_sub(m_d[opcode & 3], m_d[opcode >> 2 & 3], 0);
-					m_pc += 2;
-					break;
-
-				// mov mdr, dn
-				case 0xc0: case 0xc4: case 0xc8: case 0xcc:
-					m_cycles -= 2;
-					m_mdr = m_d[opcode >> 2 & 3];
-					m_pc += 2;
-					break;
-
-				// ext dn
-				case 0xc1: case 0xc5: case 0xc9: case 0xcd:
-					m_cycles -= 3;
-					m_mdr = (m_d[opcode >> 2 & 3] & 0x8000) ? 0xffff : 0x0000;
-					m_pc += 2;
-					break;
-
-				// mov dn, psw
-				case 0xd0: case 0xd4: case 0xd8: case 0xdc:
-					m_cycles -= 3;
-					m_psw = m_d[opcode >> 2 & 3];
-					m_pc += 2;
-					break;
-
-				// mov dn, mdr
-				case 0xe0: case 0xe1: case 0xe2: case 0xe3:
-					m_cycles -= 2;
-					m_d[opcode & 3] = m_mdr;
-					m_pc += 2;
-					break;
-
-				// not dn
-				case 0xe4: case 0xe5: case 0xe6: case 0xe7:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] ^= 0x00ffff);
-					m_pc += 2;
-					break;
-
-				// mov psw, dn
-				case 0xf0: case 0xf1: case 0xf2: case 0xf3:
-					m_cycles -= 2;
-					m_d[opcode & 3] = m_psw;
-					m_pc += 2;
-					break;
-
-				default:
-					unemul();
-					break;
-			}
-			break;
-
-		// extended code f4 (5 bytes)
-		case 0xf4:
-			opcode = read_arg8(m_pc + 1);
-			switch (opcode)
-			{
-				// mov dm, (abs24, an)
-				case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
-				case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-					m_cycles -= 3;
-					write_mem16(read_arg24(m_pc + 2) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
-					m_pc += 5;
-					break;
-
-				// mov am, (abs24, an)
-				case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
-				case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-					m_cycles -= 4;
-					write_mem24(read_arg24(m_pc + 2) + m_a[opcode >> 2 & 3], m_a[opcode & 3]);
-					m_pc += 5;
-					break;
-
-				// movb dm, (abs24, an)
-				case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
-				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
-					m_cycles -= 3;
-					write_mem8(read_arg24(m_pc + 2) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
-					m_pc += 5;
-					break;
-
-				// movx dm, (abs24, an)
-				case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
-				case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
-					m_cycles -= 4;
-					write_mem24(read_arg24(m_pc + 2) + m_a[opcode >> 2 & 3], m_d[opcode & 3]);
-					m_pc += 5;
-					break;
-
-				// mov dn, (abs24)
-				case 0x40: case 0x41: case 0x42: case 0x43:
-					m_cycles -= 3;
-					write_mem16(read_arg24(m_pc + 2), m_d[opcode & 3]);
-					m_pc += 5;
-					break;
-
-				// movb dn, (abs24)
-				case 0x44: case 0x45: case 0x46: case 0x47:
-					m_cycles -= 3;
-					write_mem8(read_arg24(m_pc + 2), m_d[opcode & 3]);
-					m_pc += 5;
-					break;
-
-				// mov an, (abs24)
-				case 0x50: case 0x51: case 0x52: case 0x53:
-					m_cycles -= 4;
-					write_mem24(read_arg24(m_pc + 2), m_a[opcode & 3]);
-					m_pc += 5;
-					break;
-
-				// add abs24, dn
-				case 0x60: case 0x61: case 0x62: case 0x63:
-					m_cycles -= 3;
-					m_d[opcode & 3] = do_add(m_d[opcode & 3], read_arg24(m_pc + 2), 0);
-					m_pc += 5;
-					break;
-
-				// add abs24, an
-				case 0x64: case 0x65: case 0x66: case 0x67:
-					m_cycles -= 3;
-					m_a[opcode & 3] = do_add(m_a[opcode & 3], read_arg24(m_pc + 2), 0);
-					m_pc += 5;
-					break;
-
-				// sub abs24, dn
-				case 0x68: case 0x69: case 0x6a: case 0x6b:
-					m_cycles -= 3;
-					m_d[opcode & 3] = do_sub(m_d[opcode & 3], read_arg24(m_pc + 2), 0);
-					m_pc += 5;
-					break;
-
-				// sub abs24, an
-				case 0x6c: case 0x6d: case 0x6e: case 0x6f:
-					m_cycles -= 3;
-					m_a[opcode & 3] = do_sub(m_a[opcode & 3], read_arg24(m_pc + 2), 0);
-					m_pc += 5;
-					break;
-
-				// mov imm24, dn
-				case 0x70: case 0x71: case 0x72: case 0x73:
-					m_cycles -= 3;
-					m_d[opcode & 3] = read_arg24(m_pc + 2);
-					m_pc += 5;
-					break;
-
-				// mov imm24, an
-				case 0x74: case 0x75: case 0x76: case 0x77:
-					m_cycles -= 3;
-					m_a[opcode & 3] = read_arg24(m_pc + 2);
-					m_pc += 5;
-					break;
-
-				// cmp abs24, dn
-				case 0x78: case 0x79: case 0x7a: case 0x7b:
-					m_cycles -= 3;
-					do_sub(m_d[opcode & 3], read_arg24(m_pc + 2), 0);
-					m_pc += 5;
-					break;
-
-				// cmp abs24, an
-				case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-					m_cycles -= 3;
-					do_sub(m_a[opcode & 3], read_arg24(m_pc + 2), 0);
-					m_pc += 5;
-					break;
-
-				// mov (abs24, an), dm
-				case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
-				case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
-					m_cycles -= 3;
-					m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				// movbu (abs24, an), dm
-				case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
-				case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
-					m_cycles -= 3;
-					m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				// movb (abs24, an), dm
-				case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
-				case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
-					m_cycles -= 3;
-					m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				// movx (abs24, an), dm
-				case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
-				case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
-					m_cycles -= 4;
-					m_d[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				// mov (abs24), dn
-				case 0xc0: case 0xc1: case 0xc2: case 0xc3:
-					m_cycles -= 3;
-					m_d[opcode & 3] = (INT16)read_mem16(read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				// movb (abs24), dn
-				case 0xc4: case 0xc5: case 0xc6: case 0xc7:
-					m_cycles -= 3;
-					m_d[opcode & 3] = (INT8)read_mem8(read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				// movbu (abs24), dn
-				case 0xc8: case 0xc9: case 0xca: case 0xcb:
-					m_cycles -= 3;
-					m_d[opcode & 3] = read_mem8(read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				// mov (abs24), an
-				case 0xd0: case 0xd1: case 0xd2: case 0xd3:
-					m_cycles -= 4;
-					m_a[opcode & 3] = read_mem24(read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				// jmp imm24
-				case 0xe0:
-					m_cycles -= 4;
-					change_pc(m_pc + 5 + read_arg24(m_pc + 2));
-					break;
-
-				// jsr label24
-				case 0xe1:
-					m_cycles -= 5;
-					do_jsr(m_pc + 5 + read_arg24(m_pc + 2), m_pc + 5);
-					break;
-
-				// mov (abs24, an), am
-				case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
-				case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
-					m_cycles -= 4;
-					m_a[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + read_arg24(m_pc + 2));
-					m_pc += 5;
-					break;
-
-				default:
-					unemul();
-					break;
-			}
-			break;
-
-		// extended code f5 (3 bytes)
-		case 0xf5:
-			opcode = read_arg8(m_pc + 1);
-			switch (opcode)
-			{
-				// and imm8, dn
-				case 0x00: case 0x01: case 0x02: case 0x03:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] &= 0xff0000 | read_arg8(m_pc + 2));
-					m_pc += 3;
-					break;
-
-				// btst imm8, dn
-				case 0x04: case 0x05: case 0x06: case 0x07:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] & read_arg8(m_pc + 2));
-					m_pc += 3;
-					break;
-
-				// or imm8, dn
-				case 0x08: case 0x09: case 0x0a: case 0x0b:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] |= read_arg8(m_pc + 2));
-					m_pc += 3;
-					break;
-
-				// addnf imm8, an
-				case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-					m_cycles -= 2;
-					m_a[opcode & 3] = m_a[opcode & 3] + (INT8)read_arg8(m_pc + 2);
-					m_pc += 3;
-					break;
-
-				// movb dm, (d8, an)
-				case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
-				case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-					m_cycles -= 2;
-					write_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2), m_d[opcode & 3]);
-					m_pc += 3;
-					break;
-
-				// movb (d8, an), dm
-				case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
-				case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
-					m_cycles -= 2;
-					m_d[opcode & 3] = (INT8)read_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2));
-					m_pc += 3;
-					break;
-
-				// movbu (d8, an), dm
-				case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
-				case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
-					m_cycles -= 2;
-					m_d[opcode & 3] = read_mem8(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2));
-					m_pc += 3;
-					break;
-
-				// movx dm, (d8, an)
-				case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
-				case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
-					m_cycles -= 3;
-					write_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2), m_d[opcode & 3]);
-					m_pc += 3;
-					break;
-
-				// movx (d8, an), dm
-				case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
-				case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
-					m_cycles -= 3;
-					m_d[opcode & 3] = read_mem24(m_a[opcode >> 2 & 3] + (INT8)read_arg8(m_pc + 2));
-					m_pc += 3;
-					break;
-
-				// bltx label8
-				case 0xe0:
-					do_branch(2, ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_NX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_VX)); // (VX^NX)=1
-					break;
-
-				// bgtx label8
-				case 0xe1:
-					do_branch(2, ((m_psw & (FLAG_ZX|FLAG_NX|FLAG_VX)) == 0) || ((m_psw & (FLAG_ZX|FLAG_NX|FLAG_VX)) == (FLAG_NX|FLAG_VX))); // ((VX^NX)|ZX)=0
-					break;
-
-				// bgex label8
-				case 0xe2:
-					do_branch(2, ((m_psw & (FLAG_NX|FLAG_VX)) == 0) || ((m_psw & (FLAG_NX|FLAG_VX)) == (FLAG_NX|FLAG_VX))); // (VX^NX)=0
-					break;
-
-				// blex label8
-				case 0xe3:
-					do_branch(2, (m_psw & FLAG_ZX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_NX) || ((m_psw & (FLAG_NX|FLAG_VX)) == FLAG_VX)); // ((VX^NX)|ZX)=1
-					break;
-
-				// bcsx label8
-				case 0xe4:
-					do_branch(2, m_psw & FLAG_CX); // CX=1
-					break;
-
-				// bhix label8
-				case 0xe5:
-					do_branch(2, !(m_psw & (FLAG_ZX|FLAG_CX))); // (CX|ZX)=0
-					break;
-
-				// bccx label8
-				case 0xe6:
-					do_branch(2, !(m_psw & FLAG_CX)); // CX=0
-					break;
-
-				// blsx label8
-				case 0xe7:
-					do_branch(2, m_psw & (FLAG_ZX|FLAG_CX)); // (CX|ZX)=1
-					break;
-
-				// beqx label8
-				case 0xe8:
-					do_branch(2, m_psw & FLAG_ZX); // ZX=1
-					break;
-
-				// bnex label8
-				case 0xe9:
-					do_branch(2, !(m_psw & FLAG_ZX)); // ZX=0
-					break;
-
-				// bnc label8
-				case 0xfe:
-					do_branch(2, !(m_psw & FLAG_NF)); // NF=0
-					break;
-
-				default:
-					unemul();
-					break;
-			}
-			break;
-
-		// nop
-		case 0xf6:
-			m_cycles -= 1;
-			m_pc += 1;
-			break;
-
-		// extended code f7 (4 bytes)
-		case 0xf7:
-			opcode = read_arg8(m_pc + 1);
-			switch (opcode)
-			{
-				// and imm16, dn
-				case 0x00: case 0x01: case 0x02: case 0x03:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] &= 0xff0000 | read_arg16(m_pc + 2));
-					m_pc += 4;
-					break;
-
-				// btst imm16, dn
-				case 0x04: case 0x05: case 0x06: case 0x07:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] & read_arg16(m_pc + 2));
-					m_pc += 4;
-					break;
-
-				// add imm16, an
-				case 0x08: case 0x09: case 0x0a: case 0x0b:
-					m_cycles -= 2;
-					m_a[opcode & 3] = do_add(m_a[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
-					m_pc += 4;
-					break;
-
-				// sub imm16, an
-				case 0x0c: case 0x0d: case 0x0e: case 0x0f:
-					m_cycles -= 2;
-					m_a[opcode & 3] = do_sub(m_a[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
-					m_pc += 4;
-					break;
-
-				// and imm16, psw
-				case 0x10:
-					m_cycles -= 3;
-					m_psw &= read_arg16(m_pc+2);
-					m_pc += 4;
-					break;
-
-				// or imm16, psw
-				case 0x14:
-					m_cycles -= 3;
-					m_psw |= read_arg16(m_pc+2);
-					m_pc += 4;
-					break;
-
-				// add imm16, dn
-				case 0x18: case 0x19: case 0x1a: case 0x1b:
-					m_cycles -= 2;
-					m_d[opcode & 3] = do_add(m_d[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
-					m_pc += 4;
-					break;
-
-				// sub imm16, dn
-				case 0x1c: case 0x1d: case 0x1e: case 0x1f:
-					m_cycles -= 2;
-					m_d[opcode & 3] = do_sub(m_d[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
-					m_pc += 4;
-					break;
-
-				// or imm16, dn
-				case 0x40: case 0x41: case 0x42: case 0x43:
-					m_cycles -= 2;
-					test_nz16(m_d[opcode & 3] |= read_arg16(m_pc + 2));
-					m_pc += 4;
-					break;
-
-				// cmp imm16, dn
-				case 0x48: case 0x49: case 0x4a: case 0x4b:
-					m_cycles -= 2;
-					do_sub(m_d[opcode & 3], (INT16)read_arg16(m_pc + 2), 0);
-					m_pc += 4;
-					break;
-
-				// xor imm16, dn
-				case 0x4c: case 0x4d: case 0x4e: case 0x4f:
-					m_cycles -= 3;
-					test_nz16(m_d[opcode & 3] ^= read_arg16(m_pc + 2));
-					m_pc += 4;
-					break;
-
-				// mov dm, (imm16, an)
-				case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
-				case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
-					m_cycles -= 2;
-					write_mem16(m_a[opcode >> 2 & 3] + (INT16)read_arg16(m_pc + 2), (UINT16)m_d[opcode & 3]);
-					m_pc += 4;
-					break;
-
-				// mov (imm16, an), dm
-				case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
-				case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
-					m_cycles -= 2;
-					m_d[opcode & 3] = (INT16)read_mem16(m_a[opcode >> 2 & 3] + (INT16)read_arg16(m_pc + 2));
-					m_pc += 4;
-					break;
-
-				default:
-					unemul();
-					break;
-			}
-			break;
-
-		// mov imm16, dn
-		case 0xf8: case 0xf9: case 0xfa: case 0xfb:
-			m_cycles -= 1;
-			m_d[opcode & 3] = (INT16)read_arg16(m_pc + 1);
-			m_pc += 3;
-			break;
-
-		// jmp label16
-		case 0xfc:
-			m_cycles -= 2;
-			change_pc(m_pc + 3 + (INT16)read_arg16(m_pc + 1));
-			break;
-
-		// jsr label16
-		case 0xfd:
-			m_cycles -= 4;
-			do_jsr(m_pc + 3 + (INT16)read_arg16(m_pc + 1), m_pc + 3);
-			break;
-
-		// rts
-		case 0xfe:
-			m_cycles -= 5;
-			change_pc(read_mem24(m_a[3]));
-			m_a[3] += 4;
-			break;
-
-		default:
-			unemul();
-			break;
+				m_pc += 2;
+				break;
+
+			// mov imm16, dn
+			case 0xf8: case 0xf9: case 0xfa: case 0xfb:
+				m_d[opcode & 3] = (INT16)read_arg16(m_pc);
+				m_pc += 2;
+				break;
+
+			// jmp label16
+			case 0xfc:
+				m_cycles -= 1;
+				change_pc(m_pc + 2 + (INT16)read_arg16(m_pc));
+				break;
+
+			// jsr label16
+			case 0xfd:
+				m_cycles -= 3;
+				do_jsr(m_pc + 2 + (INT16)read_arg16(m_pc), m_pc + 2);
+				break;
+
+			// rts
+			case 0xfe:
+				m_cycles -= 4;
+				change_pc(read_mem24(m_a[3]));
+				m_a[3] += 4;
+				break;
+
+			default:
+				unemul();
+				break;
 		}
 	}
 }
diff --git a/src/emu/cpu/mn10200/mn10200.h b/src/emu/cpu/mn10200/mn10200.h
index 43e4912f7e1..ec519fc9074 100644
--- a/src/emu/cpu/mn10200/mn10200.h
+++ b/src/emu/cpu/mn10200/mn10200.h
@@ -164,7 +164,7 @@ private:
 	UINT32 do_sub(UINT32 a, UINT32 b, UINT32 c);
 	void test_nz16(UINT16 v);
 	void do_jsr(UINT32 to, UINT32 ret);
-	void do_branch(int offset, bool state);
+	void do_branch(bool state);
 };