srcclean in preparation for release.

This commit is contained in:
Vas Crabb 2025-04-27 02:42:17 +10:00
parent 1ae7456ff6
commit cfc4dde4e9
25 changed files with 148 additions and 148 deletions

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@ -52,8 +52,8 @@ void pc9801_118_device::device_add_mconfig(machine_config &config)
// 5B is near both CS-4232 and this // 5B is near both CS-4232 and this
YM2608(config, m_opn3, XTAL_5B * 2 / 5); YM2608(config, m_opn3, XTAL_5B * 2 / 5);
m_opn3->irq_handler().set([this] (int state) { m_bus->int_w<5>(state); }); m_opn3->irq_handler().set([this] (int state) { m_bus->int_w<5>(state); });
// m_opn3->port_a_read_callback().set(FUNC(pc9801_118_device::opn_porta_r)); // m_opn3->port_a_read_callback().set(FUNC(pc9801_118_device::opn_porta_r));
// m_opn3->port_b_write_callback().set(FUNC(pc9801_118_device::opn_portb_w)); // m_opn3->port_b_write_callback().set(FUNC(pc9801_118_device::opn_portb_w));
m_opn3->add_route(ALL_OUTPUTS, "lspeaker", 1.00); m_opn3->add_route(ALL_OUTPUTS, "lspeaker", 1.00);
m_opn3->add_route(ALL_OUTPUTS, "rspeaker", 1.00); m_opn3->add_route(ALL_OUTPUTS, "rspeaker", 1.00);

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@ -48,7 +48,7 @@ private:
required_device<pc9801_slot_device> m_bus; required_device<pc9801_slot_device> m_bus;
required_device<ym2608_device> m_opn3; required_device<ym2608_device> m_opn3;
// u16 m_io_base, m_joy_sel; // u16 m_io_base, m_joy_sel;
uint8_t m_ext_reg; uint8_t m_ext_reg;
}; };

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@ -17,7 +17,7 @@
Thanks to Franklin Bowen for bug fixes, ideas Thanks to Franklin Bowen for bug fixes, ideas
TODO: TODO:
- KONAMI EXG/TFR isn't disassembled accurately: - KONAMI EXG/TFR isn't disassembled accurately:
0x3E/0x3F + param bit 7 clear = EXG 0x3E/0x3F + param bit 7 clear = EXG
0x3E/0x3F + param bit 7 set = TFR 0x3E/0x3F + param bit 7 set = TFR

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@ -880,7 +880,7 @@ void sh3_base_device::irr0_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{ {
COMBINE_DATA(&m_irr0); COMBINE_DATA(&m_irr0);
logerror("'%s' (%08x): INTC unmapped internal write %02x & %02x (IRR0)\n", tag(), m_sh2_state->pc, data, mem_mask); logerror("'%s' (%08x): INTC unmapped internal write %02x & %02x (IRR0)\n", tag(), m_sh2_state->pc, data, mem_mask);
// not sure if this is how we should clear lines in this core... // not sure if this is how we should clear lines in this core...
if (!(data & 0x01)) execute_set_input(0, CLEAR_LINE); if (!(data & 0x01)) execute_set_input(0, CLEAR_LINE);
if (!(data & 0x02)) execute_set_input(1, CLEAR_LINE); if (!(data & 0x02)) execute_set_input(1, CLEAR_LINE);
if (!(data & 0x04)) execute_set_input(2, CLEAR_LINE); if (!(data & 0x04)) execute_set_input(2, CLEAR_LINE);

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@ -636,12 +636,12 @@ void sh4_base_device::pteh_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{ {
// for use with LDTLB opcode // for use with LDTLB opcode
/* /*
NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
N = VPM = Virtual Page Number N = VPM = Virtual Page Number
A = ASID = Address Space Identifier A = ASID = Address Space Identifier
same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called) same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
*/ */
COMBINE_DATA(&m_pteh); COMBINE_DATA(&m_pteh);
} }
@ -654,9 +654,9 @@ uint32_t sh4_base_device::ptel_r(offs_t offset, uint32_t mem_mask)
void sh4_base_device::ptel_w(offs_t offset, uint32_t data, uint32_t mem_mask) void sh4_base_device::ptel_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{ {
/* /*
---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW ---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
same format as data array 1 of the utlb same format as data array 1 of the utlb
*/ */
COMBINE_DATA(&m_ptel); COMBINE_DATA(&m_ptel);
} }
@ -692,15 +692,15 @@ void sh4_base_device::mmucr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{ {
// MMU Control // MMU Control
/* /*
LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
L = LRUI = Least recently used ITLB L = LRUI = Least recently used ITLB
B = URB = UTLB replace boundary B = URB = UTLB replace boundary
C = URC = UTLB replace counter C = URC = UTLB replace counter
Q = SQMD = Store Queue Mode Bit Q = SQMD = Store Queue Mode Bit
V = SV = Single Virtual Mode Bit V = SV = Single Virtual Mode Bit
T = TI = TLB invalidate T = TI = TLB invalidate
A = AT = Address translation bit (enable) A = AT = Address translation bit (enable)
*/ */
COMBINE_DATA(&m_mmucr); COMBINE_DATA(&m_mmucr);
// MMUCR_AT // MMUCR_AT
@ -823,9 +823,9 @@ uint32_t sh4_base_device::ptea_r(offs_t offset, uint32_t mem_mask)
void sh4_base_device::ptea_w(offs_t offset, uint32_t data, uint32_t mem_mask) void sh4_base_device::ptea_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{ {
/* /*
---- ---- ---- ---- ---- ---- ---- TSSS ---- ---- ---- ---- ---- ---- ---- TSSS
same format as data array 2 of the utlb same format as data array 2 of the utlb
*/ */
COMBINE_DATA(&m_ptea); COMBINE_DATA(&m_ptea);
} }

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@ -906,7 +906,7 @@ void scsp_device::UpdateRegR(int reg)
++m_MidiR; ++m_MidiR;
m_MidiR &= 31; m_MidiR &= 31;
} }
if (m_MidiR == m_MidiW) // if the input FIFO is empty, clear the IRQ if (m_MidiR == m_MidiW) // if the input FIFO is empty, clear the IRQ
{ {
m_irq_cb(m_IrqMidi, CLEAR_LINE); m_irq_cb(m_IrqMidi, CLEAR_LINE);
m_udata.data[0x20 / 2] &= ~8; m_udata.data[0x20 / 2] &= ~8;

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@ -398,11 +398,11 @@ void victor9k_state::ssda_sm_dtr_w(int state)
m_ssda->cts_w(state); m_ssda->cts_w(state);
m_ssda->dcd_w(!state); m_ssda->dcd_w(!state);
/* ___ /* ___
* We're supposed to set the ENC/DEC input of the HC55516 to !state, * We're supposed to set the ENC/DEC input of the HC55516 to !state,
* but only playback/decode is currently supported, and that input * but only playback/decode is currently supported, and that input
* is not implemenented. * is not implemenented.
*/ */
} }

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@ -1471,9 +1471,9 @@ static INPUT_PORTS_START( bfcobra )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Collect") PORT_CODE(KEYCODE_D) PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Collect") PORT_CODE(KEYCODE_D)
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START1 ) PORT_NAME("Start") PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START1 ) PORT_NAME("Start")
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Bonus") PORT_CODE(KEYCODE_F) PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Bonus") PORT_CODE(KEYCODE_F)
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_START("STROBE2") PORT_START("STROBE2")
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("<A") PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("<A")
@ -1574,9 +1574,9 @@ static INPUT_PORTS_START( brainbox2 )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER )
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_START ) PORT_NAME("Start") PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_START ) PORT_NAME("Start")
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON1 )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 )
PORT_START("STROBE2") PORT_START("STROBE2")
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )

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@ -1,12 +1,12 @@
// license:BSD-3-Clause // license:BSD-3-Clause
// copyright-holders:Devin Acker // copyright-holders:Devin Acker
/* /*
Skeleton driver for Casio CPS-2000 piano. Skeleton driver for Casio CPS-2000 piano.
Sound hardware: Sound hardware:
- 2x uPD932 consonant-vowel synth - 2x uPD932 consonant-vowel synth
- uPD934 PCM rhythm - uPD934 PCM rhythm
- monophonic square wave bass w/ RC envelope and filter - monophonic square wave bass w/ RC envelope and filter
*/ */
#include "emu.h" #include "emu.h"

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@ -529,7 +529,7 @@ public:
void system_outputb_w(uint8_t data); void system_outputb_w(uint8_t data);
void system_outputc_w(uint8_t data); void system_outputc_w(uint8_t data);
// handlers for lucky bar MCU ports // handlers for lucky bar MCU ports
uint8_t mcu_portb_r(); uint8_t mcu_portb_r();
void mcu_porta_w(uint8_t data); void mcu_porta_w(uint8_t data);
void mcu_portb_w(uint8_t data); void mcu_portb_w(uint8_t data);
@ -22195,7 +22195,7 @@ void wingco_state::init_wcat3()
as the game needs to be soft resets 4-5 times before as the game needs to be soft resets 4-5 times before
working apparently fine working apparently fine
see from 0xb0 - 0xcf range for an example see from 0xb0 - 0xcf range for an example
(comparable to range 0x96 - 0xb5 in lucky8) (comparable to range 0x96 - 0xb5 in lucky8)
*/ */
uint8_t *rom = memregion("maincpu")->base(); uint8_t *rom = memregion("maincpu")->base();
@ -23716,7 +23716,7 @@ void cmaster_state::init_super7()
{ {
/* possibly incomplete decryption. Game appears to work with clean NVRAM, /* possibly incomplete decryption. Game appears to work with clean NVRAM,
but stops with 'scheda da inizializzare" (PCB to be initialized) but stops with 'scheda da inizializzare" (PCB to be initialized)
message with NVRAM present message with NVRAM present
*/ */
uint8_t *rom = memregion("maincpu")->base(); uint8_t *rom = memregion("maincpu")->base();

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@ -341,7 +341,7 @@ protected:
----FFEEDDCCBBAA---------------- (layer A-F mix codes in forced blending) ----FFEEDDCCBBAA---------------- (layer A-F mix codes in forced blending)
---x---------------------------- (disable shadows) ---x---------------------------- (disable shadows)
--x----------------------------- (disable z-buffering) --x----------------------------- (disable z-buffering)
yy------------------------------ (last encountered tile mix code) yy------------------------------ (last encountered tile mix code)
*/ */
#define GXMIX_BLEND_AUTO 0 // emulate all blend effects #define GXMIX_BLEND_AUTO 0 // emulate all blend effects
#define GXMIX_BLEND_NONE 1 // disable all blend effects #define GXMIX_BLEND_NONE 1 // disable all blend effects

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@ -1499,7 +1499,7 @@ void norautp_state::krampcb4_map(address_map &map)
{ {
map(0x0000, 0x3fff).rom(); map(0x0000, 0x3fff).rom();
map(0xa000, 0xa7ff).ram().share("nvram"); map(0xa000, 0xa7ff).ram().share("nvram");
// map(0xff00, 0xffff).ram(); // map(0xff00, 0xffff).ram();
} }
@ -1957,7 +1957,7 @@ static INPUT_PORTS_START( ddellf97 )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x00, "Bonus 5-Cards (D-UP)" ) PORT_DIPLOCATION("DSW1:6") PORT_DIPNAME( 0x04, 0x00, "Bonus 5-Cards (D-UP)" ) PORT_DIPLOCATION("DSW1:6")
PORT_DIPSETTING( 0x04, DEF_STR( No ) ) PORT_DIPSETTING( 0x04, DEF_STR( No ) )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) ) PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPNAME( 0x08, 0x08, "Raise Bet" ) PORT_DIPLOCATION("DSW1:5") PORT_DIPNAME( 0x08, 0x08, "Raise Bet" ) PORT_DIPLOCATION("DSW1:5")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
@ -2360,8 +2360,8 @@ static INPUT_PORTS_START( tpoker2a )
PORT_INCLUDE( dphl ) PORT_INCLUDE( dphl )
// PORT_MODIFY("IN0") // in case of need ticket/hopper // PORT_MODIFY("IN0") // in case of need ticket/hopper
// PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_READ_LINE_DEVICE_MEMBER("hopper", FUNC(ticket_dispenser_device::line_r)) // PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_READ_LINE_DEVICE_MEMBER("hopper", FUNC(ticket_dispenser_device::line_r))
PORT_MODIFY("DSW1") PORT_MODIFY("DSW1")
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSW1:8") PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSW1:8")

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@ -422,7 +422,7 @@ void paracaidista_state::paracaidista(machine_config &config)
m_dma8257->out_tc_cb().set_inputline(m_maincpu, I8085_RST65_LINE); // under test m_dma8257->out_tc_cb().set_inputline(m_maincpu, I8085_RST65_LINE); // under test
m_dma8257->out_hrq_cb().set(FUNC(paracaidista_state::dmac_hrq_w)); // tied to HALT(HOLD) 8085 line m_dma8257->out_hrq_cb().set(FUNC(paracaidista_state::dmac_hrq_w)); // tied to HALT(HOLD) 8085 line
m_dma8257->in_memr_cb().set(FUNC(paracaidista_state::dmac_mem_r)); // under test m_dma8257->in_memr_cb().set(FUNC(paracaidista_state::dmac_mem_r)); // under test
m_dma8257->out_memw_cb().set(FUNC(paracaidista_state::dmac_mem_w)); // under test m_dma8257->out_memw_cb().set(FUNC(paracaidista_state::dmac_mem_w)); // under test
// video hardware // video hardware
screen_device &screen(SCREEN(config, m_screen, SCREEN_TYPE_RASTER)); screen_device &screen(SCREEN(config, m_screen, SCREEN_TYPE_RASTER));

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@ -1246,7 +1246,7 @@ void pc9801us_state::pc9801us_io(address_map &map)
NAME([this] (offs_t offset) { return m_sdip->read((offset >> 8) + 4); }), NAME([this] (offs_t offset) { return m_sdip->read((offset >> 8) + 4); }),
NAME([this] (offs_t offset, u8 data) { m_sdip->write((offset >> 8) + 4, data); }) NAME([this] (offs_t offset, u8 data) { m_sdip->write((offset >> 8) + 4, data); })
); );
// map(0x8f1f, 0x8f1f).w(m_sdip, FUNC(pc98_sdip_device::bank_w)); // map(0x8f1f, 0x8f1f).w(m_sdip, FUNC(pc98_sdip_device::bank_w));
} }
void pc9801bx_state::pc9801bx2_map(address_map &map) void pc9801bx_state::pc9801bx2_map(address_map &map)
@ -2640,8 +2640,8 @@ void pc9801us_state::pc9801fs(machine_config &config)
pit_clock_config(config, xtal / 4); pit_clock_config(config, xtal / 4);
// PC98_119_KBD(config.replace(), m_keyb, 0); // PC98_119_KBD(config.replace(), m_keyb, 0);
// m_keyb->rxd_callback().set("sio_kbd", FUNC(i8251_device::write_rxd)); // m_keyb->rxd_callback().set("sio_kbd", FUNC(i8251_device::write_rxd));
PC98_SDIP(config, "sdip", 0); PC98_SDIP(config, "sdip", 0);
} }

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@ -1132,9 +1132,9 @@ cfr. https://github.com/angelosa/mame_scratch/blob/main/src/redwood1.cpp
*/ */
//ROM_START( pc9821ne ) //ROM_START( pc9821ne )
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) ) // ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// ROM_LOAD( "bios_ne.rom", 0x18000, 0x18000, BAD_DUMP CRC(2ae070c4) SHA1(d7963942042bfd84ed5fc9b7ba8f1c327c094172) ) // ROM_LOAD( "bios_ne.rom", 0x18000, 0x18000, BAD_DUMP CRC(2ae070c4) SHA1(d7963942042bfd84ed5fc9b7ba8f1c327c094172) )
// ROM_LOAD( "font_ne.rom", 0x00000, 0x46800, BAD_DUMP CRC(fb213757) SHA1(61525826d62fb6e99377b23812faefa291d78c2e) ) // ROM_LOAD( "font_ne.rom", 0x00000, 0x46800, BAD_DUMP CRC(fb213757) SHA1(61525826d62fb6e99377b23812faefa291d78c2e) )
/* /*
98MULTi Ce2 - 80486SX 25 98MULTi Ce2 - 80486SX 25
@ -1340,16 +1340,16 @@ Both bad dumps, requires separate PCI-based driver anyway.
//ROM_START( pc9821v13 ) //ROM_START( pc9821v13 )
// "ROM SUM ERROR" // "ROM SUM ERROR"
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) ) // ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// ROM_LOAD( "bios_v13.rom", 0x18000, 0x18000, BAD_DUMP CRC(0a682b93) SHA1(76a7360502fa0296ea93b4c537174610a834d367) ) // ROM_LOAD( "bios_v13.rom", 0x18000, 0x18000, BAD_DUMP CRC(0a682b93) SHA1(76a7360502fa0296ea93b4c537174610a834d367) )
//ROM_START( pc9821v20 ) //ROM_START( pc9821v20 )
// ROM_REGION16_LE( 0x30000, "ipl", ROMREGION_ERASEFF ) // ROM_REGION16_LE( 0x30000, "ipl", ROMREGION_ERASEFF )
// "ROM SUM ERROR" // "ROM SUM ERROR"
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) ) // ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// Not an ITF ROM // Not an ITF ROM
// ROM_LOAD( "itf_v20.rom", 0x10000, 0x08000, CRC(10e52302) SHA1(f95b8648e3f5a23e507a9fbda8ab2e317d8e5151) ) // ROM_LOAD( "itf_v20.rom", 0x10000, 0x08000, CRC(10e52302) SHA1(f95b8648e3f5a23e507a9fbda8ab2e317d8e5151) )
// ROM_LOAD( "bios_v20.rom", 0x18000, 0x18000, BAD_DUMP CRC(d5d1f13b) SHA1(bf44b5f4e138e036f1b848d6616fbd41b5549764) ) // ROM_LOAD( "bios_v20.rom", 0x18000, 0x18000, BAD_DUMP CRC(d5d1f13b) SHA1(bf44b5f4e138e036f1b848d6616fbd41b5549764) )
/* /*

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@ -177,13 +177,13 @@ public:
//class pc9821_valuestar_state : public pc9821_mate_x_state //class pc9821_valuestar_state : public pc9821_mate_x_state
//{ //{
//public: //public:
// pc9821_valuestar_state(const machine_config &mconfig, device_type type, const char *tag) // pc9821_valuestar_state(const machine_config &mconfig, device_type type, const char *tag)
// : pc9821_mate_x_state(mconfig, type, tag) // : pc9821_mate_x_state(mconfig, type, tag)
// { // {
// } // }
// //
// void pc9821v13(machine_config &config); // void pc9821v13(machine_config &config);
// void pc9821v20(machine_config &config); // void pc9821v20(machine_config &config);
//}; //};
// 9821NOTE // 9821NOTE
@ -193,19 +193,19 @@ public:
//class pc9821_note_state : public pc9821_state //class pc9821_note_state : public pc9821_state
//{ //{
//public: //public:
// pc9821_note_state(const machine_config &mconfig, device_type type, const char *tag) // pc9821_note_state(const machine_config &mconfig, device_type type, const char *tag)
// : pc9821_state(mconfig, type, tag) // : pc9821_state(mconfig, type, tag)
// , m_pmc(*this, "pmc") // , m_pmc(*this, "pmc")
// { // {
// } // }
// //
// void pc9821ne(machine_config &config); // void pc9821ne(machine_config &config);
// //
//protected: //protected:
// void pc9821ne_io(address_map &map) ATTR_COLD; // void pc9821ne_io(address_map &map) ATTR_COLD;
// //
//private: //private:
// required_device<redwood1_device> m_pmc; // required_device<redwood1_device> m_pmc;
//}; //};
class pc9821_note_lavie_state : public pc9821_state class pc9821_note_lavie_state : public pc9821_state

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@ -421,7 +421,7 @@ void pc98_119_kbd_device::key_repeat(uint8_t row, uint8_t column)
m_repeat_state[code] ^= 1; m_repeat_state[code] ^= 1;
code |= m_repeat_state[code] << 7; code |= m_repeat_state[code] << 7;
send_key(code); send_key(code);
} }
void pc98_119_kbd_device::received_byte(u8 byte) void pc98_119_kbd_device::received_byte(u8 byte)

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@ -10,7 +10,7 @@
class pc98_memsw_device : public device_t, class pc98_memsw_device : public device_t,
public device_nvram_interface public device_nvram_interface
{ {
public: public:
pc98_memsw_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); pc98_memsw_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

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@ -10,7 +10,7 @@
class pc98_sdip_device : public device_t, class pc98_sdip_device : public device_t,
public device_nvram_interface public device_nvram_interface
{ {
public: public:
pc98_sdip_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); pc98_sdip_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

View File

@ -768,7 +768,7 @@ struct model2_state::triangle
u8 luma = 0; u8 luma = 0;
int16_t viewport[4] = { 0, 0, 0, 0 }; int16_t viewport[4] = { 0, 0, 0, 0 };
int16_t center[2] = { 0, 0 }; int16_t center[2] = { 0, 0 };
u8 window = 0; u8 window = 0;
}; };
struct model2_state::quad_m2 struct model2_state::quad_m2
@ -823,8 +823,8 @@ struct model2_state::raster_state
u16 max_z = 0; // Maximum sortable Z value u16 max_z = 0; // Maximum sortable Z value
u16 texture_ram[0x10000]; // Texture RAM pointer u16 texture_ram[0x10000]; // Texture RAM pointer
u8 log_ram[0x40000]; // Log RAM pointer u8 log_ram[0x40000]; // Log RAM pointer
u8 cur_window = 0; // Current window u8 cur_window = 0; // Current window
plane clip_plane[4][4]; // Polygon clipping planes plane clip_plane[4][4]; // Polygon clipping planes
}; };
/******************************************* /*******************************************