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mirror of https://github.com/holub/mame synced 2025-05-19 20:29:09 +03:00
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srcclean in preparation for release.

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This commit is contained in:
Vas Crabb 2025-04-27 02:42:17 +10:00
parent 1ae7456ff6
commit cfc4dde4e9
25 changed files with 148 additions and 148 deletions
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2
hash/tvgogo.xml
View File

@ -14,7 +14,7 @@ _(EU)__|__(US)__|____________|_____________________________________
| Y | Dodgeball |Motion controller
| Y | Baseball |Baseball Bat shaped motion controller
Y | | Paintball |Gun controller
Y | | Snowboarding |Snowboard-shaped motion controller
Y | | Snowboarding |Snowboard-shaped motion controller
| | Skateboard |Skateboard-shaped motion controller

4
src/devices/bus/cbus/pc9801_118.cpp
View File

@ -52,8 +52,8 @@ void pc9801_118_device::device_add_mconfig(machine_config &config)
// 5B is near both CS-4232 and this
YM2608(config, m_opn3, XTAL_5B * 2 / 5);
m_opn3->irq_handler().set([this] (int state) { m_bus->int_w<5>(state); });
// m_opn3->port_a_read_callback().set(FUNC(pc9801_118_device::opn_porta_r));
// m_opn3->port_b_write_callback().set(FUNC(pc9801_118_device::opn_portb_w));
// m_opn3->port_a_read_callback().set(FUNC(pc9801_118_device::opn_porta_r));
// m_opn3->port_b_write_callback().set(FUNC(pc9801_118_device::opn_portb_w));
m_opn3->add_route(ALL_OUTPUTS, "lspeaker", 1.00);
m_opn3->add_route(ALL_OUTPUTS, "rspeaker", 1.00);

2
src/devices/bus/cbus/pc9801_118.h
View File

@ -48,7 +48,7 @@ private:
required_device<pc9801_slot_device> m_bus;
required_device<ym2608_device> m_opn3;
// u16 m_io_base, m_joy_sel;
// u16 m_io_base, m_joy_sel;
uint8_t m_ext_reg;
};

2
src/devices/cpu/m6809/6x09dasm.cpp
View File

@ -17,7 +17,7 @@
Thanks to Franklin Bowen for bug fixes, ideas
TODO:
- KONAMI EXG/TFR isn't disassembled accurately:
- KONAMI EXG/TFR isn't disassembled accurately:
0x3E/0x3F + param bit 7 clear = EXG
0x3E/0x3F + param bit 7 set = TFR

2
src/devices/cpu/sh/sh3comn.cpp
View File

@ -880,7 +880,7 @@ void sh3_base_device::irr0_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
COMBINE_DATA(&m_irr0);
logerror("'%s' (%08x): INTC unmapped internal write %02x & %02x (IRR0)\n", tag(), m_sh2_state->pc, data, mem_mask);
// not sure if this is how we should clear lines in this core...
// not sure if this is how we should clear lines in this core...
if (!(data & 0x01)) execute_set_input(0, CLEAR_LINE);
if (!(data & 0x02)) execute_set_input(1, CLEAR_LINE);
if (!(data & 0x04)) execute_set_input(2, CLEAR_LINE);

32
src/devices/cpu/sh/sh4comn.cpp
View File

@ -636,12 +636,12 @@ void sh4_base_device::pteh_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// for use with LDTLB opcode
/*
NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
N = VPM = Virtual Page Number
A = ASID = Address Space Identifier
N = VPM = Virtual Page Number
A = ASID = Address Space Identifier
same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
*/
COMBINE_DATA(&m_pteh);
}
@ -654,9 +654,9 @@ uint32_t sh4_base_device::ptel_r(offs_t offset, uint32_t mem_mask)
void sh4_base_device::ptel_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
/*
---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
same format as data array 1 of the utlb
same format as data array 1 of the utlb
*/
COMBINE_DATA(&m_ptel);
}
@ -692,15 +692,15 @@ void sh4_base_device::mmucr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// MMU Control
/*
LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
L = LRUI = Least recently used ITLB
B = URB = UTLB replace boundary
C = URC = UTLB replace counter
Q = SQMD = Store Queue Mode Bit
V = SV = Single Virtual Mode Bit
T = TI = TLB invalidate
A = AT = Address translation bit (enable)
L = LRUI = Least recently used ITLB
B = URB = UTLB replace boundary
C = URC = UTLB replace counter
Q = SQMD = Store Queue Mode Bit
V = SV = Single Virtual Mode Bit
T = TI = TLB invalidate
A = AT = Address translation bit (enable)
*/
COMBINE_DATA(&m_mmucr);
// MMUCR_AT
@ -823,9 +823,9 @@ uint32_t sh4_base_device::ptea_r(offs_t offset, uint32_t mem_mask)
void sh4_base_device::ptea_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
/*
---- ---- ---- ---- ---- ---- ---- TSSS
---- ---- ---- ---- ---- ---- ---- TSSS
same format as data array 2 of the utlb
same format as data array 2 of the utlb
*/
COMBINE_DATA(&m_ptea);
}

2
src/devices/cpu/uml.cpp
View File

@ -332,7 +332,7 @@ public:
static void truncate_imm(instruction &inst)
{
u64 const mask = size_mask(inst);
for (int i = 0; inst.numparams() > i; ++i)
truncate_immediate(inst, i, mask);
}

2
src/devices/sound/scsp.cpp
View File

@ -906,7 +906,7 @@ void scsp_device::UpdateRegR(int reg)
++m_MidiR;
m_MidiR &= 31;
}
if (m_MidiR == m_MidiW) // if the input FIFO is empty, clear the IRQ
if (m_MidiR == m_MidiW) // if the input FIFO is empty, clear the IRQ
{
m_irq_cb(m_IrqMidi, CLEAR_LINE);
m_udata.data[0x20 / 2] &= ~8;

4
src/devices/video/ppu2c0x.h
View File

@ -149,7 +149,7 @@ protected:
// device_config_memory_interface overrides
virtual space_config_vector memory_space_config() const override;
virtual u32 palette_entries() const noexcept override { return 0x40 * 8; }
virtual u32 palette_entries() const noexcept override { return 0x40 * 8; }
TIMER_CALLBACK_MEMBER(hblank_tick);
TIMER_CALLBACK_MEMBER(nmi_tick);
@ -309,7 +309,7 @@ public:
protected:
virtual void device_start() override ATTR_COLD;
virtual u32 palette_entries() const noexcept override { return 0x40 * 2; }
virtual u32 palette_entries() const noexcept override { return 0x40 * 2; }
virtual void draw_background(u8 *line_priority) override;
virtual void draw_sprite_pixel(int sprite_xpos, int color, int pixel, u8 pixel_data, bitmap_rgb32 &bitmap) override;

2
src/devices/video/ppu2c0x_vt.h
View File

@ -53,7 +53,7 @@ protected:
virtual void device_start() override ATTR_COLD;
virtual void device_reset() override ATTR_COLD;
virtual u32 palette_entries() const noexcept override { return (0x40 * 8) + (0x1000 * 8); }
virtual u32 palette_entries() const noexcept override { return (0x40 * 8) + (0x1000 * 8); }
virtual void read_tile_plane_data(int address, int color) override;
virtual void shift_tile_plane_data(uint8_t &pix) override;

10
src/mame/act/victor9k.cpp
View File

@ -398,11 +398,11 @@ void victor9k_state::ssda_sm_dtr_w(int state)
m_ssda->cts_w(state);
m_ssda->dcd_w(!state);
/* ___
* We're supposed to set the ENC/DEC input of the HC55516 to !state,
* but only playback/decode is currently supported, and that input
* is not implemenented.
*/
/* ___
* We're supposed to set the ENC/DEC input of the HC55516 to !state,
* but only playback/decode is currently supported, and that input
* is not implemenented.
*/
}

6
src/mame/amstrad/amstrad_m.cpp
View File

@ -2760,11 +2760,11 @@ IRQ_CALLBACK_MEMBER(amstrad_state::amstrad_cpu_acknowledge_int)
{
static uint8_t prev_x,prev_y;
uint8_t data_x, data_y;
m_amx_mouse_data = 0x0f;
data_x = m_io_mouse[0].read_safe(0);
data_y = m_io_mouse[1].read_safe(0);
if(data_x > prev_x)
m_amx_mouse_data &= ~0x08;
if(data_x < prev_x)
@ -2776,7 +2776,7 @@ IRQ_CALLBACK_MEMBER(amstrad_state::amstrad_cpu_acknowledge_int)
m_amx_mouse_data |= (m_io_mouse[2].read_safe(0) << 4);
prev_x = data_x;
prev_y = data_y;
m_amx_mouse_data |= (m_io_kbrow[9].read_safe(0) & 0x80); // DEL key
}
}

14
src/mame/bfm/bfcobra.cpp
View File

@ -1471,9 +1471,9 @@ static INPUT_PORTS_START( bfcobra )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Collect") PORT_CODE(KEYCODE_D)
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START1 ) PORT_NAME("Start")
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Bonus") PORT_CODE(KEYCODE_F)
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_START("STROBE2")
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("<A")
@ -1574,9 +1574,9 @@ static INPUT_PORTS_START( brainbox2 )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER )
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_START ) PORT_NAME("Start")
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON1 )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON1 )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 )
PORT_START("STROBE2")
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
@ -1782,7 +1782,7 @@ void bfcobra_state::bfcobra(machine_config &config)
MC6809(config, m_audiocpu, M6809_XTAL); // MC6809P
m_audiocpu->set_addrmap(AS_PROGRAM, &bfcobra_state::m6809_prog_map);
m_audiocpu->set_periodic_int(FUNC(bfcobra_state::timer_irq), attotime::from_hz(1000));
WATCHDOG_TIMER(config, "watchdog").set_time(PERIOD_OF_555_MONOSTABLE(120000,100e-9));
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);

12
src/mame/casio/cps2000.cpp
View File

@ -1,12 +1,12 @@
// license:BSD-3-Clause
// copyright-holders:Devin Acker
/*
Skeleton driver for Casio CPS-2000 piano.
Skeleton driver for Casio CPS-2000 piano.
Sound hardware:
- 2x uPD932 consonant-vowel synth
- uPD934 PCM rhythm
- monophonic square wave bass w/ RC envelope and filter
Sound hardware:
- 2x uPD932 consonant-vowel synth
- uPD934 PCM rhythm
- monophonic square wave bass w/ RC envelope and filter
*/
#include "emu.h"
@ -55,7 +55,7 @@ private:
required_device<msm6200_device> m_kbd;
required_device<va_rc_eg_device> m_bass_env;
required_device<upd934g_device> m_pcm;
required_ioport_array<5> m_keys;
ioport_value m_key_sel;

48
src/mame/igs/goldstar.cpp
View File

@ -529,7 +529,7 @@ public:
void system_outputb_w(uint8_t data);
void system_outputc_w(uint8_t data);
// handlers for lucky bar MCU ports
// handlers for lucky bar MCU ports
uint8_t mcu_portb_r();
void mcu_porta_w(uint8_t data);
void mcu_portb_w(uint8_t data);
@ -584,7 +584,7 @@ public:
protected:
TILE_GET_INFO_MEMBER(get_magical_fg_tile_info);
//virtual void machine_start() override { goldstar_state::machine_start(); m_tile_bank = 0; }
virtual void machine_start() override;
virtual void machine_start() override;
private:
optional_device<ds2401_device> m_fl7w4_id;
@ -598,7 +598,7 @@ private:
void lucky8p_map(address_map &map) ATTR_COLD;
void nd8lines_map(address_map &map) ATTR_COLD;
void magodds_map(address_map &map) ATTR_COLD;
void luckybar_map(address_map &map) ATTR_COLD;
void luckybar_map(address_map &map) ATTR_COLD;
};
@ -1614,10 +1614,10 @@ void wingco_state::mcu_portc_w(uint8_t data)
uint8_t wingco_state::nvram_r(offs_t offset)
{
uint8_t ret = m_nvram8[offset];
if(offset == 0x7ff)
if(offset == 0x7ff)
ret = 0;
if(offset == 0x7fd)
{
switch(m_nvram8[0x7fd])
@ -1626,9 +1626,9 @@ uint8_t wingco_state::nvram_r(offs_t offset)
case 0x04: ret = 0x02; break;
case 0x10: ret = 0x20; break;
case 0x40: ret = 0x80; break;
}
}
}
return ret;
}
@ -11838,7 +11838,7 @@ ROM_START( crazybon )
ROM_REGION( 0x10000, "user1", ROMREGION_ERASE00 )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) BAD_DUMP )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) BAD_DUMP )
@ -11859,7 +11859,7 @@ ROM_START( crazybona )
ROM_REGION( 0x10000, "user1", ROMREGION_ERASE00 )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) BAD_DUMP )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) BAD_DUMP )
@ -11880,7 +11880,7 @@ ROM_START( crazybonb )
ROM_REGION( 0x10000, "user1", ROMREGION_ERASE00 )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) BAD_DUMP )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) BAD_DUMP )
@ -12412,7 +12412,7 @@ ROM_END
/*
Original Wing W4 PCB + Dyna D9005 subboard with Z80,
ROM, RAM and Dyna DP 1200-5 custom.
GFX ROMs are identical to many other sets.
*/
@ -13062,7 +13062,7 @@ ROM_START( cmasterb )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "u53.8", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -13097,7 +13097,7 @@ ROM_START( cmezspin )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "u53.8", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -13201,7 +13201,7 @@ ROM_START( cmasterc )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "msii841.u53", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -13313,7 +13313,7 @@ ROM_START( cmasterd )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "u53.8", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -13348,7 +13348,7 @@ ROM_START( cmastere )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "u53.8", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -13383,7 +13383,7 @@ ROM_START( cmasterf )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "u53.8", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -20705,7 +20705,7 @@ ROM_START( cmpacman )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "8.u53", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -20732,7 +20732,7 @@ ROM_START( cmpacmana )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "8.u53", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -20809,7 +20809,7 @@ ROM_START( cmtetris )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "8.u53", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -20958,7 +20958,7 @@ ROM_START( cmtetrisb )
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "rom8.u53", 0x0000, 0x10000, CRC(e92443d3) SHA1(4b6ca4521841610054165f085ae05510e77af191) )
// proms taken from cmv4, probably wrong
// proms taken from cmv4, probably wrong
ROM_REGION( 0x200, "proms", 0 )
ROM_LOAD( "82s129.u84", 0x0000, 0x0100, CRC(0489b760) SHA1(78f8632b17a76335183c5c204cdec856988368b0) )
ROM_LOAD( "82s129.u79", 0x0100, 0x0100, CRC(21eb5b19) SHA1(9b8425bdb97f11f4855c998c7792c3291fd07470) )
@ -22195,7 +22195,7 @@ void wingco_state::init_wcat3()
as the game needs to be soft resets 4-5 times before
working apparently fine
see from 0xb0 - 0xcf range for an example
see from 0xb0 - 0xcf range for an example
(comparable to range 0x96 - 0xb5 in lucky8)
*/
uint8_t *rom = memregion("maincpu")->base();
@ -23716,7 +23716,7 @@ void cmaster_state::init_super7()
{
/* possibly incomplete decryption. Game appears to work with clean NVRAM,
but stops with 'scheda da inizializzare" (PCB to be initialized)
message with NVRAM present
message with NVRAM present
*/
uint8_t *rom = memregion("maincpu")->base();

2
src/mame/konami/konamigx.h
View File

@ -341,7 +341,7 @@ protected:
----FFEEDDCCBBAA---------------- (layer A-F mix codes in forced blending)
---x---------------------------- (disable shadows)
--x----------------------------- (disable z-buffering)
yy------------------------------ (last encountered tile mix code)
yy------------------------------ (last encountered tile mix code)
*/
#define GXMIX_BLEND_AUTO 0 // emulate all blend effects
#define GXMIX_BLEND_NONE 1 // disable all blend effects

78
src/mame/misc/norautp.cpp
View File

@ -396,7 +396,7 @@
6 Bet setting see below Bet setting
MAX BET
Switch 4 Switch 6
Switch 4 Switch 6
on on =max bet 25 (5- 8 setting)
off on =max bet 20 (1- 8 setting)
on off =max bet 15
@ -907,7 +907,7 @@ private:
uint8_t nvram_r(offs_t offset);
void nvram_w(offs_t offset, uint8_t data);
void nvunlock_w(offs_t offset, uint8_t data);
std::unique_ptr<uint16_t[]> m_np_vram;
required_device<cpu_device> m_maincpu;
required_device<nvram_device> m_nvram;
@ -921,7 +921,7 @@ private:
output_finder<12> m_lamps;
std::unique_ptr<uint8_t[]> m_nvram8;
bool m_display_line_control = false;
bool m_nvunlock = false;
uint8_t m_videoram[0x800] = {};
@ -1499,7 +1499,7 @@ void norautp_state::krampcb4_map(address_map &map)
{
map(0x0000, 0x3fff).rom();
map(0xa000, 0xa7ff).ram().share("nvram");
// map(0xff00, 0xffff).ram();
// map(0xff00, 0xffff).ram();
}
@ -1957,7 +1957,7 @@ static INPUT_PORTS_START( ddellf97 )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x00, "Bonus 5-Cards (D-UP)" ) PORT_DIPLOCATION("DSW1:6")
PORT_DIPSETTING( 0x04, DEF_STR( No ) )
PORT_DIPSETTING( 0x04, DEF_STR( No ) )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPNAME( 0x08, 0x08, "Raise Bet" ) PORT_DIPLOCATION("DSW1:5")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
@ -2062,7 +2062,7 @@ static INPUT_PORTS_START( delv18ap )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:4")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
@ -2360,8 +2360,8 @@ static INPUT_PORTS_START( tpoker2a )
PORT_INCLUDE( dphl )
// PORT_MODIFY("IN0") // in case of need ticket/hopper
// PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_READ_LINE_DEVICE_MEMBER("hopper", FUNC(ticket_dispenser_device::line_r))
// PORT_MODIFY("IN0") // in case of need ticket/hopper
// PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_READ_LINE_DEVICE_MEMBER("hopper", FUNC(ticket_dispenser_device::line_r))
PORT_MODIFY("DSW1")
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSW1:8")
@ -3928,7 +3928,7 @@ ROM_START( kimblz80 )
ROM_LOAD( "quiz_char_ii.bin", 0x0800, 0x0800, CRC(ad645a41) SHA1(a2c47f21609cda20a6cfee17a7bfd32fb2afd6fe) )
ROM_END
// Hi Lo Kimble, Z80
// Hi Lo Kimble, Z80
ROM_START( hilokimb )
ROM_REGION( 0x10000, "maincpu", 0 ) // not encrypted. extended addressing.
ROM_LOAD( "wolfie02_u11_2764.u11", 0x0000, 0x2000, CRC(ec26e205) SHA1(a778365a22c83d285c0896bab62bc04a718a5324) )
@ -4220,9 +4220,9 @@ ROM_END
Dellfern UK LTD
MADE IN ENGLAND (C)1997
Rom: VERSION 18, 16.05.97 BY V.S
- CPU: 1x Z84C0006PEC
- RAM: 1x 6264A 8K X 8 - Bit CMOS SRAM
- RAM: 1x GM76C28A - 2048 x 8 bit CMOS Static RAM
@ -4233,7 +4233,7 @@ ROM_END
- Crystal: 1x 18.432 MHz
- PLDs: 1x PALCE16V8H read protected
Pack of six programs inside for different cabs types.
Pack of six programs inside for different cabs types.
Program offsets:
@ -5372,7 +5372,7 @@ ROM_END
- RAM: 2x 2111A-2: Static Random Access Memory 256 x 4 bit.
- RAM: 1X 6116-3
- I/O: 3x 8255: Peripeheral Interface Adapter.
- Prg ROMs: 2x 2732: U12,U18: Eprom.
- Prg ROMs: 2x 2732: U12,U18: Eprom.
- Gfx ROMs: 1x 2732: U31: Eprom.
- Sound: Discrete.
- Crystal: 1x 18.000 MHz.
@ -5381,7 +5381,7 @@ ROM_END
PCB/EPROM MARKINGS = NONE
U51 LABEL:98CC
PCB Layout (PCB2): Edge Connector 36x2
.------------------------------------------------------------------------------------------------------------.
@ -5456,7 +5456,7 @@ ROM_END
- CPU: 1x 8080
- RAM: 2x 2111A-2: Static Random Access Memory 256 x 4 bit.
- I/O: 3x 8255: Peripeheral Interface Adapter.
- Prg ROMs: 2x 2732: U12,U18: Eprom.
- Prg ROMs: 2x 2732: U12,U18: Eprom.
- Gfx ROMs: 1x 2716: U31: Eprom.
- Sound: Discrete.
- Crystal: 1x 18.000 MHz.
@ -5467,20 +5467,20 @@ ROM_END
1x CD4093
1x 3.6V NI-CD
1x CD4040
2x NEC D5101LC-1: 256x4 static CMOS RAM.
2x NEC D5101LC-1: 256x4 static CMOS RAM.
PCB MARKINGS Silkscreened: NONE
PCB MARKED:5239
PCB MARKED:8310
PCB MARKED:8310
EPROM MARKINGS:
U12: U12 ANTI STAT CB0A
U18: U18 ANTI STAT 36E3
U31: U31 CGIT F506
U51: 98CE
PCB Layout (PCB5): Edge Connector 36x2
.------------------------------------------------------------------------------------------------------------.
|PIN'S BATTERY PCB .---------. .---------. .-----. ......... .---------. |
@ -5606,7 +5606,7 @@ ROM_END
- CPU: 1x 8080
- RAM: 3x 2111A-2: Static Random Access Memory 256 x 4 bit.
- I/O: 3x 8255: Peripeheral Interface Adapter.
- Prg ROMs: 2x 2764: U12, U18: Eprom.
- Prg ROMs: 2x 2764: U12, U18: Eprom.
- Gfx ROMs: 1x 2732: U31: Eprom.
- Sound: Discrete.
- Crystal: 1x 18.144 MHz.
@ -5619,12 +5619,12 @@ ROM_END
R.A.B.
W.S.B.
DECMO 3084
STICKERED: DEC 14'84
STICKERED: DEC 17'84
STICKERED: TESTED OK W.S.B 6998
PCB MARKED:6998
STICKERED: DEC 17'84
STICKERED: TESTED OK W.S.B 6998
PCB MARKED:6998
EPROM MARKINGS:
U12: 6000 U12 5-25
U18: 6000 U18
@ -5650,7 +5650,7 @@ ROM_END
- CPU: 1x 8080
- RAM: 3x 2111A-2: Static Random Access Memory 256 x 4 bit.
- I/O: 3x 8255: Peripeheral Interface Adapter.
- Prg ROMs: 2x 2764: U12, U18: Eprom.
- Prg ROMs: 2x 2764: U12, U18: Eprom.
- Gfx ROMs: 1x 2732: U31: Eprom.
- Sound: Discrete.
- Crystal: 1x 18.144 MHz.
@ -5658,15 +5658,15 @@ ROM_END
- BATTERY ADDON PCB:ENCASED IN RESIN
LABELED:14690 MODEL 4036 BATTERY BOARD
PCB MARKINGS Silkscreened = PATENT PENDING. COPYRIGHT 1983 M.KRAMER MFG.INC. MODEL 3000 M.KRAMER INC
R.A.B.
W.S.B.
STICKERED: TEST 1 JUN 12'84
STICKERED: TEST 3 JUN 5 '84
PCB MARKED:5253
STICKERED: TEST 3 JUN 5 '84
PCB MARKED:5253
EPROM MARKINGS:
U12: JPB M8 USA U12 5/25
U18: JPB U18 USA M8 5/25
@ -5692,7 +5692,7 @@ ROM_END
- CPU: 1x 8080
- RAM: 3x 2111A-2: Static Random Access Memory 256 x 4 bit.
- I/O: 3x 8255: Peripeheral Interface Adapter.
- Prg ROMs: 2x 2764: U12, U18: Eprom.
- Prg ROMs: 2x 2764: U12, U18: Eprom.
- Gfx ROMs: 1x 2732: U31: Eprom.
- Sound: Discrete.
- Crystal: 1x 18.144 MHz.
@ -5700,23 +5700,23 @@ ROM_END
- BATTERY ADDON PCB: ENCASED IN RESIN
LABELED: MODEL 16304 4000 BATTERY BOARD
PCB MARKINGS Silkscreened = PATENT PENDING. COPYRIGHT 1983 M.KRAMER MFG.INC. MODEL 3000 M.KRAMER INC
R.A.B.
W.S.B.
DECMO 3384
STICKERED: TEST 5 NOV 31 '84
STICKERED: TEST 3 NOV 27 '84
STICKERED: TEST 3 NOV 27 '84
STICKERED: K TESTED OK W.S.B 6759 NOV 27 84
PCB MARKED:6759
PCB MARKED:6759
EPROM MARKINGS:
U12: U12 JF30 TN 5 25 6200-1F06
U18: U18 JF30 MODEL 6000 5E4F--33CB
U31: U31B MOD3000 CF7B
U51: U51-06EC
*/
ROM_START( krampcb6 )
ROM_REGION( 0x10000, "maincpu", 0 )
@ -6572,4 +6572,4 @@ GAMEL( 1990, tpoker2b, tpoker2, tpoker2, tpoker2a, norautp_state, empty_ini
//* The following ones are still unknown. No info about name, CPU, manufacturer, or HW *
//**************************************************************************************
// YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS LAYOUT
// YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS LAYOUT

8
src/mame/misc/paracaidista.cpp
View File

@ -153,7 +153,7 @@ private:
output_finder<2> m_lamps;
// logic gates
u8 m_sndvol = 0;
u8 m_sndvol = 0;
u8 m_inputsel = 0;
u8 m_inputasel = 0;
};
@ -172,7 +172,7 @@ uint32_t paracaidista_state::screen_update(screen_device &screen, bitmap_ind16 &
for (int x = cliprect.left() / 8; x <= (cliprect.right() / 8); x++)
{
const u8 pixel_data = src[x];
// unpack 8 pixels from the byte
for (int bit = 0; bit < 8; bit++)
dst[(x << 3) | bit] = BIT(pixel_data, bit ^ 7);
@ -420,9 +420,9 @@ void paracaidista_state::paracaidista(machine_config &config)
I8257(config, m_dma8257, 6'553'600 / 2);
m_dma8257->out_tc_cb().set_inputline(m_maincpu, I8085_RST65_LINE); // under test
m_dma8257->out_hrq_cb().set(FUNC(paracaidista_state::dmac_hrq_w)); // tied to HALT(HOLD) 8085 line
m_dma8257->out_hrq_cb().set(FUNC(paracaidista_state::dmac_hrq_w)); // tied to HALT(HOLD) 8085 line
m_dma8257->in_memr_cb().set(FUNC(paracaidista_state::dmac_mem_r)); // under test
m_dma8257->out_memw_cb().set(FUNC(paracaidista_state::dmac_mem_w)); // under test
m_dma8257->out_memw_cb().set(FUNC(paracaidista_state::dmac_mem_w)); // under test
// video hardware
screen_device &screen(SCREEN(config, m_screen, SCREEN_TYPE_RASTER));

6
src/mame/nec/pc9801.cpp
View File

@ -1246,7 +1246,7 @@ void pc9801us_state::pc9801us_io(address_map &map)
NAME([this] (offs_t offset) { return m_sdip->read((offset >> 8) + 4); }),
NAME([this] (offs_t offset, u8 data) { m_sdip->write((offset >> 8) + 4, data); })
);
// map(0x8f1f, 0x8f1f).w(m_sdip, FUNC(pc98_sdip_device::bank_w));
// map(0x8f1f, 0x8f1f).w(m_sdip, FUNC(pc98_sdip_device::bank_w));
}
void pc9801bx_state::pc9801bx2_map(address_map &map)
@ -2640,8 +2640,8 @@ void pc9801us_state::pc9801fs(machine_config &config)
pit_clock_config(config, xtal / 4);
// PC98_119_KBD(config.replace(), m_keyb, 0);
// m_keyb->rxd_callback().set("sio_kbd", FUNC(i8251_device::write_rxd));
// PC98_119_KBD(config.replace(), m_keyb, 0);
// m_keyb->rxd_callback().set("sio_kbd", FUNC(i8251_device::write_rxd));
PC98_SDIP(config, "sdip", 0);
}

18
src/mame/nec/pc9821.cpp
View File

@ -1132,9 +1132,9 @@ cfr. https://github.com/angelosa/mame_scratch/blob/main/src/redwood1.cpp
*/
//ROM_START( pc9821ne )
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// ROM_LOAD( "bios_ne.rom", 0x18000, 0x18000, BAD_DUMP CRC(2ae070c4) SHA1(d7963942042bfd84ed5fc9b7ba8f1c327c094172) )
// ROM_LOAD( "font_ne.rom", 0x00000, 0x46800, BAD_DUMP CRC(fb213757) SHA1(61525826d62fb6e99377b23812faefa291d78c2e) )
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// ROM_LOAD( "bios_ne.rom", 0x18000, 0x18000, BAD_DUMP CRC(2ae070c4) SHA1(d7963942042bfd84ed5fc9b7ba8f1c327c094172) )
// ROM_LOAD( "font_ne.rom", 0x00000, 0x46800, BAD_DUMP CRC(fb213757) SHA1(61525826d62fb6e99377b23812faefa291d78c2e) )
/*
98MULTi Ce2 - 80486SX 25
@ -1340,16 +1340,16 @@ Both bad dumps, requires separate PCI-based driver anyway.
//ROM_START( pc9821v13 )
// "ROM SUM ERROR"
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// ROM_LOAD( "bios_v13.rom", 0x18000, 0x18000, BAD_DUMP CRC(0a682b93) SHA1(76a7360502fa0296ea93b4c537174610a834d367) )
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// ROM_LOAD( "bios_v13.rom", 0x18000, 0x18000, BAD_DUMP CRC(0a682b93) SHA1(76a7360502fa0296ea93b4c537174610a834d367) )
//ROM_START( pc9821v20 )
// ROM_REGION16_LE( 0x30000, "ipl", ROMREGION_ERASEFF )
// "ROM SUM ERROR"
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// ROM_REGION16_LE( 0x30000, "ipl", ROMREGION_ERASEFF )
// "ROM SUM ERROR"
// ROM_LOAD( "itf.rom", 0x10000, 0x08000, BAD_DUMP CRC(dd4c7bb8) SHA1(cf3aa193df2722899066246bccbed03f2e79a74a) )
// Not an ITF ROM
// ROM_LOAD( "itf_v20.rom", 0x10000, 0x08000, CRC(10e52302) SHA1(f95b8648e3f5a23e507a9fbda8ab2e317d8e5151) )
// ROM_LOAD( "bios_v20.rom", 0x18000, 0x18000, BAD_DUMP CRC(d5d1f13b) SHA1(bf44b5f4e138e036f1b848d6616fbd41b5549764) )
// ROM_LOAD( "bios_v20.rom", 0x18000, 0x18000, BAD_DUMP CRC(d5d1f13b) SHA1(bf44b5f4e138e036f1b848d6616fbd41b5549764) )
/*

28
src/mame/nec/pc9821.h
View File

@ -177,13 +177,13 @@ public:
//class pc9821_valuestar_state : public pc9821_mate_x_state
//{
//public:
// pc9821_valuestar_state(const machine_config &mconfig, device_type type, const char *tag)
// : pc9821_mate_x_state(mconfig, type, tag)
// {
// }
// pc9821_valuestar_state(const machine_config &mconfig, device_type type, const char *tag)
// : pc9821_mate_x_state(mconfig, type, tag)
// {
// }
//
// void pc9821v13(machine_config &config);
// void pc9821v20(machine_config &config);
// void pc9821v13(machine_config &config);
// void pc9821v20(machine_config &config);
//};
// 9821NOTE
@ -193,19 +193,19 @@ public:
//class pc9821_note_state : public pc9821_state
//{
//public:
// pc9821_note_state(const machine_config &mconfig, device_type type, const char *tag)
// : pc9821_state(mconfig, type, tag)
// , m_pmc(*this, "pmc")
// {
// }
// pc9821_note_state(const machine_config &mconfig, device_type type, const char *tag)
// : pc9821_state(mconfig, type, tag)
// , m_pmc(*this, "pmc")
// {
// }
//
// void pc9821ne(machine_config &config);
// void pc9821ne(machine_config &config);
//
//protected:
// void pc9821ne_io(address_map &map) ATTR_COLD;
// void pc9821ne_io(address_map &map) ATTR_COLD;
//
//private:
// required_device<redwood1_device> m_pmc;
// required_device<redwood1_device> m_pmc;
//};
class pc9821_note_lavie_state : public pc9821_state

2
src/mame/nec/pc98_kbd.cpp
View File

@ -421,7 +421,7 @@ void pc98_119_kbd_device::key_repeat(uint8_t row, uint8_t column)
m_repeat_state[code] ^= 1;
code |= m_repeat_state[code] << 7;
send_key(code);
send_key(code);
}
void pc98_119_kbd_device::received_byte(u8 byte)

2
src/mame/nec/pc98_memsw.h
View File

@ -10,7 +10,7 @@
class pc98_memsw_device : public device_t,
public device_nvram_interface
public device_nvram_interface
{
public:
pc98_memsw_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

2
src/mame/nec/pc98_sdip.h
View File

@ -10,7 +10,7 @@
class pc98_sdip_device : public device_t,
public device_nvram_interface
public device_nvram_interface
{
public:
pc98_sdip_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

6
src/mame/sega/model2.h
View File

@ -768,7 +768,7 @@ struct model2_state::triangle
u8 luma = 0;
int16_t viewport[4] = { 0, 0, 0, 0 };
int16_t center[2] = { 0, 0 };
u8 window = 0;
u8 window = 0;
};
struct model2_state::quad_m2
@ -823,8 +823,8 @@ struct model2_state::raster_state
u16 max_z = 0; // Maximum sortable Z value
u16 texture_ram[0x10000]; // Texture RAM pointer
u8 log_ram[0x40000]; // Log RAM pointer
u8 cur_window = 0; // Current window
plane clip_plane[4][4]; // Polygon clipping planes
u8 cur_window = 0; // Current window
plane clip_plane[4][4]; // Polygon clipping planes
};
/*******************************************