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Pass 2 of struct modernization.

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This commit is contained in:
Aaron Giles 2012-09-15 22:30:30 +00:00
parent 000f9d27ed
commit cff1004165
217 changed files with 1100 additions and 1100 deletions
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4
src/emu/cpu/alph8201/8201dasm.c
View File

@ -259,14 +259,14 @@ static const char *const Formats[] = {
#define MAX_OPS (((sizeof(Formats) / sizeof(Formats[0])) - 1) / PTRS_PER_FORMAT)
typedef struct opcode {
struct AD8201Opcode {
byte mask;
byte bits;
byte type;
byte pmask;
byte pdown;
const char *fmt;
} AD8201Opcode;
};
static AD8201Opcode Op[MAX_OPS+1];
static int OpInizialized = 0;

4
src/emu/cpu/arm/arm.c
View File

@ -227,7 +227,7 @@ enum
/* Private Data */
/* sArmRegister defines the CPU state */
typedef struct
struct ARM_REGS
{
int icount;
UINT32 sArmRegister[kNumRegisters];
@ -239,7 +239,7 @@ typedef struct
address_space *program;
direct_read_data *direct;
endianness_t endian;
} ARM_REGS;
};
/* Prototypes */
static void HandleALU( ARM_REGS* cpustate, UINT32 insn);

4
src/emu/cpu/arm7/arm7core.h
View File

@ -185,7 +185,7 @@ enum
/* CPU state struct */
typedef struct
struct arm_state
{
ARM7CORE_REGS // these must be included in your cpu specific register implementation
ARM7COPRO_REGS
@ -196,7 +196,7 @@ typedef struct
#if ARM7_MMU_ENABLE_HACK
UINT32 mmu_enable_addr; // workaround for "MMU is enabled when PA != VA" problem
#endif
} arm_state;
};
/****************************************************************************************************
* VARIOUS INTERNAL STRUCS/DEFINES/ETC..

12
src/emu/cpu/cubeqcpu/cubeqcpu.c
View File

@ -71,7 +71,7 @@ enum alu_dst
STRUCTURES & TYPEDEFS
***************************************************************************/
typedef struct
struct cquestsnd_state
{
/* AM2901 internals */
UINT16 ram[16];
@ -101,10 +101,10 @@ typedef struct
address_space *program;
direct_read_data *direct;
int icount;
} cquestsnd_state;
};
typedef struct
struct cquestrot_state
{
/* AM2901 internals */
UINT16 ram[16];
@ -143,10 +143,10 @@ typedef struct
address_space *program;
direct_read_data *direct;
int icount;
} cquestrot_state;
};
typedef struct
struct cquestlin_state
{
/* 12-bit AM2901 internals */
UINT16 ram[16];
@ -190,7 +190,7 @@ typedef struct
address_space *program;
direct_read_data *direct;
int icount;
} cquestlin_state;
};
/***************************************************************************
STATE ACCESSORS

20
src/emu/cpu/dsp56k/dsp56k.h
View File

@ -30,7 +30,7 @@ DECLARE_LEGACY_CPU_DEVICE(DSP56156, dsp56k);
STRUCTURES & TYPEDEFS
***************************************************************************/
// 5-4 Host Interface
typedef struct
struct dsp56k_host_interface
{
// **** Dsp56k side **** //
// Host Control Register
@ -62,10 +62,10 @@ typedef struct
// HACK - Host interface bootstrap write offset
UINT16 bootstrap_offset;
} dsp56k_host_interface;
};
// 1-9 ALU
typedef struct
struct dsp56k_data_alu
{
// Four 16-bit input registers (can be accessed as 2 32-bit registers)
PAIR x;
@ -79,10 +79,10 @@ typedef struct
// One data bus shifter/limiter
// A parallel, single cycle, non-pipelined Multiply-Accumulator (MAC) unit
// Basics
} dsp56k_data_alu;
};
// 1-10 Address Generation Unit (AGU)
typedef struct
struct dsp56k_agu
{
// Four address registers
UINT16 r0;
@ -109,10 +109,10 @@ typedef struct
// UINT8 status;
// Basics
} dsp56k_agu;
};
// 1-11 Program Control Unit (PCU)
typedef struct
struct dsp56k_pcu
{
// Program Counter
UINT16 pc;
@ -146,10 +146,10 @@ typedef struct
// Other PCU internals
UINT16 reset_vector;
} dsp56k_pcu;
};
// 1-8 The dsp56156 CORE
typedef struct
struct dsp56k_core
{
// PROGRAM CONTROLLER
dsp56k_pcu PCU;
@ -197,7 +197,7 @@ typedef struct
UINT16 peripheral_ram[0x40];
UINT16 program_ram[0x800];
} dsp56k_core;
};
INLINE dsp56k_core *get_safe_token(device_t *device)

4
src/emu/cpu/dsp56k/dsp56pcu.c
View File

@ -236,11 +236,11 @@ void pcu_reset(dsp56k_core* cpustate)
/***************************************************************************
INTERRUPT HANDLING
***************************************************************************/
typedef struct
struct dsp56k_irq_data
{
UINT16 irq_vector;
char irq_source[128];
} dsp56k_irq_data;
};
dsp56k_irq_data dsp56k_interrupt_sources[32];

4
src/emu/cpu/esrip/esrip.c
View File

@ -61,7 +61,7 @@ CPU_DISASSEMBLE( esrip );
STRUCTURES & TYPEDEFS
***************************************************************************/
typedef struct
struct esrip_state
{
UINT16 ram[32];
UINT16 acc;
@ -118,7 +118,7 @@ typedef struct
write16_device_func fdt_w;
UINT8 (*status_in)(running_machine &machine);
int (*draw)(running_machine &machine, int l, int r, int fig, int attr, int addr, int col, int x_scale, int bank);
} esrip_state;
};
INLINE esrip_state *get_safe_token(device_t *device)

4
src/emu/cpu/g65816/g65816ds.c
View File

@ -26,12 +26,12 @@ author (Karl Stenerud) at karl@higashiyama-unet.ocn.ne.jp.
#define ADDRESS_65816(A) ((A)&0xffffff)
typedef struct
struct opcode_struct
{
unsigned char name;
unsigned char flag;
unsigned char ea;
} opcode_struct;
};
enum
{

4
src/emu/cpu/h6280/h6280.h
View File

@ -37,7 +37,7 @@ enum
/****************************************************************************
* The 6280 registers.
****************************************************************************/
typedef struct
struct h6280_Regs
{
int ICount;
@ -70,7 +70,7 @@ typedef struct
INT32 NZ; /* last value (lazy N and Z flag) */
#endif
UINT8 io_buffer; /* last value written to the PSG, timer, and interrupt pages */
} h6280_Regs;
};
DECLARE_LEGACY_CPU_DEVICE(H6280, h6280);

16
src/emu/cpu/h83002/h8priv.h
View File

@ -11,30 +11,30 @@
#define H8_MAX_PORTS (16) // number of I/O ports defined architecturally (1-9 and A-G = 16)
typedef struct
struct H8S2XXX_TPU_ITEM
{
UINT32 tgr, irq, out;
} H8S2XXX_TPU_ITEM;
};
typedef struct
struct H8S2XXX_TPU
{
emu_timer *timer;
int cycles_per_tick;
UINT64 timer_cycles;
} H8S2XXX_TPU;
};
typedef struct
struct H8S2XXX_SCI
{
emu_timer *timer;
UINT32 bitrate;
} H8S2XXX_SCI;
};
typedef struct
struct H8S2XXX_TMR
{
emu_timer *timer;
int cycles_per_tick;
UINT64 timer_cycles;
} H8S2XXX_TMR;
};
struct h83xx_state
{

4
src/emu/cpu/h83002/h8speriph.c
View File

@ -1158,13 +1158,13 @@ static TIMER_CALLBACK( h8s_tpu_callback)
// SERIAL CONTROLLER INTERFACE //
/////////////////////////////////
typedef struct
struct H8S_SCI_ENTRY
{
UINT32 reg_smr, reg_brr, reg_scr, reg_tdr, reg_ssr, reg_rdr;
UINT32 reg_pdr, reg_port;
UINT8 port_mask_sck, port_mask_txd, port_mask_rxd;
UINT8 int_tx, int_rx;
} H8S_SCI_ENTRY;
};
const H8S_SCI_ENTRY H8S_SCI_TABLE[] =
{

4
src/emu/cpu/hcd62121/hcd62121d.c
View File

@ -32,12 +32,12 @@ enum
_4, /* for nibble shifts */
};
typedef struct
struct hcd62121_dasm
{
const char *str;
UINT8 arg1;
UINT8 arg2;
} hcd62121_dasm;
};
static const hcd62121_dasm hcd62121_ops[256] =

4
src/emu/cpu/hd61700/hd61700d.c
View File

@ -39,13 +39,13 @@ enum
OP_RSIR,
};
typedef struct
struct hd61700_dasm
{
const char *str;
UINT8 arg1;
UINT8 arg2;
bool optjr;
} hd61700_dasm;
};
static const hd61700_dasm hd61700_ops[256] =
{

4
src/emu/cpu/hd6309/6309dasm.c
View File

@ -25,14 +25,14 @@
#include "hd6309.h"
// Opcode structure
typedef struct
struct opcodeinfo
{
UINT8 opcode; // 8-bit opcode value
UINT8 length; // Opcode length in bytes
char name[6]; // Opcode name
UINT8 mode; // Addressing mode
unsigned flags; // Disassembly flags
} opcodeinfo;
};
enum hd6309_addressing_modes
{

4
src/emu/cpu/i386/cycles.h
View File

@ -337,11 +337,11 @@ typedef enum
#define CPU_CYCLES_MEDIAGX 3
typedef struct
struct X86_CYCLE_TABLE
{
X86_CYCLES op;
UINT8 cpu_cycles[X86_NUM_CPUS][2];
} X86_CYCLE_TABLE;
};
static const X86_CYCLE_TABLE x86_cycle_table[] =
{

8
src/emu/cpu/i386/i386dasm.c
View File

@ -90,19 +90,19 @@ enum
#define SPECIAL64 0x800
#define SPECIAL64_ENT(x) (SPECIAL64 | ((x) << 24))
typedef struct {
struct I386_OPCODE {
const char *mnemonic;
UINT32 flags;
UINT32 param1;
UINT32 param2;
UINT32 param3;
offs_t dasm_flags;
} I386_OPCODE;
};
typedef struct {
struct GROUP_OP {
char mnemonic[32];
const I386_OPCODE *opcode;
} GROUP_OP;
};
static const UINT8 *opcode_ptr;
static const UINT8 *opcode_ptr_base;

4
src/emu/cpu/i386/i386ops.h
View File

@ -1,9 +1,9 @@
typedef struct {
struct X86_OPCODE {
UINT8 opcode;
UINT32 flags;
void (*handler16)(i386_state *cpustate);
void (*handler32)(i386_state *cpustate);
} X86_OPCODE;
};
#define OP_I386 0x1
#define OP_FPU 0x2

20
src/emu/cpu/i386/i386priv.h
View File

@ -197,16 +197,16 @@ enum
#define MXCSR_RC (3<<13) // Rounding Control
#define MXCSR_FZ (1<<15) // Flush to Zero
typedef struct {
struct I386_SREG {
UINT16 selector;
UINT16 flags;
UINT32 base;
UINT32 limit;
int d; // Operand size
bool valid;
} I386_SREG;
};
typedef struct
struct I386_CALL_GATE
{
UINT16 segment;
UINT16 selector;
@ -215,19 +215,19 @@ typedef struct
UINT8 dpl;
UINT8 dword_count;
UINT8 present;
} I386_CALL_GATE;
};
typedef struct {
struct I386_SYS_TABLE {
UINT32 base;
UINT16 limit;
} I386_SYS_TABLE;
};
typedef struct {
struct I386_SEG_DESC {
UINT16 segment;
UINT16 flags;
UINT32 base;
UINT32 limit;
} I386_SEG_DESC;
};
typedef union {
UINT32 d[8];
@ -420,7 +420,7 @@ static int i386_limit_check(i386_state *cpustate, int seg, UINT32 offset);
/***********************************************************************************/
typedef struct {
struct MODRM_TABLE {
struct {
int b;
int w;
@ -431,7 +431,7 @@ typedef struct {
int w;
int d;
} rm;
} MODRM_TABLE;
};
extern MODRM_TABLE i386_MODRM_table[256];

4
src/emu/cpu/i860/i860dec.c
View File

@ -4073,13 +4073,13 @@ enum {
};
typedef struct {
struct decode_tbl_t {
/* Execute function for this opcode. */
void (*insn_exec)(i860s *, UINT32);
/* Flags for this opcode. */
char flags;
} decode_tbl_t;
};
/* First-level decode table (i.e., for the 6 primary opcode bits). */

4
src/emu/cpu/i860/i860dis.c
View File

@ -374,7 +374,7 @@ enum
};
typedef struct
struct decode_tbl_t
{
/* Disassembly function for this opcode.
Call with buffer, mnemonic, pc, insn. */
@ -386,7 +386,7 @@ typedef struct
/* Mnemonic of this opcode (sometimes partial when more decode is
done in disassembly routines-- e.g., loads and stores). */
const char *mnemonic;
} decode_tbl_t;
};
/* First-level decode table (i.e., for the 6 primary opcode bits). */

4
src/emu/cpu/i960/i960dis.c
View File

@ -8,11 +8,11 @@
#include "i960.h"
#include "i960dis.h"
typedef struct
struct mnemonic_t
{
const char *mnem;
unsigned short type;
} mnemonic_t;
};
static const mnemonic_t mnemonic[256] = {

4
src/emu/cpu/konami/knmidasm.c
View File

@ -1581,10 +1581,10 @@ static void absd( char *buf ) {
*********************************************************************************/
typedef struct {
struct konami_opcode_def {
void (*decode)( char *buf );
int confirmed;
} konami_opcode_def;
};
static const konami_opcode_def op_table[256] = {
/* 00 */ { illegal, 0 },

2
src/emu/cpu/lh5801/5801dasm.c
View File

@ -131,7 +131,7 @@ static const char *const InsNames[]={
"RPV", "SPV",
};
typedef struct { Ins ins; Adr adr; Regs reg; } Entry;
struct Entry { Ins ins; Adr adr; Regs reg; };
static const Entry table[0x100]={
{ SBC, Reg, XL }, // 0

4
src/emu/cpu/m37710/m7700ds.c
View File

@ -16,12 +16,12 @@ Based on G65C816 CPU Emulator by Karl Stenerud
#define ADDRESS_24BIT(A) ((A)&0xffffff)
typedef struct
struct opcode_struct
{
unsigned char name;
unsigned char flag;
unsigned char ea;
} opcode_struct;
};
enum
{

4
src/emu/cpu/m68000/m68k_in.c
View File

@ -128,13 +128,13 @@ void (*m68ki_instruction_jump_table[NUM_CPU_TYPES][0x10000])(m68ki_cpu_core *m68
unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
/* This is used to generate the opcode handler jump table */
typedef struct
struct opcode_handler_struct
{
void (*opcode_handler)(m68ki_cpu_core *m68k); /* handler function */
unsigned int mask; /* mask on opcode */
unsigned int match; /* what to match after masking */
unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
} opcode_handler_struct;
};
/* Opcode handler table */

4
src/emu/cpu/m68000/m68kdasm.c
View File

@ -174,13 +174,13 @@ static int valid_ea(UINT32 opcode, UINT32 mask);
static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr);
/* used to build opcode handler jump table */
typedef struct
struct opcode_struct
{
void (*opcode_handler)(void); /* handler function */
UINT32 mask; /* mask on opcode */
UINT32 match; /* what to match after masking */
UINT32 ea_mask; /* what ea modes are allowed */
} opcode_struct;
};

16
src/emu/cpu/m68000/m68kmake.c
View File

@ -175,7 +175,7 @@ enum
/* Everything we need to know about an opcode */
typedef struct
struct opcode_struct
{
char name[MAX_NAME_LENGTH]; /* opcode handler name */
unsigned char size; /* Size of operation */
@ -188,33 +188,33 @@ typedef struct
char cpu_mode[NUM_CPUS]; /* User or supervisor mode */
char cpus[NUM_CPUS+1]; /* Allowed CPUs */
unsigned char cycles[NUM_CPUS]; /* cycles for 000, 010, 020, 030, 040 */
} opcode_struct;
};
/* All modifications necessary for a specific EA mode of an instruction */
typedef struct
struct ea_info_struct
{
const char* fname_add;
const char* ea_add;
unsigned int mask_add;
unsigned int match_add;
} ea_info_struct;
};
/* Holds the body of a function */
typedef struct
struct body_struct
{
char body[MAX_BODY_LENGTH][MAX_LINE_LENGTH+1];
int length;
} body_struct;
};
/* Holds a sequence of search / replace strings */
typedef struct
struct replace_struct
{
char replace[MAX_REPLACE_LENGTH][2][MAX_LINE_LENGTH+1];
int length;
} replace_struct;
};
/* Function Prototypes */

4
src/emu/cpu/m6805/m6805.c
View File

@ -45,7 +45,7 @@ enum
};
/* 6805 Registers */
typedef struct
struct m6805_Regs
{
/* Pre-pointerafied public globals */
int iCount;
@ -67,7 +67,7 @@ typedef struct
direct_read_data *direct;
int irq_state[9]; /* KW Additional lines for HD63705 */
int nmi_state;
} m6805_Regs;
};
INLINE m6805_Regs *get_safe_token(device_t *device)
{

4
src/emu/cpu/m6809/6809dasm.c
View File

@ -20,14 +20,14 @@
#include "m6809.h"
// Opcode structure
typedef struct
struct opcodeinfo
{
UINT8 opcode; // 8-bit opcode value
UINT8 length; // Opcode length in bytes
char name[6]; // Opcode name
UINT8 mode; // Addressing mode
unsigned flags; // Disassembly flags
} opcodeinfo;
};
enum m6809_addressing_modes
{

4
src/emu/cpu/mc68hc11/hc11dasm.c
View File

@ -26,10 +26,10 @@ enum
PAGE4,
};
typedef struct {
struct M68HC11_OPCODE {
char mnemonic[32];
int address_mode;
} M68HC11_OPCODE;
};
static const M68HC11_OPCODE opcode_table[256] =
{

4
src/emu/cpu/minx/minx.c
View File

@ -65,7 +65,7 @@ TODO:
#define EXEC_01 0x01
typedef struct {
struct minx_state {
// MINX_CONFIG config;
UINT16 PC;
UINT16 SP;
@ -87,7 +87,7 @@ typedef struct {
legacy_cpu_device *device;
address_space *program;
int icount;
} minx_state;
};
#define RD(offset) minx->program->read_byte( offset )
#define WR(offset,data) minx->program->write_byte( offset, data )

4
src/emu/cpu/mips/mips3.c
View File

@ -86,7 +86,7 @@
***************************************************************************/
/* MIPS3 Registers */
typedef struct
struct mips3_regs
{
/* core state */
mips3_state core;
@ -112,7 +112,7 @@ typedef struct
void (*ldr)(UINT32 op);
void (*sdl)(UINT32 op);
void (*sdr)(UINT32 op);
} mips3_regs;
};

8
src/emu/cpu/nec/necdasm.c
View File

@ -74,19 +74,19 @@ enum
SEG_SS
};
typedef struct {
struct I386_OPCODE {
char mnemonic[32];
UINT32 flags;
UINT32 param1;
UINT32 param2;
UINT32 param3;
offs_t dasm_flags;
} I386_OPCODE;
};
typedef struct {
struct GROUP_OP {
char mnemonic[32];
const I386_OPCODE *opcode;
} GROUP_OP;
};
static const UINT8 *opcode_ptr;
static const UINT8 *opcode_ptr_base;

20
src/emu/cpu/powerpc/ppc.c
View File

@ -195,15 +195,15 @@ static UINT32 ppc_field_xlat[256];
#define BYTE_REVERSE16(x) ((((x) >> 8) & 0xff) | (((x) << 8) & 0xff00))
#define BYTE_REVERSE32(x) ((((x) >> 24) & 0xff) | (((x) >> 8) & 0xff00) | (((x) << 8) & 0xff0000) | (((x) << 24) & 0xff000000))
typedef struct {
struct DMA_REGS {
UINT32 cr;
UINT32 da;
UINT32 sa;
UINT32 ct;
UINT32 cc;
} DMA_REGS;
};
typedef struct {
struct SPU_REGS {
UINT8 spls;
UINT8 sphs;
UINT16 brd;
@ -214,7 +214,7 @@ typedef struct {
UINT8 sptb;
emu_timer *rx_timer;
emu_timer *tx_timer;
} SPU_REGS;
};
typedef union {
UINT64 id;
@ -226,13 +226,13 @@ typedef union {
float f;
} FPR32;
typedef struct {
struct BATENT {
UINT32 u;
UINT32 l;
} BATENT;
};
typedef struct {
struct PPC_REGS {
UINT32 r[32];
UINT32 pc;
UINT32 npc;
@ -350,15 +350,15 @@ typedef struct {
void (* optable59[1024])(UINT32);
void (* optable63[1024])(UINT32);
void (* optable[64])(UINT32);
} PPC_REGS;
};
typedef struct {
struct PPC_OPCODE {
int code;
int subcode;
void (* handler)(UINT32);
} PPC_OPCODE;
};

4
src/emu/cpu/powerpc/ppc_dasm.c
View File

@ -102,7 +102,7 @@ enum
* Describes the layout of an instruction.
*/
typedef struct
struct IDESCR
{
char mnem[32]; // mnemonic
UINT32 match; // bit pattern of instruction after it has been masked
@ -110,7 +110,7 @@ typedef struct
// bit pattern to determine a match)
int format; // operand format
int flags; // flags
} IDESCR;
};
/*
* Instruction Table

4
src/emu/cpu/saturn/saturnds.c
View File

@ -586,12 +586,12 @@ enum _opcode_adr
};
typedef enum _opcode_adr opcode_adr;
typedef struct
struct OPCODE
{
opcode_sel sel;
opcode_adr adr;
MNEMONICS mnemonic;
} OPCODE;
};
static const char *field_2_string(int adr_enum)
{

4
src/emu/cpu/scudsp/scudspdasm.c
View File

@ -26,12 +26,12 @@ enum
EA_MVIDSTMEM,
};
typedef struct {
struct SCUDSP_OPCODE {
char mnemonic[32];
int address_mode_1;
int address_mode_2;
int address_mode_3,
} SCUDSP_OPCODE;
};
static const SCUDSP_OPCODE alu_table[16] =
{

4
src/emu/cpu/sh2/sh2comn.h
View File

@ -90,7 +90,7 @@ do { \
sh2_exception(sh2,message,irq); \
} while(0)
typedef struct
struct sh2_state
{
UINT32 ppc;
UINT32 pc;
@ -182,7 +182,7 @@ typedef struct
uml::code_handle * nocode; /* nocode */
uml::code_handle * out_of_cycles; /* out of cycles exception handler */
#endif
} sh2_state;
};
#ifdef USE_SH2DRC
class sh2_frontend : public drc_frontend

4
src/emu/cpu/sh4/sh4comn.h
View File

@ -49,7 +49,7 @@ class sh4_frontend;
#endif
typedef struct
struct sh4_state
{
UINT32 ppc;
UINT32 pc, spc;
@ -208,7 +208,7 @@ typedef struct
UINT32 prefadr;
UINT32 target;
#endif
} sh4_state;
};
#ifdef USE_SH4DRC
class sh4_frontend : public drc_frontend

16
src/emu/cpu/sharc/sharc.c
View File

@ -39,13 +39,13 @@ enum
SHARC_B12, SHARC_B13, SHARC_B14, SHARC_B15,
};
typedef struct
struct SHARC_DAG
{
UINT32 i[8];
UINT32 m[8];
UINT32 b[8];
UINT32 l[8];
} SHARC_DAG;
};
typedef union
{
@ -53,7 +53,7 @@ typedef union
float f;
} SHARC_REG;
typedef struct
struct DMA_REGS
{
UINT32 control;
UINT32 int_index;
@ -64,16 +64,16 @@ typedef struct
UINT32 ext_index;
UINT32 ext_modifier;
UINT32 ext_count;
} DMA_REGS;
};
typedef struct
struct LADDR
{
UINT32 addr;
UINT32 code;
UINT32 loop_type;
} LADDR;
};
typedef struct
struct DMA_OP
{
UINT32 src;
UINT32 dst;
@ -86,7 +86,7 @@ typedef struct
INT32 chained_direction;
emu_timer *timer;
bool active;
} DMA_OP;
};
typedef struct _SHARC_REGS SHARC_REGS;
struct _SHARC_REGS

4
src/emu/cpu/sharc/sharc.h
View File

@ -17,9 +17,9 @@ typedef enum
BOOT_MODE_NOBOOT
} SHARC_BOOT_MODE;
typedef struct {
struct sharc_config {
SHARC_BOOT_MODE boot_mode;
} sharc_config;
};
extern void sharc_set_flag_input(device_t *device, int flag_num, int state);

4
src/emu/cpu/sharc/sharcdsm.h
View File

@ -69,9 +69,9 @@ static const char mr_regnames[16][8] =
"???", "???", "???", "???", "???", "???", "???", "???"
};
typedef struct
struct SHARC_DASM_OP
{
UINT32 op_mask;
UINT32 op_bits;
UINT32 (* handler)(UINT32, UINT64);
} SHARC_DASM_OP;
};

4
src/emu/cpu/sharc/sharcops.h
View File

@ -1,9 +1,9 @@
typedef struct
struct SHARC_OP
{
UINT32 op_mask;
UINT32 op_bits;
void (*handler)(SHARC_REGS *cpustate);
} SHARC_OP;
};
static const SHARC_OP sharc_opcode_table[] =
{

4
src/emu/cpu/sm8500/sm8500.h
View File

@ -4,10 +4,10 @@
#define __SM8500_H__
typedef struct {
struct SM8500_CONFIG {
void (*handle_dma)(device_t *device, int cycles);
void (*handle_timers)(device_t *device, int cycles);
} SM8500_CONFIG;
};
/* interrupts */
#define ILL_INT 0

4
src/emu/cpu/spc700/spc700.c
View File

@ -66,7 +66,7 @@ Address Function Register R/W When Reset Remarks
#include "spc700.h"
/* CPU Structure */
typedef struct
struct spc700i_cpu
{
uint a; /* Accumulator */
uint x; /* Index Register X */
@ -96,7 +96,7 @@ typedef struct
uint temp1, temp2, temp3;
short spc_int16;
int spc_int32;
} spc700i_cpu;
};
INLINE spc700i_cpu *get_safe_token(device_t *device)
{

4
src/emu/cpu/spc700/spc700ds.c
View File

@ -20,11 +20,11 @@ author (Karl Stenerud) at karl@higashiyama-unet.ocn.ne.jp.
typedef struct
struct opcode_struct
{
unsigned char name;
unsigned char args[2];
} opcode_struct;
};
enum
{

8
src/emu/cpu/superfx/superfx.c
View File

@ -2,18 +2,18 @@
#include "debugger.h"
#include "superfx.h"
typedef struct
struct pixelcache_t
{
UINT16 offset;
UINT8 bitpend;
UINT8 data[8];
} pixelcache_t;
};
typedef struct
struct cache_t
{
UINT8 buffer[0x200];
UINT8 valid[0x20];
} cache_t;
};
struct superfx_state
{

4
src/emu/cpu/tlcs900/900tbl.c
View File

@ -3852,13 +3852,13 @@ static void _ZCF(tlcs900_state *cpustate)
}
typedef struct
struct tlcs900inst
{
void (*opfunc)(tlcs900_state *cpustate);
int operand1;
int operand2;
int cycles;
} tlcs900inst;
};
static void prepare_operands(tlcs900_state *cpustate, const tlcs900inst *inst)

4
src/emu/cpu/tlcs900/dasm900.c
View File

@ -88,12 +88,12 @@ enum e_operand
};
typedef struct
struct tlcs900inst
{
e_mnemonics mnemonic;
e_operand operand1;
e_operand operand2;
} tlcs900inst;
};
static const tlcs900inst mnemonic_80[256] =

12
src/emu/cpu/tms32051/tms32051.c
View File

@ -46,7 +46,7 @@ enum
TMS32051_AR7,
};
typedef struct
struct PMST
{
UINT16 iptr;
UINT16 avis;
@ -56,18 +56,18 @@ typedef struct
UINT16 ndx;
UINT16 trm;
UINT16 braf;
} PMST;
};
typedef struct
struct ST0
{
UINT16 dp;
UINT16 intm;
UINT16 ovm;
UINT16 ov;
UINT16 arp;
} ST0;
};
typedef struct
struct ST1
{
UINT16 arb;
UINT16 cnf;
@ -77,7 +77,7 @@ typedef struct
UINT16 hm;
UINT16 xf;
UINT16 pm;
} ST1;
};
struct tms32051_state
{

16
src/emu/cpu/tms57002/tmsmake.c
View File

@ -31,26 +31,26 @@ enum {
enum { PA, PC, PD, PD24, PI, PML, PMO, PMV, PB, PWA, PWC, PWD, SFAI };
typedef struct {
struct instr {
char *name;
char *dasm;
char *run;
int line, cycles, type, baseval, variants;
unsigned int flags;
} instr;
};
typedef struct {
struct pdesc {
const char *opt;
int pcount, id;
} pdesc;
};
typedef struct {
struct pinf {
const char *start;
int size;
int id;
int pcount;
int ppos[4];
} pinf;
};
static const pdesc pp_r[] = {
{ "a", 0, PA },
@ -74,12 +74,12 @@ static instr cat1[0x40], cat2[0x80], cat3[0x80];
static pinf parse_res[4096];
static int parse_count;
typedef struct {
struct vinfo {
unsigned int mask;
int variants;
const char *name;
const char *getter;
} vinfo;
};
enum { IxCMODE, IxDMODE, IxSFAI, IxCRM, IxDBP, IxSFAO, IxSFMO, IxRND, IxMOVM, IxSFMA, IxCOUNT };

8
src/emu/cpu/tms7000/7000dasm.c
View File

@ -4,17 +4,17 @@
typedef enum { DONE, NONE, UI8, I8, UI16, I16, PCREL, PCABS, TRAP } operandtype;
typedef struct {
struct oprandinfo {
char opstr[4][12];
operandtype decode[4];
} oprandinfo;
};
typedef struct {
struct opcodeinfo {
int opcode;
char name[8];
int operand;
UINT32 s_flag;
} opcodeinfo;
};
static const oprandinfo of[] = {
/* 00 */ { {" B,A", "", "", ""}, {NONE, DONE, DONE, DONE} },

4
src/emu/cpu/upd7810/upd7810.h
View File

@ -33,10 +33,10 @@ typedef enum
typedef int (*upd7810_io_callback)(device_t *device, int ioline, int state);
// use it as reset parameter in the Machine struct
typedef struct {
struct UPD7810_CONFIG {
UPD7810_TYPE type;
upd7810_io_callback io_callback;
} UPD7810_CONFIG;
};
enum
{

2
src/emu/drawgfxm.h
View File

@ -56,7 +56,7 @@
/* special priority type meaning "none" */
typedef struct { char dummy[3]; } NO_PRIORITY;
struct NO_PRIORITY { char dummy[3]; };
extern bitmap_ind8 drawgfx_dummy_priority_bitmap;
#define DECLARE_NO_PRIORITY bitmap_t &priority = drawgfx_dummy_priority_bitmap;

8
src/emu/machine/68681.c
View File

@ -44,7 +44,7 @@ static const char *const duart68681_reg_write_names[0x10] =
#define RX_FIFO_SIZE 3
typedef struct
struct DUART68681_CHANNEL
{
/* Registers */
UINT8 CR; /* Command register */
@ -70,9 +70,9 @@ typedef struct
UINT8 tx_ready;
emu_timer *tx_timer;
} DUART68681_CHANNEL;
};
typedef struct
struct duart68681_state
{
/* device */
device_t *device;
@ -99,7 +99,7 @@ typedef struct
/* UART channels */
DUART68681_CHANNEL channel[2];
} duart68681_state;
};
INLINE duart68681_state *get_safe_token(device_t *device)
{

4
src/emu/machine/matsucd.c
View File

@ -27,7 +27,7 @@ can be expanded with support for the other drives as needed.
#define MATSU_STATUS_MEDIA ( 1 << 6 ) /* media present (in caddy or tray) */
#define MATSU_STATUS_DOORCLOSED ( 1 << 7 ) /* tray status */
typedef struct
struct matsucd
{
UINT8 enabled; /* /ENABLE - Unit enabled */
UINT8 cmd_signal; /* /CMD - Command mode */
@ -53,7 +53,7 @@ typedef struct
cdrom_file *cdrom;
device_t *cdda;
emu_timer *frame_timer;
} matsucd;
};
static matsucd cd;

4
src/emu/machine/msm6242.h
View File

@ -30,11 +30,11 @@ struct msm6242_interface
devcb_write_line m_out_int_cb;
};
typedef struct
struct rtc_regs_t
{
UINT8 sec, min, hour, day, wday, month;
UINT16 year;
} rtc_regs_t;
};
// ======================> msm6242_device

8
src/emu/machine/pc16552d.c
View File

@ -34,7 +34,7 @@
#define INT_ENABLE_RX_LINE_STATUS 0x04
#define INT_ENABLE_MODEM_STATUS 0x08
typedef struct
struct PC16552D_CHANNEL
{
UINT16 divisor;
UINT8 reg[8];
@ -48,15 +48,15 @@ typedef struct
int tx_fifo_write_ptr;
int tx_fifo_num;
emu_timer *tx_fifo_timer;
} PC16552D_CHANNEL;
};
typedef struct
struct PC16552D_REGS
{
PC16552D_CHANNEL ch[2];
int frequency;
void (* irq_handler)(running_machine &machine, int channel, int value);
void (* tx_callback)(running_machine &machine, int channel, int count, UINT8* data);
} PC16552D_REGS;
};
#define MAX_PC16552D_CHIPS 4

4
src/emu/machine/rtc9701.h
View File

@ -37,10 +37,10 @@ typedef enum
} rtc9701_state_t;
typedef struct
struct rtc_regs_t
{
UINT8 sec, min, hour, day, wday, month, year;
} rtc_regs_t;
};
// ======================> rtc9701_device

4
src/emu/machine/s3520cf.h
View File

@ -29,10 +29,10 @@ typedef enum
RTC_SET_DATA
} s3520cf_state_t;
typedef struct
struct rtc_regs_t
{
UINT8 sec, min, hour, day, wday, month, year;
} rtc_regs_t;
};
// ======================> s3520cf_device

148
src/emu/machine/s3c2400.h
View File

@ -407,17 +407,17 @@ void s3c2400_uart_fifo_w( device_t *device, int uart, UINT8 data);
TYPE DEFINITIONS
*******************************************************************************/
typedef struct
struct s3c24xx_memcon_regs_t
{
UINT32 data[0x34/4];
} s3c24xx_memcon_regs_t;
};
typedef struct
struct s3c24xx_usbhost_regs_t
{
UINT32 data[0x5C/4];
} s3c24xx_usbhost_regs_t;
};
typedef struct
struct s3c24xx_irq_regs_t
{
UINT32 srcpnd;
UINT32 intmod;
@ -425,9 +425,9 @@ typedef struct
UINT32 priority;
UINT32 intpnd;
UINT32 intoffset;
} s3c24xx_irq_regs_t;
};
typedef struct
struct s3c24xx_dma_regs_t
{
UINT32 disrc;
UINT32 didst;
@ -436,9 +436,9 @@ typedef struct
UINT32 dcsrc;
UINT32 dcdst;
UINT32 dmasktrig;
} s3c24xx_dma_regs_t;
};
typedef struct
struct s3c24xx_clkpow_regs_t
{
UINT32 locktime;
UINT32 mpllcon;
@ -446,9 +446,9 @@ typedef struct
UINT32 clkcon;
UINT32 clkslow;
UINT32 clkdivn;
} s3c24xx_clkpow_regs_t;
};
typedef struct
struct s3c24xx_lcd_regs_t
{
UINT32 lcdcon1;
UINT32 lcdcon2;
@ -464,14 +464,14 @@ typedef struct
UINT32 reserved[8];
UINT32 dithmode;
UINT32 tpal;
} s3c24xx_lcd_regs_t;
};
typedef struct
struct s3c24xx_lcdpal_regs_t
{
UINT32 data[0x400/4];
} s3c24xx_lcdpal_regs_t;
};
typedef struct
struct s3c24xx_uart_regs_t
{
UINT32 ulcon;
UINT32 ucon;
@ -484,9 +484,9 @@ typedef struct
UINT32 utxh;
UINT32 urxh;
UINT32 ubrdiv;
} s3c24xx_uart_regs_t;
};
typedef struct
struct s3c24xx_pwm_regs_t
{
UINT32 tcfg0;
UINT32 tcfg1;
@ -505,38 +505,38 @@ typedef struct
UINT32 tcnto3;
UINT32 tcntb4;
UINT32 tcnto4;
} s3c24xx_pwm_regs_t;
};
typedef struct
struct s3c24xx_usbdev_regs_t
{
UINT32 data[0xBC/4];
} s3c24xx_usbdev_regs_t;
};
typedef struct
struct s3c24xx_wdt_regs_t
{
UINT32 wtcon;
UINT32 wtdat;
UINT32 wtcnt;
} s3c24xx_wdt_regs_t;
};
typedef struct
struct s3c24xx_iic_regs_t
{
UINT32 iiccon;
UINT32 iicstat;
UINT32 iicadd;
UINT32 iicds;
} s3c24xx_iic_regs_t;
};
typedef struct
struct s3c24xx_iis_regs_t
{
UINT32 iiscon;
UINT32 iismod;
UINT32 iispsr;
UINT32 iisfcon;
UINT32 iisfifo;
} s3c24xx_iis_regs_t;
};
typedef struct
struct s3c24xx_gpio_regs_t
{
UINT32 gpacon;
UINT32 gpadat;
@ -561,9 +561,9 @@ typedef struct
UINT32 opencr;
UINT32 misccr;
UINT32 extint;
} s3c24xx_gpio_regs_t;
};
typedef struct
struct s3c24xx_rtc_regs_t
{
UINT32 rtccon;
UINT32 ticnt;
@ -583,15 +583,15 @@ typedef struct
UINT32 bcddow;
UINT32 bcdmon;
UINT32 bcdyear;
} s3c24xx_rtc_regs_t;
};
typedef struct
struct s3c24xx_adc_regs_t
{
UINT32 adccon;
UINT32 adcdat;
} s3c24xx_adc_regs_t;
};
typedef struct
struct s3c24xx_spi_regs_t
{
UINT32 spcon;
UINT32 spsta;
@ -599,41 +599,41 @@ typedef struct
UINT32 sppre;
UINT32 sptdat;
UINT32 sprdat;
} s3c24xx_spi_regs_t;
};
typedef struct
struct s3c24xx_mmc_regs_t
{
UINT32 data[0x40/4];
} s3c24xx_mmc_regs_t;
};
typedef struct
struct s3c24xx_memcon_t
{
s3c24xx_memcon_regs_t regs;
} s3c24xx_memcon_t;
};
typedef struct
struct s3c24xx_usbhost_t
{
s3c24xx_usbhost_regs_t regs;
} s3c24xx_usbhost_t;
};
typedef struct
struct s3c24xx_irq_t
{
s3c24xx_irq_regs_t regs;
int line_irq, line_fiq;
} s3c24xx_irq_t;
};
typedef struct
struct s3c24xx_dma_t
{
s3c24xx_dma_regs_t regs;
emu_timer *timer;
} s3c24xx_dma_t;
};
typedef struct
struct s3c24xx_clkpow_t
{
s3c24xx_clkpow_regs_t regs;
} s3c24xx_clkpow_t;
};
typedef struct
struct s3c24xx_lcd_t
{
s3c24xx_lcd_regs_t regs;
emu_timer *timer;
@ -650,81 +650,81 @@ typedef struct
UINT32 tpal;
UINT32 hpos_min, hpos_max, vpos_min, vpos_max;
UINT32 dma_data, dma_bits;
} s3c24xx_lcd_t;
};
typedef struct
struct s3c24xx_lcdpal_t
{
s3c24xx_lcdpal_regs_t regs;
} s3c24xx_lcdpal_t;
};
typedef struct
struct s3c24xx_uart_t
{
s3c24xx_uart_regs_t regs;
} s3c24xx_uart_t;
};
typedef struct
struct s3c24xx_pwm_t
{
s3c24xx_pwm_regs_t regs;
emu_timer *timer[5];
UINT32 cnt[5];
UINT32 cmp[5];
UINT32 freq[5];
} s3c24xx_pwm_t;
};
typedef struct
struct s3c24xx_usbdev_t
{
s3c24xx_usbdev_regs_t regs;
} s3c24xx_usbdev_t;
};
typedef struct
struct s3c24xx_wdt_t
{
s3c24xx_wdt_regs_t regs;
emu_timer *timer;
} s3c24xx_wdt_t;
};
typedef struct
struct s3c24xx_iic_t
{
s3c24xx_iic_regs_t regs;
emu_timer *timer;
int count;
} s3c24xx_iic_t;
};
typedef struct
struct s3c24xx_iis_t
{
s3c24xx_iis_regs_t regs;
emu_timer *timer;
UINT16 fifo[16/2];
int fifo_index;
} s3c24xx_iis_t;
};
typedef struct
struct s3c24xx_gpio_t
{
s3c24xx_gpio_regs_t regs;
} s3c24xx_gpio_t;
};
typedef struct
struct s3c24xx_rtc_t
{
s3c24xx_rtc_regs_t regs;
emu_timer *timer_tick_count;
emu_timer *timer_update;
} s3c24xx_rtc_t;
};
typedef struct
struct s3c24xx_adc_t
{
s3c24xx_adc_regs_t regs;
} s3c24xx_adc_t;
};
typedef struct
struct s3c24xx_spi_t
{
s3c24xx_spi_regs_t regs;
} s3c24xx_spi_t;
};
typedef struct
struct s3c24xx_mmc_t
{
s3c24xx_mmc_regs_t regs;
} s3c24xx_mmc_t;
};
typedef struct
struct s3c24xx_t
{
const s3c2400_interface *iface;
s3c24xx_memcon_t memcon;
@ -745,6 +745,6 @@ typedef struct
s3c24xx_adc_t adc;
s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
s3c24xx_mmc_t mmc;
} s3c24xx_t;
};
#endif

156
src/emu/machine/s3c2410.h
View File

@ -498,17 +498,17 @@ static const UINT32 MAP_SUBINT_TO_INT[11] =
TYPE DEFINITIONS
*******************************************************************************/
typedef struct
struct s3c24xx_memcon_regs_t
{
UINT32 data[0x34/4];
} s3c24xx_memcon_regs_t;
};
typedef struct
struct s3c24xx_usbhost_regs_t
{
UINT32 data[0x5C/4];
} s3c24xx_usbhost_regs_t;
};
typedef struct
struct s3c24xx_irq_regs_t
{
UINT32 srcpnd;
UINT32 intmod;
@ -518,9 +518,9 @@ typedef struct
UINT32 intoffset;
UINT32 subsrcpnd;
UINT32 intsubmsk;
} s3c24xx_irq_regs_t;
};
typedef struct
struct s3c24xx_dma_regs_t
{
UINT32 disrc;
UINT32 disrcc;
@ -531,9 +531,9 @@ typedef struct
UINT32 dcsrc;
UINT32 dcdst;
UINT32 dmasktrig;
} s3c24xx_dma_regs_t;
};
typedef struct
struct s3c24xx_clkpow_regs_t
{
UINT32 locktime;
UINT32 mpllcon;
@ -541,9 +541,9 @@ typedef struct
UINT32 clkcon;
UINT32 clkslow;
UINT32 clkdivn;
} s3c24xx_clkpow_regs_t;
};
typedef struct
struct s3c24xx_lcd_regs_t
{
UINT32 lcdcon1;
UINT32 lcdcon2;
@ -563,14 +563,14 @@ typedef struct
UINT32 lcdsrcpnd;
UINT32 lcdintmsk;
UINT32 lpcsel;
} s3c24xx_lcd_regs_t;
};
typedef struct
struct s3c24xx_lcdpal_regs_t
{
UINT32 data[0x400/4];
} s3c24xx_lcdpal_regs_t;
};
typedef struct
struct s3c24xx_nand_regs_t
{
UINT32 nfconf;
UINT32 nfcmd;
@ -578,9 +578,9 @@ typedef struct
UINT32 nfdata;
UINT32 nfstat;
UINT32 nfecc;
} s3c24xx_nand_regs_t;
};
typedef struct
struct s3c24xx_uart_regs_t
{
UINT32 ulcon;
UINT32 ucon;
@ -593,9 +593,9 @@ typedef struct
UINT32 utxh;
UINT32 urxh;
UINT32 ubrdiv;
} s3c24xx_uart_regs_t;
};
typedef struct
struct s3c24xx_pwm_regs_t
{
UINT32 tcfg0;
UINT32 tcfg1;
@ -614,38 +614,38 @@ typedef struct
UINT32 tcnto3;
UINT32 tcntb4;
UINT32 tcnto4;
} s3c24xx_pwm_regs_t;
};
typedef struct
struct s3c24xx_usbdev_regs_t
{
UINT32 data[0x130/4];
} s3c24xx_usbdev_regs_t;
};
typedef struct
struct s3c24xx_wdt_regs_t
{
UINT32 wtcon;
UINT32 wtdat;
UINT32 wtcnt;
} s3c24xx_wdt_regs_t;
};
typedef struct
struct s3c24xx_iic_regs_t
{
UINT32 iiccon;
UINT32 iicstat;
UINT32 iicadd;
UINT32 iicds;
} s3c24xx_iic_regs_t;
};
typedef struct
struct s3c24xx_iis_regs_t
{
UINT32 iiscon;
UINT32 iismod;
UINT32 iispsr;
UINT32 iisfcon;
UINT32 iisfifo;
} s3c24xx_iis_regs_t;
};
typedef struct
struct s3c24xx_gpio_regs_t
{
UINT32 gpacon;
UINT32 gpadat;
@ -695,9 +695,9 @@ typedef struct
UINT32 gstatus2;
UINT32 gstatus3;
UINT32 gstatus4;
} s3c24xx_gpio_regs_t;
};
typedef struct
struct s3c24xx_rtc_regs_t
{
UINT32 rtccon;
UINT32 ticnt;
@ -717,18 +717,18 @@ typedef struct
UINT32 bcddow;
UINT32 bcdmon;
UINT32 bcdyear;
} s3c24xx_rtc_regs_t;
};
typedef struct
struct s3c24xx_adc_regs_t
{
UINT32 adccon;
UINT32 adctsc;
UINT32 adcdly;
UINT32 adcdat0;
UINT32 adcdat1;
} s3c24xx_adc_regs_t;
};
typedef struct
struct s3c24xx_spi_regs_t
{
UINT32 spcon;
UINT32 spsta;
@ -736,41 +736,41 @@ typedef struct
UINT32 sppre;
UINT32 sptdat;
UINT32 sprdat;
} s3c24xx_spi_regs_t;
};
typedef struct
struct s3c24xx_sdi_regs_t
{
UINT32 data[0x44/4];
} s3c24xx_sdi_regs_t;
};
typedef struct
struct s3c24xx_memcon_t
{
s3c24xx_memcon_regs_t regs;
} s3c24xx_memcon_t;
};
typedef struct
struct s3c24xx_usbhost_t
{
s3c24xx_usbhost_regs_t regs;
} s3c24xx_usbhost_t;
};
typedef struct
struct s3c24xx_irq_t
{
s3c24xx_irq_regs_t regs;
int line_irq, line_fiq;
} s3c24xx_irq_t;
};
typedef struct
struct s3c24xx_dma_t
{
s3c24xx_dma_regs_t regs;
emu_timer *timer;
} s3c24xx_dma_t;
};
typedef struct
struct s3c24xx_clkpow_t
{
s3c24xx_clkpow_regs_t regs;
} s3c24xx_clkpow_t;
};
typedef struct
struct s3c24xx_lcd_t
{
s3c24xx_lcd_regs_t regs;
emu_timer *timer;
@ -787,89 +787,89 @@ typedef struct
UINT32 tpal;
UINT32 hpos_min, hpos_max, vpos_min, vpos_max;
UINT32 dma_data, dma_bits;
} s3c24xx_lcd_t;
};
typedef struct
struct s3c24xx_lcdpal_t
{
s3c24xx_lcdpal_regs_t regs;
} s3c24xx_lcdpal_t;
};
typedef struct
struct s3c24xx_nand_t
{
s3c24xx_nand_regs_t regs;
UINT8 mecc[3];
int ecc_pos, data_count;
} s3c24xx_nand_t;
};
typedef struct
struct s3c24xx_uart_t
{
s3c24xx_uart_regs_t regs;
} s3c24xx_uart_t;
};
typedef struct
struct s3c24xx_pwm_t
{
s3c24xx_pwm_regs_t regs;
emu_timer *timer[5];
UINT32 cnt[5];
UINT32 cmp[5];
UINT32 freq[5];
} s3c24xx_pwm_t;
};
typedef struct
struct s3c24xx_usbdev_t
{
s3c24xx_usbdev_regs_t regs;
} s3c24xx_usbdev_t;
};
typedef struct
struct s3c24xx_wdt_t
{
s3c24xx_wdt_regs_t regs;
emu_timer *timer;
UINT32 freq, cnt;
} s3c24xx_wdt_t;
};
typedef struct
struct s3c24xx_iic_t
{
s3c24xx_iic_regs_t regs;
emu_timer *timer;
int count;
} s3c24xx_iic_t;
};
typedef struct
struct s3c24xx_iis_t
{
s3c24xx_iis_regs_t regs;
emu_timer *timer;
UINT16 fifo[16/2];
int fifo_index;
} s3c24xx_iis_t;
};
typedef struct
struct s3c24xx_gpio_t
{
s3c24xx_gpio_regs_t regs;
} s3c24xx_gpio_t;
};
typedef struct
struct s3c24xx_rtc_t
{
s3c24xx_rtc_regs_t regs;
emu_timer *timer_tick_count;
emu_timer *timer_update;
} s3c24xx_rtc_t;
};
typedef struct
struct s3c24xx_adc_t
{
s3c24xx_adc_regs_t regs;
} s3c24xx_adc_t;
};
typedef struct
struct s3c24xx_spi_t
{
s3c24xx_spi_regs_t regs;
} s3c24xx_spi_t;
};
typedef struct
struct s3c24xx_sdi_t
{
s3c24xx_sdi_regs_t regs;
} s3c24xx_sdi_t;
};
typedef struct
struct s3c24xx_t
{
const s3c2410_interface *iface;
UINT8 steppingstone[4*1024];
@ -892,6 +892,6 @@ typedef struct
s3c24xx_adc_t adc;
s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
s3c24xx_sdi_t sdi;
} s3c24xx_t;
};
#endif

172
src/emu/machine/s3c2440.h
View File

@ -527,17 +527,17 @@ static const UINT32 MAP_SUBINT_TO_INT[15] =
TYPE DEFINITIONS
*******************************************************************************/
typedef struct
struct s3c24xx_memcon_regs_t
{
UINT32 data[0x34/4];
} s3c24xx_memcon_regs_t;
};
typedef struct
struct s3c24xx_usbhost_regs_t
{
UINT32 data[0x5C/4];
} s3c24xx_usbhost_regs_t;
};
typedef struct
struct s3c24xx_irq_regs_t
{
UINT32 srcpnd;
UINT32 intmod;
@ -547,9 +547,9 @@ typedef struct
UINT32 intoffset;
UINT32 subsrcpnd;
UINT32 intsubmsk;
} s3c24xx_irq_regs_t;
};
typedef struct
struct s3c24xx_dma_regs_t
{
UINT32 disrc;
UINT32 disrcc;
@ -560,9 +560,9 @@ typedef struct
UINT32 dcsrc;
UINT32 dcdst;
UINT32 dmasktrig;
} s3c24xx_dma_regs_t;
};
typedef struct
struct s3c24xx_clkpow_regs_t
{
UINT32 locktime;
UINT32 mpllcon;
@ -571,9 +571,9 @@ typedef struct
UINT32 clkslow;
UINT32 clkdivn;
UINT32 camdivn;
} s3c24xx_clkpow_regs_t;
};
typedef struct
struct s3c24xx_lcd_regs_t
{
UINT32 lcdcon1;
UINT32 lcdcon2;
@ -593,14 +593,14 @@ typedef struct
UINT32 lcdsrcpnd;
UINT32 lcdintmsk;
UINT32 tconsel;
} s3c24xx_lcd_regs_t;
};
typedef struct
struct s3c24xx_lcdpal_regs_t
{
UINT32 data[0x400/4];
} s3c24xx_lcdpal_regs_t;
};
typedef struct
struct s3c24xx_nand_regs_t
{
UINT32 nfconf;
UINT32 nfcont;
@ -618,14 +618,14 @@ typedef struct
UINT32 nfsecc;
UINT32 nfsblk;
UINT32 nfeblk;
} s3c24xx_nand_regs_t;
};
typedef struct
struct s3c24xx_cam_regs_t
{
UINT32 data[0xA4/4];
} s3c24xx_cam_regs_t;
};
typedef struct
struct s3c24xx_uart_regs_t
{
UINT32 ulcon;
UINT32 ucon;
@ -638,9 +638,9 @@ typedef struct
UINT32 utxh;
UINT32 urxh;
UINT32 ubrdiv;
} s3c24xx_uart_regs_t;
};
typedef struct
struct s3c24xx_pwm_regs_t
{
UINT32 tcfg0;
UINT32 tcfg1;
@ -659,39 +659,39 @@ typedef struct
UINT32 tcnto3;
UINT32 tcntb4;
UINT32 tcnto4;
} s3c24xx_pwm_regs_t;
};
typedef struct
struct s3c24xx_usbdev_regs_t
{
UINT32 data[0x130/4];
} s3c24xx_usbdev_regs_t;
};
typedef struct
struct s3c24xx_wdt_regs_t
{
UINT32 wtcon;
UINT32 wtdat;
UINT32 wtcnt;
} s3c24xx_wdt_regs_t;
};
typedef struct
struct s3c24xx_iic_regs_t
{
UINT32 iiccon;
UINT32 iicstat;
UINT32 iicadd;
UINT32 iicds;
UINT32 iiclc;
} s3c24xx_iic_regs_t;
};
typedef struct
struct s3c24xx_iis_regs_t
{
UINT32 iiscon;
UINT32 iismod;
UINT32 iispsr;
UINT32 iisfcon;
UINT32 iisfifo;
} s3c24xx_iis_regs_t;
};
typedef struct
struct s3c24xx_gpio_regs_t
{
UINT32 gpacon;
UINT32 gpadat;
@ -748,9 +748,9 @@ typedef struct
UINT32 gpjcon;
UINT32 gpjdat;
UINT32 gpjup;
} s3c24xx_gpio_regs_t;
};
typedef struct
struct s3c24xx_rtc_regs_t
{
UINT32 rtccon;
UINT32 ticnt;
@ -770,9 +770,9 @@ typedef struct
UINT32 bcddow;
UINT32 bcdmon;
UINT32 bcdyear;
} s3c24xx_rtc_regs_t;
};
typedef struct
struct s3c24xx_adc_regs_t
{
UINT32 adccon;
UINT32 adctsc;
@ -780,9 +780,9 @@ typedef struct
UINT32 adcdat0;
UINT32 adcdat1;
UINT32 adcupdn;
} s3c24xx_adc_regs_t;
};
typedef struct
struct s3c24xx_spi_regs_t
{
UINT32 spcon;
UINT32 spsta;
@ -790,46 +790,46 @@ typedef struct
UINT32 sppre;
UINT32 sptdat;
UINT32 sprdat;
} s3c24xx_spi_regs_t;
};
typedef struct
struct s3c24xx_sdi_regs_t
{
UINT32 data[0x44/4];
} s3c24xx_sdi_regs_t;
};
typedef struct
struct s3c24xx_ac97_regs_t
{
UINT32 data[0x20/4];
} s3c24xx_ac97_regs_t;
};
typedef struct
struct s3c24xx_memcon_t
{
s3c24xx_memcon_regs_t regs;
} s3c24xx_memcon_t;
};
typedef struct
struct s3c24xx_usbhost_t
{
s3c24xx_usbhost_regs_t regs;
} s3c24xx_usbhost_t;
};
typedef struct
struct s3c24xx_irq_t
{
s3c24xx_irq_regs_t regs;
int line_irq, line_fiq;
} s3c24xx_irq_t;
};
typedef struct
struct s3c24xx_dma_t
{
s3c24xx_dma_regs_t regs;
emu_timer *timer;
} s3c24xx_dma_t;
};
typedef struct
struct s3c24xx_clkpow_t
{
s3c24xx_clkpow_regs_t regs;
} s3c24xx_clkpow_t;
};
typedef struct
struct s3c24xx_lcd_t
{
s3c24xx_lcd_regs_t regs;
emu_timer *timer;
@ -846,99 +846,99 @@ typedef struct
UINT32 tpal;
UINT32 hpos_min, hpos_max, vpos_min, vpos_max;
UINT32 dma_data, dma_bits;
} s3c24xx_lcd_t;
};
typedef struct
struct s3c24xx_lcdpal_t
{
s3c24xx_lcdpal_regs_t regs;
} s3c24xx_lcdpal_t;
};
typedef struct
struct s3c24xx_nand_t
{
s3c24xx_nand_regs_t regs;
UINT8 mecc[4];
UINT8 secc[2];
int ecc_pos, data_count;
} s3c24xx_nand_t;
};
typedef struct
struct s3c24xx_cam_t
{
s3c24xx_cam_regs_t regs;
} s3c24xx_cam_t;
};
typedef struct
struct s3c24xx_uart_t
{
s3c24xx_uart_regs_t regs;
} s3c24xx_uart_t;
};
typedef struct
struct s3c24xx_pwm_t
{
s3c24xx_pwm_regs_t regs;
emu_timer *timer[5];
UINT32 cnt[5];
UINT32 cmp[5];
UINT32 freq[5];
} s3c24xx_pwm_t;
};
typedef struct
struct s3c24xx_usbdev_t
{
s3c24xx_usbdev_regs_t regs;
} s3c24xx_usbdev_t;
};
typedef struct
struct s3c24xx_wdt_t
{
s3c24xx_wdt_regs_t regs;
emu_timer *timer;
} s3c24xx_wdt_t;
};
typedef struct
struct s3c24xx_iic_t
{
s3c24xx_iic_regs_t regs;
emu_timer *timer;
int count;
} s3c24xx_iic_t;
};
typedef struct
struct s3c24xx_iis_t
{
s3c24xx_iis_regs_t regs;
emu_timer *timer;
UINT16 fifo[16/2];
int fifo_index;
} s3c24xx_iis_t;
};
typedef struct
struct s3c24xx_gpio_t
{
s3c24xx_gpio_regs_t regs;
} s3c24xx_gpio_t;
};
typedef struct
struct s3c24xx_rtc_t
{
s3c24xx_rtc_regs_t regs;
emu_timer *timer_tick_count;
emu_timer *timer_update;
} s3c24xx_rtc_t;
};
typedef struct
struct s3c24xx_adc_t
{
s3c24xx_adc_regs_t regs;
} s3c24xx_adc_t;
};
typedef struct
struct s3c24xx_spi_t
{
s3c24xx_spi_regs_t regs;
} s3c24xx_spi_t;
};
typedef struct
struct s3c24xx_sdi_t
{
s3c24xx_sdi_regs_t regs;
} s3c24xx_sdi_t;
};
typedef struct
struct s3c24xx_ac97_t
{
s3c24xx_ac97_regs_t regs;
} s3c24xx_ac97_t;
};
typedef struct
struct s3c24xx_t
{
const s3c2440_interface *iface;
UINT8 steppingstone[4*1024];
@ -963,6 +963,6 @@ typedef struct
s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
s3c24xx_sdi_t sdi;
s3c24xx_ac97_t ac97;
} s3c24xx_t;
};
#endif

4
src/emu/machine/scsibus.h
View File

@ -100,7 +100,7 @@
#define SCSI_SENSE_SIZE 4
typedef struct
struct adaptec_sense_t
{
// parameter list
UINT8 reserved1[3];
@ -121,7 +121,7 @@ typedef struct
UINT8 step_pulse_code;
UINT8 bit_flags;
UINT8 sectors_per_track;
} adaptec_sense_t;
};
class scsibus_device : public device_t
{

4
src/emu/machine/v3021.h
View File

@ -27,10 +27,10 @@
// TYPE DEFINITIONS
//**************************************************************************
typedef struct
struct rtc_regs_t
{
UINT8 sec, min, hour, day, wday, month, year;
} rtc_regs_t;
};
// ======================> v3021_device

4
src/emu/sound/c140.c
View File

@ -65,7 +65,7 @@ struct voice_registers
UINT8 reserved[4];
};
typedef struct
struct VOICE
{
long ptoffset;
long pos;
@ -84,7 +84,7 @@ typedef struct
long sample_start;
long sample_end;
long sample_loop;
} VOICE;
};
struct c140_state
{

4
src/emu/sound/c352.h
View File

@ -63,7 +63,7 @@ private:
C352_FLG_REVERSE = 0x0001, // play sample backwards
};
typedef struct
struct c352_ch_t
{
UINT8 vol_l;
UINT8 vol_r;
@ -83,7 +83,7 @@ private:
UINT16 repeat;
UINT32 current_addr;
UINT32 pos;
} c352_ch_t;
};
c352_ch_t m_c352_ch[32];
int m_sample_rate_base;

8
src/emu/sound/c6280.c
View File

@ -56,7 +56,7 @@
#include "emu.h"
#include "c6280.h"
typedef struct {
struct t_channel {
UINT16 frequency;
UINT8 control;
UINT8 balance;
@ -66,9 +66,9 @@ typedef struct {
UINT8 noise_control;
UINT32 noise_counter;
UINT32 counter;
} t_channel;
};
typedef struct {
struct c6280_t {
sound_stream *stream;
device_t *device;
device_t *cpudevice;
@ -80,7 +80,7 @@ typedef struct {
INT16 volume_table[32];
UINT32 noise_freq_tab[32];
UINT32 wave_freq_tab[4096];
} c6280_t;
};
INLINE c6280_t *get_safe_token(device_t *device)
{

4
src/emu/sound/digitalk.c
View File

@ -237,7 +237,7 @@ complete set of waveforms is repeated R times.
*/
typedef struct {
struct digitalker {
const UINT8 *rom;
device_t *device;
sound_stream *stream;
@ -258,7 +258,7 @@ typedef struct {
UINT8 dac_index; // 128 for done
INT16 dac[128];
} digitalker;
};
// Quantized intensity values, first index is the volume, second the
// intensity (positive half only, real value goes -8..7)

8
src/emu/sound/discrete.c
View File

@ -83,20 +83,20 @@ const device_type DISCRETE = &device_creator<discrete_sound_device>;
*
*************************************/
typedef struct
struct output_buffer
{
double *node_buf;
const double *source;
volatile double *ptr;
int node_num;
} output_buffer;
};
typedef struct
struct input_buffer
{
volatile const double *ptr; /* pointer into linked_outbuf.nodebuf */
output_buffer * linked_outbuf; /* what output are we connected to ? */
double buffer; /* input[] will point here */
} input_buffer;
};
class discrete_task
{

4
src/emu/sound/es5503.h
View File

@ -67,7 +67,7 @@ private:
MODE_SWAP = 3
};
typedef struct
struct ES5503Osc
{
UINT16 freq;
UINT16 wtsize;
@ -80,7 +80,7 @@ private:
UINT32 accumulator;
UINT8 irqpend;
} ES5503Osc;
};
ES5503Osc oscillators[32];

32
src/emu/sound/fm.c
View File

@ -519,7 +519,7 @@ static FILE *sample[1];
/* struct describing a single operator (SLOT) */
typedef struct
struct FM_SLOT
{
INT32 *DT; /* detune :dt_tab[DT] */
UINT8 KSR; /* key scale rate :3-KSR */
@ -558,9 +558,9 @@ typedef struct
/* LFO */
UINT32 AMmask; /* AM enable flag */
} FM_SLOT;
};
typedef struct
struct FM_CH
{
FM_SLOT SLOT[4]; /* four SLOTs (operators) */
@ -582,10 +582,10 @@ typedef struct
UINT32 fc; /* fnum,blk:adjusted to sample rate */
UINT8 kcode; /* key code: */
UINT32 block_fnum; /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
} FM_CH;
};
typedef struct
struct FM_ST
{
device_t *device;
void * param; /* this chip parameter */
@ -613,7 +613,7 @@ typedef struct
FM_TIMERHANDLER timer_handler;
FM_IRQHANDLER IRQ_Handler;
const ssg_callbacks *SSG;
} FM_ST;
};
@ -622,16 +622,16 @@ typedef struct
/***********************************************************/
/* OPN 3slot struct */
typedef struct
struct FM_3SLOT
{
UINT32 fc[3]; /* fnum3,blk3: calculated */
UINT8 fn_h; /* freq3 latch */
UINT8 kcode[3]; /* key code */
UINT32 block_fnum[3]; /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
} FM_3SLOT;
};
/* OPN/A/B common state */
typedef struct
struct FM_OPN
{
UINT8 type; /* chip type */
FM_ST ST; /* general state */
@ -669,7 +669,7 @@ typedef struct
INT32 out_adpcm[4]; /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 ADPCM */
INT32 out_delta[4]; /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 DELTAT*/
#endif
} FM_OPN;
};
@ -2089,12 +2089,12 @@ static void OPNPrescaler_w(FM_OPN *OPN , int addr, int pre_divider)
/*****************************************************************************/
/* here's the virtual YM2203(OPN) */
typedef struct
struct YM2203
{
UINT8 REGS[256]; /* registers */
FM_OPN OPN; /* OPN state */
FM_CH CH[3]; /* channel state */
} YM2203;
};
/* Generate samples for one of the YM2203s */
void ym2203_update_one(void *chip, FMSAMPLE *buffer, int length)
@ -2385,7 +2385,7 @@ int ym2203_timer_over(void *chip,int c)
#if (BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B)
/* ADPCM type A channel struct */
typedef struct
struct ADPCM_CH
{
UINT8 flag; /* port state */
UINT8 flagMask; /* arrived flag mask */
@ -2402,10 +2402,10 @@ typedef struct
INT8 vol_mul; /* volume in "0.75dB" steps */
UINT8 vol_shift; /* volume in "-6dB" steps */
INT32 *pan; /* &out_adpcm[OPN_xxxx] */
} ADPCM_CH;
};
/* here's the virtual YM2610 */
typedef struct
struct YM2610
{
UINT8 REGS[512]; /* registers */
FM_OPN OPN; /* OPN state */
@ -2423,7 +2423,7 @@ typedef struct
UINT8 flagmask; /* YM2608 only */
UINT8 irqmask; /* YM2608 only */
} YM2610;
};
/* here is the virtual YM2608 */
typedef YM2610 YM2608;

24
src/emu/sound/fm2612.c
View File

@ -531,7 +531,7 @@ static FILE *sample[1];
/* struct describing a single operator (SLOT) */
typedef struct
struct FM_SLOT
{
INT32 *DT; /* detune :dt_tab[DT] */
UINT8 KSR; /* key scale rate :3-KSR */
@ -570,9 +570,9 @@ typedef struct
/* LFO */
UINT32 AMmask; /* AM enable flag */
} FM_SLOT;
};
typedef struct
struct FM_CH
{
FM_SLOT SLOT[4]; /* four SLOTs (operators) */
@ -594,10 +594,10 @@ typedef struct
UINT32 fc; /* fnum,blk:adjusted to sample rate */
UINT8 kcode; /* key code: */
UINT32 block_fnum; /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
} FM_CH;
};
typedef struct
struct FM_ST
{
device_t *device;
void * param; /* this chip parameter */
@ -625,7 +625,7 @@ typedef struct
FM_TIMERHANDLER timer_handler;
FM_IRQHANDLER IRQ_Handler;
const ssg_callbacks *SSG;
} FM_ST;
};
@ -634,17 +634,17 @@ typedef struct
/***********************************************************/
/* OPN 3slot struct */
typedef struct
struct FM_3SLOT
{
UINT32 fc[3]; /* fnum3,blk3: calculated */
UINT8 fn_h; /* freq3 latch */
UINT8 kcode[3]; /* key code */
UINT32 block_fnum[3]; /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
UINT8 key_csm; /* CSM mode Key-ON flag */
} FM_3SLOT;
};
/* OPN/A/B common state */
typedef struct
struct FM_OPN
{
UINT8 type; /* chip type */
FM_ST ST; /* general state */
@ -675,10 +675,10 @@ typedef struct
INT32 mem; /* one sample delay memory */
INT32 out_fm[8]; /* outputs of working channels */
} FM_OPN;
};
/* here's the virtual YM2612 */
typedef struct
struct YM2612
{
UINT8 REGS[512]; /* registers */
FM_OPN OPN; /* OPN state */
@ -688,7 +688,7 @@ typedef struct
/* dac output (YM2612) */
int dacen;
INT32 dacout;
} YM2612;
};
/* log output level */
#define LOG_ERR 3 /* ERROR */

12
src/emu/sound/fmopl.c
View File

@ -198,7 +198,7 @@ static FILE * cymfile = NULL;
typedef struct
struct OPL_SLOT
{
UINT32 ar; /* attack rate: AR<<2 */
UINT32 dr; /* decay rate: DR<<2 */
@ -237,9 +237,9 @@ typedef struct
/* waveform select */
UINT16 wavetable;
} OPL_SLOT;
};
typedef struct
struct OPL_CH
{
OPL_SLOT SLOT[2];
/* phase generator state */
@ -247,10 +247,10 @@ typedef struct
UINT32 fc; /* Freq. Increment base */
UINT32 ksl_base; /* KeyScaleLevel Base step */
UINT8 kcode; /* key code (for key scaling) */
} OPL_CH;
};
/* OPL state */
typedef struct
struct FM_OPL
{
/* FM channel slots */
OPL_CH P_CH[9]; /* OPL/OPL2 chips have 9 channels*/
@ -325,7 +325,7 @@ typedef struct
#if BUILD_Y8950
INT32 output_deltat[4]; /* for Y8950 DELTA-T, chip is mono, that 4 here is just for safety */
#endif
} FM_OPL;
};

4
src/emu/sound/i5000.h
View File

@ -47,7 +47,7 @@ protected:
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
private:
typedef struct
struct channel_t
{
bool is_playing;
oki_adpcm_state m_adpcm;
@ -65,7 +65,7 @@ private:
int output_r;
int output_l;
} channel_t;
};
channel_t m_channels[16];

4
src/emu/sound/k005289.c
View File

@ -31,13 +31,13 @@
#define FREQBASEBITS 16
/* this structure defines the parameters for a channel */
typedef struct
struct k005289_sound_channel
{
int frequency;
int counter;
int volume;
const unsigned char *wave;
} k005289_sound_channel;
};
struct k005289_state
{

4
src/emu/sound/k051649.c
View File

@ -30,14 +30,14 @@
/* this structure defines the parameters for a channel */
typedef struct
struct k051649_sound_channel
{
unsigned long counter;
int frequency;
int volume;
int key;
signed char waveram[32];
} k051649_sound_channel;
};
struct k051649_state
{

8
src/emu/sound/msm5232.c
View File

@ -9,7 +9,7 @@
8 channel tone generator
*/
typedef struct {
struct VOICE {
UINT8 mode;
int TG_count_period;
@ -35,10 +35,10 @@ typedef struct {
int pitch; /* current pitch data */
int GF;
} VOICE;
};
typedef struct {
struct msm5232_state {
sound_stream *stream;
VOICE voi[8];
@ -71,7 +71,7 @@ typedef struct {
device_t *device;
void (*gate_handler)(device_t *device, int state); /* callback called when the GATE output pin changes state */
} msm5232_state;
};
INLINE msm5232_state *get_safe_token(device_t *device)

4
src/emu/sound/n63701x.c
View File

@ -17,7 +17,7 @@ silence compression: '00 nn' must be replaced by nn+1 times '80'.
#include "n63701x.h"
typedef struct
struct voice
{
int select;
int playing;
@ -25,7 +25,7 @@ typedef struct
int position;
int volume;
int silence_counter;
} voice;
};
struct namco_63701x

4
src/emu/sound/namco.c
View File

@ -36,7 +36,7 @@
/* this structure defines the parameters for a channel */
typedef struct
struct sound_channel
{
UINT32 frequency;
UINT32 counter;
@ -47,7 +47,7 @@ typedef struct
UINT32 noise_counter;
INT32 noise_hold;
INT32 waveform_select;
} sound_channel;
};
struct namco_sound

4
src/emu/sound/s14001a.c
View File

@ -237,7 +237,7 @@ and off as it normally does during speech). Once START has gone low-high-low, th
#include "emu.h"
#include "s14001a.h"
typedef struct
struct S14001AChip
{
sound_stream * stream;
@ -262,7 +262,7 @@ typedef struct
UINT8 *SpeechRom; // array to hold rom contents, mame will not need this, will use a pointer
INT16 filtervals[8];
UINT8 VSU1000_amp; // amplitude setting on VSU-1000 board
} S14001AChip;
};
INLINE S14001AChip *get_safe_token(device_t *device)
{

4
src/emu/sound/x1_010.c
View File

@ -67,7 +67,7 @@ Registers:
#define VOL_BASE (2*32*256/30) // Volume base
/* this structure defines the parameters for a channel */
typedef struct {
struct X1_010_CHANNEL {
unsigned char status;
unsigned char volume; // volume / wave form no.
unsigned char frequency; // frequency / pitch lo
@ -75,7 +75,7 @@ typedef struct {
unsigned char start; // start address / envelope time
unsigned char end; // end address / envelope no.
unsigned char reserve[2];
} X1_010_CHANNEL;
};
struct x1_010_state
{

8
src/emu/sound/ym2151.c
View File

@ -23,7 +23,7 @@ static FILE * cymfile = NULL;
/* struct describing a single operator */
typedef struct
struct YM2151Operator
{
UINT32 phase; /* accumulated operator phase */
UINT32 freq; /* operator frequency count */
@ -73,10 +73,10 @@ typedef struct
UINT32 reserved0; /**/
UINT32 reserved1; /**/
} YM2151Operator;
};
typedef struct
struct YM2151
{
signed int chanout[8];
signed int m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
@ -168,7 +168,7 @@ typedef struct
device_t *device;
unsigned int clock; /* chip clock in Hz (passed from 2151intf.c) */
unsigned int sampfreq; /* sampling frequency in Hz (passed from 2151intf.c) */
} YM2151;
};
#define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */

12
src/emu/sound/ym2413.c
View File

@ -164,7 +164,7 @@ static FILE * cymfile = NULL;
typedef struct
struct OPLL_SLOT
{
UINT32 ar; /* attack rate: AR<<2 */
UINT32 dr; /* decay rate: DR<<2 */
@ -207,9 +207,9 @@ typedef struct
/* waveform select */
unsigned int wavetable;
} OPLL_SLOT;
};
typedef struct
struct OPLL_CH
{
OPLL_SLOT SLOT[2];
/* phase generator state */
@ -218,10 +218,10 @@ typedef struct
UINT32 ksl_base; /* KeyScaleLevel Base step */
UINT8 kcode; /* key code (for key scaling) */
UINT8 sus; /* sus on/off (release speed in percussive mode)*/
} OPLL_CH;
};
/* chip state */
typedef struct
struct YM2413
{
OPLL_CH P_CH[9]; /* OPLL chips have 9 channels*/
UINT8 instvol_r[9]; /* instrument/volume (or volume/volume in percussive mode)*/
@ -272,7 +272,7 @@ typedef struct
signed int output[2];
signed int outchan;
} YM2413;
};
/* key scale level */
/* table is 3dB/octave, DV converts this into 6dB/octave */

12
src/emu/sound/ymf262.c
View File

@ -141,7 +141,7 @@ static FILE * cymfile = NULL;
#define OPL3_TYPE_YMF262 (0) /* 36 operators, 8 waveforms */
typedef struct
struct OPL3_SLOT
{
UINT32 ar; /* attack rate: AR<<2 */
UINT32 dr; /* decay rate: DR<<2 */
@ -190,9 +190,9 @@ typedef struct
//unsigned char reserved[128-84];//speedup: pump up the struct size to power of 2
unsigned char reserved[128-100];//speedup: pump up the struct size to power of 2
} OPL3_SLOT;
};
typedef struct
struct OPL3_CH
{
OPL3_SLOT SLOT[2];
@ -215,10 +215,10 @@ typedef struct
unsigned char reserved[512-272];//speedup:pump up the struct size to power of 2
} OPL3_CH;
};
/* OPL3 state */
typedef struct
struct OPL3
{
OPL3_CH P_CH[18]; /* OPL3 chips have 18 channels */
@ -278,7 +278,7 @@ typedef struct
double freqbase; /* frequency base */
attotime TimerBase; /* Timer base time (==sampling time)*/
device_t *device;
} OPL3;
};

12
src/emu/sound/ymf271.c
View File

@ -33,7 +33,7 @@
//#define log2(n) (log((float) n)/log((float) 2))
typedef struct
struct YMF271Slot
{
INT8 extout;
UINT8 lfoFreq;
@ -80,14 +80,14 @@ typedef struct
INT32 lfo_phase, lfo_step;
INT32 lfo_amplitude;
double lfo_phasemod;
} YMF271Slot;
};
typedef struct
struct YMF271Group
{
INT8 sync, pfm;
} YMF271Group;
};
typedef struct
struct YMF271Chip
{
YMF271Slot slots[48];
YMF271Group groups[12];
@ -112,7 +112,7 @@ typedef struct
UINT32 clock;
sound_stream * stream;
device_t *device;
} YMF271Chip;
};
// slot mapping assists
static const int fm_tab[] = { 0, 1, 2, -1, 3, 4, 5, -1, 6, 7, 8, -1, 9, 10, 11, -1 };

4
src/emu/sound/ymf278b.c
View File

@ -71,7 +71,7 @@
#define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
typedef struct
struct YMF278BSlot
{
INT16 wave; /* wavetable number */
INT16 F_NUMBER; /* frequency */
@ -111,7 +111,7 @@ typedef struct
int num; /* slot number (for debug only) */
struct _YMF278BChip *chip; /* pointer back to parent chip */
} YMF278BSlot;
};
typedef struct _YMF278BChip
{

4
src/emu/sound/ymz770.h
View File

@ -34,7 +34,7 @@ class amm;
class ymz770_device : public device_t, public device_sound_interface
{
typedef struct
struct ymz_channel
{
UINT8 phrase;
UINT8 pan;
@ -55,7 +55,7 @@ class ymz770_device : public device_t, public device_sound_interface
UINT8 *seqdata;
bool is_seq_playing;
} ymz_channel;
};
public:

4
src/emu/video/rgbgen.h
View File

@ -18,10 +18,10 @@
***************************************************************************/
/* intermediate RGB values are stored in a struct */
typedef struct { INT16 dummy, r, g, b; } rgbint;
struct rgbint { INT16 dummy, r, g, b; };
/* intermediate RGB values are stored in a struct */
typedef struct { INT16 a, r, g, b; } rgbaint;
struct rgbaint { INT16 a, r, g, b; };

4
src/emu/video/vector.c
View File

@ -127,14 +127,14 @@ static render_texture *get_vector_texture(float dx, float dy, float intensity)
#define VCLIP 2
/* The vertices are buffered here */
typedef struct
struct point
{
int x; int y;
rgb_t col;
int intensity;
int arg1; int arg2; /* start/end in pixel array or clipping info */
int status; /* for dirty and clipping handling */
} point;
};

4
src/lib/formats/ace_tap.h
View File

@ -11,7 +11,7 @@
#include "cassimg.h"
typedef struct
struct ace_tape_t
{
UINT8 hdr_type;
UINT8 hdr_name[10];
@ -21,7 +21,7 @@ typedef struct
UINT8 hdr_3c4c;
UINT8 hdr_3c4d;
UINT16 dat_len;
} ace_tape_t;
};
CASSETTE_FORMATLIST_EXTERN(ace_cassette_formats);

4
src/mame/audio/cage.c
View File

@ -34,7 +34,7 @@
*************************************/
typedef struct
struct cage_t
{
cpu_device *cpu;
attotime cpu_h1_clock_period;
@ -59,7 +59,7 @@ typedef struct
UINT32 *speedup_ram;
dmadac_sound_device *dmadac[DAC_BUFFER_CHANNELS];
} cage_t;
};
static cage_t cage;

4
src/mame/audio/exidy440.c
View File

@ -71,7 +71,7 @@ typedef struct sound_cache_entry
typedef struct
struct exidy440_audio_state
{
UINT8 sound_command;
UINT8 sound_command_ack;
@ -100,7 +100,7 @@ typedef struct
/* channel frequency is configurable */
int channel_frequency[4];
} exidy440_audio_state;
};
/* constant channel parameters */
static const int channel_bits[4] =

4
src/mame/audio/flower.c
View File

@ -20,7 +20,7 @@ TODO:
/* this structure defines the parameters for a channel */
typedef struct
struct sound_channel
{
UINT32 start;
UINT32 pos;
@ -32,7 +32,7 @@ typedef struct
UINT8 effect;
UINT32 ecount;
} sound_channel;
};
struct flower_sound_state

4
src/mame/audio/gomoku.c
View File

@ -19,14 +19,14 @@ static const int defgain = 48;
/* this structure defines the parameters for a channel */
typedef struct
struct sound_channel
{
int channel;
int frequency;
int counter;
int volume;
int oneshotplaying;
} sound_channel;
};
struct gomoku_sound_state

4
src/mame/audio/wiping.c
View File

@ -19,7 +19,7 @@ static const int defgain = 48;
/* this structure defines the parameters for a channel */
typedef struct
struct sound_channel
{
int frequency;
int counter;
@ -27,7 +27,7 @@ typedef struct
const UINT8 *wave;
int oneshot;
int oneshotplaying;
} sound_channel;
};

12
src/mame/drivers/firebeat.c
View File

@ -121,25 +121,25 @@
#include "firebeat.lh"
typedef struct
struct GCU_REGS
{
UINT32 *vram;
UINT32 vram_read_address;
UINT32 vram_write_fifo_address;
UINT32 visible_area;
} GCU_REGS;
};
typedef struct
struct IBUTTON_SUBKEY
{
UINT8 identifier[8];
UINT8 password[8];
UINT8 data[0x30];
} IBUTTON_SUBKEY;
};
typedef struct
struct IBUTTON
{
IBUTTON_SUBKEY subkey[3];
} IBUTTON;
};

4
src/mame/drivers/konamigx.c
View File

@ -3660,14 +3660,14 @@ MACHINE_RESET_MEMBER(konamigx_state,konamigx)
}
}
typedef struct
struct GXGameInfoT
{
const char *romname;
UINT32 cfgport;
UINT32 sndhack;
UINT32 special;
UINT32 readback;
} GXGameInfoT;
};
#define BPP4 0
#define BPP5 1

4
src/mame/drivers/konamim2.c
View File

@ -191,14 +191,14 @@ Notes:
#include "cpu/powerpc/ppc.h"
typedef struct
struct CDE_DMA
{
UINT32 dst_addr;
int length;
UINT32 next_dst_addr;
int next_length;
int dma_done;
} CDE_DMA;
};
class konamim2_state : public driver_device
{

8
src/mame/drivers/maygayv1.c
View File

@ -193,16 +193,16 @@ static const UINT32 banks[4] = { 0, 0x40000/2, 0x20000/2, 0x60000/2 };
#define DRAM_BANK_SEL (banks[(VREG(DSBA) >> 7) & 3])
typedef struct
struct i82716_t
{
UINT16 r[16];
UINT16 *dram;
UINT8 *line_buf; // there's actually two
} i82716_t;
};
typedef struct
struct i8279_t
{
UINT8 command;
UINT8 mode;
@ -211,7 +211,7 @@ typedef struct
UINT8 clear;
UINT8 fifo[8];
UINT8 ram[16];
} i8279_t;
};
class maygayv1_state : public driver_device
{

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