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netlist: Fix cmos power pins and gcc-9 error.

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CMOS 40xx and 4316 power pins fixed.
Also fixed gcc-9 error. clang++ complains about unreachable code in
nl_base.cpp line 480 even if double parantheses are used. Assigning the
define to a local variable and testing this local variable works. Weird.
This commit is contained in:
couriersud 2019-05-05 21:40:28 +02:00
parent bc36147c95
commit d0270fa161
10 changed files with 59 additions and 43 deletions
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11
src/lib/netlist/devices/nld_4020.cpp
View File

@ -5,8 +5,9 @@
*
*/
#include "nlid_cmos.h"
//#include "nlid_cmos.h"
#include "nld_4020.h"
#include "nlid_system.h"
namespace netlist
{
@ -20,6 +21,7 @@ namespace netlist
, m_Q(*this, {{"Q1", "_Q2", "_Q3", "Q4", "Q5", "Q6", "Q7", "Q8", "Q9",
"Q10", "Q11", "Q12", "Q13", "Q14"}})
, m_cnt(*this, "m_cnt", 0)
, m_supply(*this, "VDD", "VSS")
{
}
@ -38,6 +40,7 @@ namespace netlist
object_array_t<logic_output_t, 14> m_Q;
state_var<unsigned> m_cnt;
nld_power_pins m_supply;
};
NETLIB_OBJECT(CD4020)
@ -45,7 +48,6 @@ namespace netlist
NETLIB_CONSTRUCTOR(CD4020)
NETLIB_FAMILY("CD4XXX")
, m_sub(*this, "sub")
, m_supply(*this, "supply")
, m_RESET(*this, "RESET")
{
register_subalias("IP", m_sub.m_IP);
@ -61,15 +63,14 @@ namespace netlist
register_subalias("Q12", m_sub.m_Q[11]);
register_subalias("Q13", m_sub.m_Q[12]);
register_subalias("Q14", m_sub.m_Q[13]);
register_subalias("VDD", m_supply.m_vdd);
register_subalias("VSS", m_supply.m_vss);
register_subalias("VDD", "sub.VDD");
register_subalias("VSS", "sub.VSS");
}
NETLIB_RESETI() { }
NETLIB_UPDATEI();
private:
NETLIB_SUB(CD4020_sub) m_sub;
NETLIB_SUB(vdd_vss) m_supply;
logic_input_t m_RESET;
};

10
src/lib/netlist/devices/nld_4066.cpp
View File

@ -9,7 +9,7 @@
#include "netlist/analog/nlid_twoterm.h"
#include "netlist/solver/nld_solver.h"
#include "nlid_cmos.h"
#include "nlid_system.h"
namespace netlist
{
@ -19,7 +19,7 @@ namespace netlist
{
NETLIB_CONSTRUCTOR(CD4066_GATE)
NETLIB_FAMILY("CD4XXX")
, m_supply(*this, "PS")
, m_supply(*this, "VDD", "VSS", true)
, m_R(*this, "R")
, m_control(*this, "CTL")
, m_base_r(*this, "BASER", 270.0)
@ -30,7 +30,7 @@ namespace netlist
NETLIB_UPDATEI();
private:
NETLIB_SUB(vdd_vss) m_supply;
nld_power_pins m_supply;
analog::NETLIB_SUB(R_base) m_R;
analog_input_t m_control;
@ -47,10 +47,10 @@ namespace netlist
NETLIB_UPDATE(CD4066_GATE)
{
nl_double sup = (m_supply.vdd() - m_supply.vss());
nl_double sup = (m_supply.VCC() - m_supply.GND());
nl_double low = plib::constants<nl_double>::cast(0.45) * sup;
nl_double high = plib::constants<nl_double>::cast(0.55) * sup;
nl_double in = m_control() - m_supply.vss();
nl_double in = m_control() - m_supply.GND();
nl_double rON = m_base_r() * plib::constants<nl_double>::cast(5.0) / sup;
nl_double R = -1.0;

2
src/lib/netlist/devices/nld_4066.h
View File

@ -26,6 +26,8 @@
#include "netlist/nl_setup.h"
// FIXME: Implement pure CMOS version
#define CD4066_GATE(name) \
NET_REGISTER_DEV(CD4066_GATE, name)

6
src/lib/netlist/devices/nld_4316.cpp
View File

@ -8,7 +8,7 @@
#include "nld_4316.h"
#include "netlist/analog/nlid_twoterm.h"
#include "netlist/solver/nld_solver.h"
#include "nlid_cmos.h"
#include "nlid_system.h"
namespace netlist { namespace devices {
@ -16,7 +16,7 @@ namespace netlist { namespace devices {
{
NETLIB_CONSTRUCTOR(CD4316_GATE)
NETLIB_FAMILY("CD4XXX")
, m_supply(*this, "PS")
, m_supply(*this, "VDD", "VSS")
, m_R(*this, "_R")
, m_S(*this, "S")
, m_E(*this, "E")
@ -28,7 +28,7 @@ namespace netlist { namespace devices {
NETLIB_UPDATEI();
public:
NETLIB_SUB(vdd_vss) m_supply;
nld_power_pins m_supply;
analog::NETLIB_SUB(R_base) m_R;
logic_input_t m_S;

2
src/lib/netlist/devices/nld_4316.h
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Vas Crabb
/*
* nld_4136.h
* nld_4316.h
*
* CD4066: Quad Analog Switch with Level Translation
*

21
src/lib/netlist/devices/nlid_system.h
View File

@ -428,15 +428,19 @@ namespace devices
// power pins - not a device, but a helper
// -----------------------------------------------------------------------------
/**
* Power Pins are passive inputs. Delegate noop will silently ignore any
* updates.
*/
class nld_power_pins
{
public:
nld_power_pins(device_t &owner, const char *sVCC = "VCC", const char *sGND = "GND")
nld_power_pins(device_t &owner, const char *sVCC = "VCC", const char *sGND = "GND", bool force_analog_input = false)
{
if (owner.setup().is_validation())
if (owner.setup().is_validation() || force_analog_input)
{
m_GND = plib::make_unique<analog_input_t>(owner, sGND);
m_VCC = plib::make_unique<analog_input_t>(owner, sVCC);
m_GND = plib::make_unique<analog_input_t>(owner, sGND, NETLIB_DELEGATE(power_pins, noop));
m_VCC = plib::make_unique<analog_input_t>(owner, sVCC, NETLIB_DELEGATE(power_pins, noop));
}
else
{
@ -446,11 +450,16 @@ namespace devices
}
}
/* FIXME: this will seg-fault if force_analog_input = false */
nl_double VCC() const NL_NOEXCEPT { return m_VCC->Q_Analog(); }
nl_double GND() const NL_NOEXCEPT { return m_GND->Q_Analog(); }
NETLIB_SUBXX(analog, R) m_RVG; // dummy resistor between VCC and GND
private:
plib::unique_ptr<analog_input_t> m_VCC; // only used during validation
plib::unique_ptr<analog_input_t> m_GND; // only used during validation
void noop() { }
plib::unique_ptr<analog_input_t> m_VCC; // only used during validation or force_analog_input
plib::unique_ptr<analog_input_t> m_GND; // only used during validation or force_analog_input
};
} //namespace devices

24
src/lib/netlist/macro/nlm_cd4xxx.cpp
View File

@ -107,8 +107,8 @@ static NETLIST_START(CD4066_DIP)
CD4066_GATE(C)
CD4066_GATE(D)
NET_C(A.PS.VDD, B.PS.VDD, C.PS.VDD, D.PS.VDD)
NET_C(A.PS.VSS, B.PS.VSS, C.PS.VSS, D.PS.VSS)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
PARAM(A.BASER, 270.0)
PARAM(B.BASER, 270.0)
@ -116,13 +116,13 @@ static NETLIST_START(CD4066_DIP)
PARAM(D.BASER, 270.0)
DIPPINS( /* +--------------+ */
A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD,
A.R.1, /* INOUTA |1 ++ 14| VDD */ A.VDD,
A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
B.R.2, /* INOUTB |4 4066 11| INOUTD */ D.R.1,
B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2
A.VSS, /* VSS |7 8| INOUTC */ C.R.2
/* +--------------+ */
)
NETLIST_END()
@ -133,8 +133,8 @@ static NETLIST_START(CD4016_DIP)
CD4066_GATE(C)
CD4066_GATE(D)
NET_C(A.PS.VDD, B.PS.VDD, C.PS.VDD, D.PS.VDD)
NET_C(A.PS.VSS, B.PS.VSS, C.PS.VSS, D.PS.VSS)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
PARAM(A.BASER, 1000.0)
PARAM(B.BASER, 1000.0)
@ -142,13 +142,13 @@ static NETLIST_START(CD4016_DIP)
PARAM(D.BASER, 1000.0)
DIPPINS( /* +--------------+ */
A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD,
A.R.1, /* INOUTA |1 ++ 14| VDD */ A.VDD,
A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
B.R.2, /* INOUTB |4 4016 11| INOUTD */ D.R.1,
B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2
A.VSS, /* VSS |7 8| INOUTC */ C.R.2
/* +--------------+ */
)
NETLIST_END()
@ -160,8 +160,8 @@ static NETLIST_START(CD4316_DIP)
CD4316_GATE(D)
NET_C(A.E, B.E, C.E, D.E)
NET_C(A.PS.VDD, B.PS.VDD, C.PS.VDD, D.PS.VDD)
NET_C(A.PS.VSS, B.PS.VSS, C.PS.VSS, D.PS.VSS)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
PARAM(A.BASER, 45.0)
PARAM(B.BASER, 45.0)
@ -169,14 +169,14 @@ static NETLIST_START(CD4316_DIP)
PARAM(D.BASER, 45.0)
DIPPINS( /* +--------------+ */
A.R.2, /* 1Z |1 ++ 16| VCC */ A.PS.VDD,
A.R.2, /* 1Z |1 ++ 16| VCC */ A.VDD,
A.R.1, /* 1Y |2 15| 1S */ A.S,
B.R.1, /* 2Y |3 14| 4S */ D.S,
B.R.2, /* 2Z |4 4316 13| 4Z */ D.R.2,
B.S, /* 2S |5 12| 4Y */ D.R.1,
C.S, /* 3S |6 11| 3Y */ C.R.1,
A.E, /* /E |7 10| 3Z */ C.R.2,
A.PS.VSS, /* GND |8 9| VEE */ VEE
A.VSS, /* GND |8 9| VEE */ VEE
/* +--------------+ */
)

14
src/lib/netlist/nl_base.cpp
View File

@ -477,8 +477,8 @@ void netlist_t::print_stats() const
log().verbose("Total time {1:15}", total_time);
// FIXME: clang complains about unreachable code without
const auto dummy = USE_QUEUE_STATS;
if (dummy)
const auto clang_workaround_unreachable_code = USE_QUEUE_STATS;
if (clang_workaround_unreachable_code)
{
/* Only one serialization should be counted in total time */
/* But two are contained in m_stat_mainloop */
@ -837,8 +837,9 @@ detail::core_terminal_t::core_terminal_t(core_device_t &dev, const pstring &anam
{
}
analog_t::analog_t(core_device_t &dev, const pstring &aname, const state_e state)
: core_terminal_t(dev, aname, state)
analog_t::analog_t(core_device_t &dev, const pstring &aname, const state_e state,
nldelegate delegate)
: core_terminal_t(dev, aname, state, delegate)
{
}
@ -912,8 +913,9 @@ void logic_output_t::initial(const netlist_sig_t val)
// analog_input_t
// ----------------------------------------------------------------------------------------
analog_input_t::analog_input_t(core_device_t &dev, const pstring &aname)
: analog_t(dev, aname, STATE_INP_ACTIVE)
analog_input_t::analog_input_t(core_device_t &dev, const pstring &aname,
nldelegate delegate)
: analog_t(dev, aname, STATE_INP_ACTIVE, delegate)
{
state().setup().register_term(*this);
}

8
src/lib/netlist/nl_base.h
View File

@ -755,7 +755,8 @@ namespace netlist
{
public:
analog_t(core_device_t &dev, const pstring &aname, const state_e state);
analog_t(core_device_t &dev, const pstring &aname, const state_e state,
nldelegate delegate = nldelegate());
const analog_net_t & net() const NL_NOEXCEPT;
analog_net_t & net() NL_NOEXCEPT;
@ -869,8 +870,9 @@ namespace netlist
{
public:
/*! Constructor */
analog_input_t(core_device_t &dev, /*!< owning device */
const pstring &aname /*!< name of terminal */
analog_input_t(core_device_t &dev, /*!< owning device */
const pstring &aname, /*!< name of terminal */
nldelegate delegate = nldelegate() /*!< delegate */
);
/*! returns voltage at terminal.

4
src/mame/machine/nl_breakout.cpp
View File

@ -124,8 +124,8 @@ CIRCUIT_LAYOUT( breakout )
ANALOG_INPUT(V5, 5)
ALIAS(VCC, V5)
#define GNDD "ttllow", Q
#define P "ttlhigh", Q
#define GNDD "GND", Q
#define P "V5", Q
//----------------------------------------------------------------
// Clock circuit