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r4000: intention is no longer a mask
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@ -3642,7 +3642,7 @@ r4000_base_device::translate_result r4000_base_device::translate(int intention,
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// address needs translation, using a combination of VPN2 and ASID
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u64 const key = (address & (extended ? (EH_R | EH_VPN2_64) : EH_VPN2_32)) | (m_cp0[CP0_EntryHi] & EH_ASID);
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unsigned *mru = m_tlb_mru[intention & device_vtlb_interface::TR_TYPE];
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unsigned *mru = m_tlb_mru[intention];
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if (VERBOSE & LOG_STATS)
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m_tlb_scans++;
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@ -3673,7 +3673,7 @@ r4000_base_device::translate_result r4000_base_device::translate(int intention,
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}
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// test dirty
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if ((intention & TR_WRITE) && !(pfn & EL_D))
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if ((intention == TR_WRITE) && !(pfn & EL_D))
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{
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modify = true;
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break;
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@ -3702,7 +3702,7 @@ r4000_base_device::translate_result r4000_base_device::translate(int intention,
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m_cp0[CP0_EntryHi] & EH_ASID, address, machine().describe_context());
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else
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LOGMASKED(LOG_TLB, "tlb miss %c asid 0x%02x address 0x%016x (%s)\n",
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mode[intention & device_vtlb_interface::TR_TYPE], m_cp0[CP0_EntryHi] & EH_ASID, address, machine().describe_context());
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mode[intention], m_cp0[CP0_EntryHi] & EH_ASID, address, machine().describe_context());
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}
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// load tlb exception registers
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@ -3712,9 +3712,9 @@ r4000_base_device::translate_result r4000_base_device::translate(int intention,
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m_cp0[CP0_XContext] = (m_cp0[CP0_XContext] & XCONTEXT_PTEBASE) | ((address >> 31) & XCONTEXT_R) | ((address >> 9) & XCONTEXT_BADVPN2);
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if (invalid || modify || (SR & SR_EXL))
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cpu_exception(modify ? EXCEPTION_MOD : (intention & TR_WRITE) ? EXCEPTION_TLBS : EXCEPTION_TLBL);
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cpu_exception(modify ? EXCEPTION_MOD : (intention == TR_WRITE) ? EXCEPTION_TLBS : EXCEPTION_TLBL);
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else
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cpu_exception((intention & TR_WRITE) ? EXCEPTION_TLBS : EXCEPTION_TLBL, extended ? 0x080 : 0x000);
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cpu_exception((intention == TR_WRITE) ? EXCEPTION_TLBS : EXCEPTION_TLBL, extended ? 0x080 : 0x000);
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}
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return MISS;
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@ -3730,7 +3730,7 @@ void r4000_base_device::address_error(int intention, u64 const address)
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if (!(SR & SR_EXL))
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m_cp0[CP0_BadVAddr] = address;
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cpu_exception((intention & TR_WRITE) ? EXCEPTION_ADES : EXCEPTION_ADEL);
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cpu_exception((intention == TR_WRITE) ? EXCEPTION_ADES : EXCEPTION_ADEL);
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// address errors shouldn't typically occur, so a breakpoint is handy
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machine().debug_break();
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