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vsmile: removed Unununium timing hacks, nw

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This commit is contained in:
mooglyguy 2018-10-21 21:28:55 +02:00
parent af515310d7
commit d1ec0b957c
4 changed files with 39 additions and 286 deletions
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227
src/devices/cpu/unsp/unsp.cpp
View File

@ -177,20 +177,6 @@ void unsp_device::state_import(const device_state_entry &entry)
} }
} }
static struct unsp_timer timer_tmb1 = {
.time = 0,
.interval = 27000000/8,
.index = 0,
.next = nullptr
};
static struct unsp_timer timer_tmb2 = {
.time = 0,
.interval = 27000000/128,
.index = 1,
.next = nullptr
};
void unsp_device::device_reset() void unsp_device::device_reset()
{ {
memset(m_r, 0, sizeof(uint16_t) * 16); memset(m_r, 0, sizeof(uint16_t) * 16);
@ -200,10 +186,6 @@ void unsp_device::device_reset()
m_enable_fiq = false; m_enable_fiq = false;
m_irq = false; m_irq = false;
m_fiq = false; m_fiq = false;
timers = nullptr;
timer_add(&timer_tmb1);
timer_add(&timer_tmb2);
} }
/*****************************************************************************/ /*****************************************************************************/
@ -266,10 +248,7 @@ void unsp_device::trigger_fiq()
void unsp_device::trigger_irq(int line) void unsp_device::trigger_irq(int line)
{ {
if (!m_enable_irq || m_irq || m_fiq) if (!m_enable_irq || m_irq || m_fiq)
{
//logerror("Enable %d, IRQ %d, FIQ %d, bailing\n", m_enable_irq ? 1 : 0, m_irq ? 1 : 0, m_fiq ? 1 : 0);
return; return;
}
m_irq = true; m_irq = true;
@ -282,51 +261,12 @@ void unsp_device::trigger_irq(int line)
UNSP_REG(SR) = 0; UNSP_REG(SR) = 0;
} }
int unsp_device::get_irq()
{
if (!m_enable_irq || m_irq)
return -1;
// video
if (read16(0x2862) & read16(0x2863))
return UNSP_IRQ0_LINE;
const uint16_t enable = read16(0x3d21);
const uint16_t status = read16(0x3d22);
// timerA, timerB
if (enable & status & 0x0c00)
return UNSP_IRQ2_LINE;
// UART, ADC XXX: also SPI
if (enable & status & 0x2100)
return UNSP_IRQ3_LINE;
// XXX audio, IRQ4
// extint1, extint2
if (enable & status & 0x1200)
return UNSP_IRQ5_LINE;
// 1024Hz, 2048HZ, 4096HZ
if (enable & status & 0x0070)
return UNSP_IRQ6_LINE;
// TMB1, TMB2, 4Hz, key change
if (enable & status & 0x008b)
return UNSP_IRQ7_LINE;
return -1;
}
void unsp_device::check_irqs() void unsp_device::check_irqs()
{ {
//if (!m_sirq) if (!m_sirq)
//return; return;
int highest_irq = get_irq(); int highest_irq = -1;
/*if (highest_irq == -1)
{
for (int i = 0; i <= 8; i++) for (int i = 0; i <= 8; i++)
{ {
if (BIT(m_sirq, i)) if (BIT(m_sirq, i))
@ -335,22 +275,12 @@ void unsp_device::check_irqs()
break; break;
} }
} }
}*/
if (highest_irq < 0)
return;
if (highest_irq == UNSP_FIQ_LINE) if (highest_irq == UNSP_FIQ_LINE)
{
//logerror("Trying to trigger FIQ\n");
trigger_fiq(); trigger_fiq();
}
else else
{
//printf("Trying to trigger IRQ%d\n", highest_irq - 1);
trigger_irq(highest_irq - 1); trigger_irq(highest_irq - 1);
} }
}
void unsp_device::add_lpc(const int32_t offset) void unsp_device::add_lpc(const int32_t offset)
{ {
@ -360,11 +290,6 @@ void unsp_device::add_lpc(const int32_t offset)
UNSP_REG(SR) |= (new_lpc >> 16) & 0x3f; UNSP_REG(SR) |= (new_lpc >> 16) & 0x3f;
} }
static const int32_t cycles_per_line = 1728;
static uint32_t cycle_count = 0;
static int32_t lines_per_frame = 312;
static int32_t line_count = 0;
inline void unsp_device::execute_one(const uint16_t op) inline void unsp_device::execute_one(const uint16_t op)
{ {
uint32_t lres = 0; uint32_t lres = 0;
@ -382,162 +307,137 @@ inline void unsp_device::execute_one(const uint16_t op)
if(!(UNSP_REG(SR) & UNSP_C)) if(!(UNSP_REG(SR) & UNSP_C))
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 1: // JAE case 1: // JAE
if(UNSP_REG(SR) & UNSP_C) if(UNSP_REG(SR) & UNSP_C)
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 2: // JGE case 2: // JGE
if(!(UNSP_REG(SR) & UNSP_S)) if(!(UNSP_REG(SR) & UNSP_S))
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 3: // JL case 3: // JL
if(UNSP_REG(SR) & UNSP_S) if(UNSP_REG(SR) & UNSP_S)
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 4: // JNE case 4: // JNE
if(!(UNSP_REG(SR) & UNSP_Z)) if(!(UNSP_REG(SR) & UNSP_Z))
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 5: // JE case 5: // JE
if(UNSP_REG(SR) & UNSP_Z) if(UNSP_REG(SR) & UNSP_Z)
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 6: // JPL case 6: // JPL
if(!(UNSP_REG(SR) & UNSP_N)) if(!(UNSP_REG(SR) & UNSP_N))
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 7: // JMI case 7: // JMI
if(UNSP_REG(SR) & UNSP_N) if(UNSP_REG(SR) & UNSP_N)
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 8: // JBE case 8: // JBE
if((UNSP_REG(SR) & (UNSP_Z | UNSP_C)) != UNSP_C) if((UNSP_REG(SR) & (UNSP_Z | UNSP_C)) != UNSP_C)
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 9: // JA case 9: // JA
if((UNSP_REG(SR) & (UNSP_Z | UNSP_C)) == UNSP_C) if((UNSP_REG(SR) & (UNSP_Z | UNSP_C)) == UNSP_C)
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 10: // JLE case 10: // JLE
if(UNSP_REG(SR) & (UNSP_Z | UNSP_S)) if(UNSP_REG(SR) & (UNSP_Z | UNSP_S))
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 11: // JG case 11: // JG
if(!(UNSP_REG(SR) & (UNSP_Z | UNSP_S))) if(!(UNSP_REG(SR) & (UNSP_Z | UNSP_S)))
{ {
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
} }
else else
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
return; return;
case 14: // JMP case 14: // JMP
add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM)); add_lpc((OP1 == 0) ? OPIMM : (0 - OPIMM));
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
return; return;
default: default:
unimplemented_opcode(op); unimplemented_opcode(op);
@ -549,7 +449,6 @@ inline void unsp_device::execute_one(const uint16_t op)
r0 = OPN; r0 = OPN;
r1 = OPA; r1 = OPA;
m_icount -= 4 + 2 * r0; m_icount -= 4 + 2 * r0;
cycle_count += 4 + 2 * r0;
while (r0--) while (r0--)
{ {
@ -562,7 +461,6 @@ inline void unsp_device::execute_one(const uint16_t op)
if (op == 0x9a98) // reti if (op == 0x9a98) // reti
{ {
m_icount -= 8; m_icount -= 8;
cycle_count += 8;
UNSP_REG(SR) = pop(&UNSP_REG(SP)); UNSP_REG(SR) = pop(&UNSP_REG(SP));
UNSP_REG(PC) = pop(&UNSP_REG(SP)); UNSP_REG(PC) = pop(&UNSP_REG(SP));
@ -588,7 +486,6 @@ inline void unsp_device::execute_one(const uint16_t op)
r0 = OPN; r0 = OPN;
r1 = OPA; r1 = OPA;
m_icount -= 4 + 2 * r0; m_icount -= 4 + 2 * r0;
cycle_count += 4 + 2 * r0;
while (r0--) while (r0--)
{ {
@ -605,7 +502,6 @@ inline void unsp_device::execute_one(const uint16_t op)
if(OPN == 1 && OPA != 7) if(OPN == 1 && OPA != 7)
{ {
m_icount -= 12; m_icount -= 12;
cycle_count += 12;
lres = UNSP_REG_I(OPA) * UNSP_REG_I(OPB); lres = UNSP_REG_I(OPA) * UNSP_REG_I(OPB);
if(UNSP_REG_I(OPB) & 0x8000) if(UNSP_REG_I(OPB) & 0x8000)
{ {
@ -624,7 +520,6 @@ inline void unsp_device::execute_one(const uint16_t op)
if(!(OPA & 1)) if(!(OPA & 1))
{ {
m_icount -= 9; m_icount -= 9;
cycle_count += 9;
r1 = read16(UNSP_LPC); r1 = read16(UNSP_LPC);
add_lpc(1); add_lpc(1);
push(UNSP_REG(PC), &UNSP_REG(SP)); push(UNSP_REG(PC), &UNSP_REG(SP));
@ -643,7 +538,6 @@ inline void unsp_device::execute_one(const uint16_t op)
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 5; m_icount -= 5;
cycle_count += 5;
UNSP_REG(PC) = read16(UNSP_LPC); UNSP_REG(PC) = read16(UNSP_LPC);
UNSP_REG(SR) &= 0xffc0; UNSP_REG(SR) &= 0xffc0;
UNSP_REG(SR) |= OPIMM; UNSP_REG(SR) |= OPIMM;
@ -658,7 +552,6 @@ inline void unsp_device::execute_one(const uint16_t op)
if(OPN == 1 && OPA != 7) if(OPN == 1 && OPA != 7)
{ {
m_icount -= 12; m_icount -= 12;
cycle_count += 12;
lres = UNSP_REG_I(OPA) * UNSP_REG_I(OPB); lres = UNSP_REG_I(OPA) * UNSP_REG_I(OPB);
if(UNSP_REG_I(OPB) & 0x8000) if(UNSP_REG_I(OPB) & 0x8000)
{ {
@ -679,7 +572,6 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x05: // Interrupt flags case 0x05: // Interrupt flags
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
switch(OPIMM) switch(OPIMM)
{ {
case 0: case 0:
@ -732,7 +624,6 @@ inline void unsp_device::execute_one(const uint16_t op)
{ {
case 0x00: // r, [bp+imm6] case 0x00: // r, [bp+imm6]
m_icount -= 6; m_icount -= 6;
cycle_count += 6;
r2 = (uint16_t)(UNSP_REG(BP) + OPIMM); r2 = (uint16_t)(UNSP_REG(BP) + OPIMM);
if (OP0 != 0x0d) if (OP0 != 0x0d)
@ -741,7 +632,6 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x01: // r, imm6 case 0x01: // r, imm6
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
r1 = OPIMM; r1 = OPIMM;
break; break;
@ -749,11 +639,9 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x03: // Indirect case 0x03: // Indirect
{ {
m_icount -= 6; m_icount -= 6;
cycle_count += 6;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 1; m_icount -= 1;
cycle_count += 1;
} }
const uint8_t lsbits = OPN & 3; const uint8_t lsbits = OPN & 3;
@ -834,11 +722,9 @@ inline void unsp_device::execute_one(const uint16_t op)
{ {
case 0x00: // r case 0x00: // r
m_icount -= 3; m_icount -= 3;
cycle_count += 3;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
r1 = UNSP_REG_I(OPB); r1 = UNSP_REG_I(OPB);
@ -846,11 +732,9 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x01: // imm16 case 0x01: // imm16
m_icount -= 4; m_icount -= 4;
cycle_count += 4;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 1; m_icount -= 1;
cycle_count += 1;
} }
r0 = UNSP_REG_I(OPB); r0 = UNSP_REG_I(OPB);
@ -860,11 +744,9 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x02: // [imm16] case 0x02: // [imm16]
m_icount -= 7; m_icount -= 7;
cycle_count += 7;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 1; m_icount -= 1;
cycle_count += 1;
} }
r0 = UNSP_REG_I(OPB); r0 = UNSP_REG_I(OPB);
@ -879,11 +761,9 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x03: // store [imm16], r case 0x03: // store [imm16], r
m_icount -= 7; m_icount -= 7;
cycle_count += 7;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 1; m_icount -= 1;
cycle_count += 1;
} }
r1 = r0; r1 = r0;
@ -895,11 +775,9 @@ inline void unsp_device::execute_one(const uint16_t op)
default: // Shifted ops default: // Shifted ops
{ {
m_icount -= 3; m_icount -= 3;
cycle_count += 3;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
uint32_t shift = (UNSP_REG_I(OPB) << 4) | m_sb; uint32_t shift = (UNSP_REG_I(OPB) << 4) | m_sb;
@ -915,11 +793,9 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x05: // More shifted ops case 0x05: // More shifted ops
m_icount -= 3; m_icount -= 3;
cycle_count += 3;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
if (OPN & 4) // Shift right if (OPN & 4) // Shift right
@ -939,11 +815,9 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x06: // Rotated ops case 0x06: // Rotated ops
{ {
m_icount -= 3; m_icount -= 3;
cycle_count += 3;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 2; m_icount -= 2;
cycle_count += 2;
} }
uint32_t shift = (((m_sb << 16) | UNSP_REG_I(OPB)) << 4) | m_sb; uint32_t shift = (((m_sb << 16) | UNSP_REG_I(OPB)) << 4) | m_sb;
@ -963,11 +837,9 @@ inline void unsp_device::execute_one(const uint16_t op)
case 0x07: // Direct 8 case 0x07: // Direct 8
m_icount -= 5; m_icount -= 5;
cycle_count += 5;
if (OPA == 7) if (OPA == 7)
{ {
m_icount -= 1; m_icount -= 1;
cycle_count += 1;
} }
r2 = OPIMM; r2 = OPIMM;
@ -1054,27 +926,7 @@ void unsp_device::execute_run()
{ {
std::stringstream strbuffer; std::stringstream strbuffer;
dasm.disassemble(strbuffer, UNSP_LPC, op, read16(UNSP_LPC+1)); dasm.disassemble(strbuffer, UNSP_LPC, op, read16(UNSP_LPC+1));
uint32_t len = 1; logerror("%x: %s\n", UNSP_LPC, strbuffer.str().c_str());
if ((OP0 < 14 && OP1 == 4 && (OPN == 1 || OPN == 2 || OPN == 3)) || (OP0 == 15 && (OP1 == 1 || OP1 == 2)))
{
len = 2;
}
if (len == 1)
{
logerror("%04x %04x %04x %04x %04x %04x %04x %04x %02x %x%x%x%x %02x %x %x %d %x: %04x %x %x %x %x %x %s\n",
m_r[0], m_r[1], m_r[2], m_r[3], m_r[4], m_r[5], m_r[6], m_r[7],
m_r[6] & 0x3f, BIT(m_r[6], 9), BIT(m_r[6], 8), BIT(m_r[6], 7), BIT(m_r[6], 6), (m_r[6] >> 10) & 0x3f,
m_sb, m_enable_irq ? 1 : 0, cycle_count, UNSP_LPC, op, OP0, OPA, OP1, OPN, OPB, strbuffer.str().c_str());
}
else
{
logerror("%04x %04x %04x %04x %04x %04x %04x %04x %02x %x%x%x%x %02x %x %x %d %x: %04x %04x %x %x %x %x %x %s\n",
m_r[0], m_r[1], m_r[2], m_r[3], m_r[4], m_r[5], m_r[6], m_r[7],
m_r[6] & 0x3f, BIT(m_r[6], 9), BIT(m_r[6], 8), BIT(m_r[6], 7), BIT(m_r[6], 6), (m_r[6] >> 10) & 0x3f,
m_sb, m_enable_irq ? 1 : 0, cycle_count, UNSP_LPC, op, read16(UNSP_LPC+1), OP0, OPA, OP1, OPN, OPB, strbuffer.str().c_str());
}
//logerror("%x: %s\n", UNSP_LPC, strbuffer.str().c_str());
//logerror("%x%04x: %d\n", UNSP_REG(SR) & 0x3f, UNSP_REG(PC), cycle_count);
} }
#endif #endif
@ -1082,26 +934,7 @@ void unsp_device::execute_run()
execute_one(op); execute_one(op);
if (cycle_count >= cycles_per_line)
{
cycle_count -= cycles_per_line;
timer_run(cycles_per_line);
if (line_count == 240)
write16(0x3d61, 1); // trigger vblank IRQ
if (line_count == read16(0x2836))
write16(0x3d61, 2); // trigger vpos IRQ
check_irqs(); check_irqs();
line_count++;
if (line_count == lines_per_frame)
{
line_count = 0;
write16(0x3d60, 0x0100);
}
}
} }
} }
@ -1134,55 +967,3 @@ void unsp_device::execute_set_input(int irqline, int state)
break; break;
} }
} }
void unsp_device::set_timer_interval(int timer, uint32_t interval)
{
if (timer == 0)
timer_tmb1.interval = interval;
else if (timer == 1)
timer_tmb2.interval = interval;
}
void unsp_device::timer_add(struct unsp_timer *timer)
{
if (timer->time == 0)
timer->time = timer->interval;
uint32_t time = timer->time;
struct unsp_timer **p = &timers;
while (*p && (*p)->time <= time) {
time -= (*p)->time;
p = &(*p)->next;
}
timer->next = *p;
*p = timer;
timer->time = time;
if (timer->next)
timer->next->time -= time;
}
void unsp_device::timer_run(uint32_t ticks)
{
struct unsp_timer *timer;
while ((timer = timers) && timer->time <= ticks) {
timers = timer->next;
ticks -= timer->time;
write16(0x3d62, 1 << timer->index);
if (timer->interval) {
timer->time = timer->interval;
timer_add(timer);
}
}
if (timer)
timer->time -= ticks;
}
uint16_t unsp_device::get_video_line()
{
return line_count;
}

17
src/devices/cpu/unsp/unsp.h
View File

@ -17,7 +17,7 @@
#pragma once #pragma once
#define UNSP_LOG_OPCODES (1) #define UNSP_LOG_OPCODES (0)
enum enum
{ {
@ -60,14 +60,6 @@ enum
UNSP_NUM_LINES UNSP_NUM_LINES
}; };
struct unsp_timer
{
uint32_t time;
uint32_t interval;
int index;
struct unsp_timer *next;
};
class unsp_device : public cpu_device class unsp_device : public cpu_device
{ {
public: public:
@ -76,8 +68,6 @@ public:
void set_timer_interval(int timer, uint32_t interval); void set_timer_interval(int timer, uint32_t interval);
uint16_t get_video_line();
protected: protected:
// device-level overrides // device-level overrides
virtual void device_start() override; virtual void device_start() override;
@ -108,9 +98,6 @@ private:
address_space_config m_program_config; address_space_config m_program_config;
void timer_add(struct unsp_timer *timer);
void timer_run(uint32_t ticks);
uint16_t m_r[16]; uint16_t m_r[16];
bool m_enable_irq; bool m_enable_irq;
bool m_enable_fiq; bool m_enable_fiq;
@ -120,7 +107,6 @@ private:
uint16_t m_sirq; uint16_t m_sirq;
uint8_t m_sb; uint8_t m_sb;
uint8_t m_saved_sb[3]; uint8_t m_saved_sb[3];
struct unsp_timer *timers;
address_space *m_program; address_space *m_program;
int m_icount; int m_icount;
@ -140,7 +126,6 @@ private:
inline void trigger_fiq(); inline void trigger_fiq();
inline void trigger_irq(int line); inline void trigger_irq(int line);
inline void check_irqs(); inline void check_irqs();
inline int get_irq();
}; };

55
src/devices/machine/spg2xx.cpp
View File

@ -167,7 +167,7 @@ void spg2xx_device::device_reset()
memset(m_video_regs, 0, 0x100 * sizeof(uint16_t)); memset(m_video_regs, 0, 0x100 * sizeof(uint16_t));
memset(m_io_regs, 0, 0x200 * sizeof(uint16_t)); memset(m_io_regs, 0, 0x200 * sizeof(uint16_t));
//m_io_regs[0x23] = 0x0028; m_io_regs[0x23] = 0x0028;
m_uart_rx_available = false; m_uart_rx_available = false;
m_video_regs[0x36] = 0xffff; m_video_regs[0x36] = 0xffff;
@ -831,7 +831,7 @@ WRITE_LINE_MEMBER(spg2xx_device::vblank)
#endif #endif
const uint16_t old = VIDEO_IRQ_ENABLE & VIDEO_IRQ_STATUS; const uint16_t old = VIDEO_IRQ_ENABLE & VIDEO_IRQ_STATUS;
//VIDEO_IRQ_STATUS |= 1; VIDEO_IRQ_STATUS |= 1;
LOGMASKED(LOG_IRQS, "Setting video IRQ status to %04x\n", VIDEO_IRQ_STATUS); LOGMASKED(LOG_IRQS, "Setting video IRQ status to %04x\n", VIDEO_IRQ_STATUS);
const uint16_t changed = old ^ (VIDEO_IRQ_ENABLE & VIDEO_IRQ_STATUS); const uint16_t changed = old ^ (VIDEO_IRQ_ENABLE & VIDEO_IRQ_STATUS);
if (changed) if (changed)
@ -1140,14 +1140,12 @@ WRITE16_MEMBER(spg2xx_device::io_w)
if (changed & 0x0013) if (changed & 0x0013)
{ {
const uint32_t freq = s_tmb1_freq[hifreq][data & 3]; const uint32_t freq = s_tmb1_freq[hifreq][data & 3];
m_cpu->set_timer_interval(0, 27000000 / freq); m_tmb1->adjust(attotime::from_hz(freq), 0, attotime::from_hz(freq));
//m_tmb1->adjust(attotime::from_hz(freq), 0, attotime::from_hz(freq));
} }
if (changed & 0x001c) if (changed & 0x001c)
{ {
const uint32_t freq = s_tmb2_freq[hifreq][(data >> 2) & 3]; const uint32_t freq = s_tmb2_freq[hifreq][(data >> 2) & 3];
m_cpu->set_timer_interval(1, 27000000 / freq); m_tmb2->adjust(attotime::from_hz(freq), 0, attotime::from_hz(freq));
//m_tmb2->adjust(attotime::from_hz(freq), 0, attotime::from_hz(freq));
} }
} }
break; break;
@ -1301,17 +1299,17 @@ WRITE16_MEMBER(spg2xx_device::io_w)
static const char* const s_9th_bit[4] = { "0", "1", "Odd", "Even" }; static const char* const s_9th_bit[4] = { "0", "1", "Odd", "Even" };
LOGMASKED(LOG_UART, "io_w: UART Control = %04x (TxEn:%d, RxEn:%d, Bits:%d, MultiProc:%d, 9thBit:%s, TxIntEn:%d, RxIntEn:%d\n", data LOGMASKED(LOG_UART, "io_w: UART Control = %04x (TxEn:%d, RxEn:%d, Bits:%d, MultiProc:%d, 9thBit:%s, TxIntEn:%d, RxIntEn:%d\n", data
, BIT(data, 7), BIT(data, 6), BIT(data, 5) ? 9 : 8, BIT(data, 4), s_9th_bit[(data >> 2) & 3], BIT(data, 1), BIT(data, 0)); , BIT(data, 7), BIT(data, 6), BIT(data, 5) ? 9 : 8, BIT(data, 4), s_9th_bit[(data >> 2) & 3], BIT(data, 1), BIT(data, 0));
//const uint16_t changed = m_io_regs[offset] ^ data; const uint16_t changed = m_io_regs[offset] ^ data;
m_io_regs[offset] = data; m_io_regs[offset] = data;
if (!BIT(data, 6)) if (!BIT(data, 6))
{ {
m_uart_rx_available = false; m_uart_rx_available = false;
m_io_regs[0x36] = 0; m_io_regs[0x36] = 0;
} }
//if (BIT(changed, 7) && BIT(data, 7)) if (BIT(changed, 7) && BIT(data, 7))
//{ {
// m_io_regs[0x31] |= 0x0002; m_io_regs[0x31] |= 0x0002;
//} }
break; break;
} }
@ -1328,8 +1326,8 @@ WRITE16_MEMBER(spg2xx_device::io_w)
case 0x35: // UART TX Data case 0x35: // UART TX Data
LOGMASKED(LOG_UART, "io_w: UART Tx Data = %02x\n", data & 0x00ff); LOGMASKED(LOG_UART, "io_w: UART Tx Data = %02x\n", data & 0x00ff);
m_io_regs[offset] = data; m_io_regs[offset] = data;
m_io_regs[0x31] |= 2;
m_uart_tx((uint8_t)data); m_uart_tx((uint8_t)data);
m_io_regs[0x31] |= 2;
break; break;
case 0x36: // UART RX Data case 0x36: // UART RX Data
@ -1390,18 +1388,6 @@ WRITE16_MEMBER(spg2xx_device::io_w)
m_io_regs[offset] = data; m_io_regs[offset] = data;
break; break;
case 0x60: // SPECIAL INTERRUPT HAX - REMOVE BEFORE CHECKIN
m_io_regs[0x22] |= data;
break;
case 0x61: // SPECIAL INTERRUPT HAX - REMOVE BEFORE CHECKIN
m_video_regs[0x63] |= data;
break;
case 0x62: // SPECIAL INTERRUPT HAX - REMOVE BEFORE CHECKIN
m_io_regs[0x22] |= data;
break;
case 0x100: // DMA Source (lo) case 0x100: // DMA Source (lo)
LOGMASKED(LOG_DMA, "io_w: DMA Source (lo) = %04x\n", data); LOGMASKED(LOG_DMA, "io_w: DMA Source (lo) = %04x\n", data);
m_io_regs[offset] = data; m_io_regs[offset] = data;
@ -1435,17 +1421,17 @@ void spg2xx_device::device_timer(emu_timer &timer, device_timer_id id, int param
{ {
case TIMER_TMB1: case TIMER_TMB1:
{ {
//LOGMASKED(LOG_TIMERS, "TMB1 elapsed, setting IRQ Status bit 0 (old:%04x, new:%04x, enable:%04x)\n", IO_IRQ_STATUS, IO_IRQ_STATUS | 1, IO_IRQ_ENABLE); LOGMASKED(LOG_TIMERS, "TMB1 elapsed, setting IRQ Status bit 0 (old:%04x, new:%04x, enable:%04x)\n", IO_IRQ_STATUS, IO_IRQ_STATUS | 1, IO_IRQ_ENABLE);
//IO_IRQ_STATUS |= 1; IO_IRQ_STATUS |= 1;
//check_irqs(0x0001); check_irqs(0x0001);
break; break;
} }
case TIMER_TMB2: case TIMER_TMB2:
{ {
//LOGMASKED(LOG_TIMERS, "TMB2 elapsed, setting IRQ Status bit 1 (old:%04x, new:%04x, enable:%04x)\n", IO_IRQ_STATUS, IO_IRQ_STATUS | 2, IO_IRQ_ENABLE); LOGMASKED(LOG_TIMERS, "TMB2 elapsed, setting IRQ Status bit 1 (old:%04x, new:%04x, enable:%04x)\n", IO_IRQ_STATUS, IO_IRQ_STATUS | 2, IO_IRQ_ENABLE);
//IO_IRQ_STATUS |= 2; IO_IRQ_STATUS |= 2;
//check_irqs(0x0002); check_irqs(0x0002);
break; break;
} }
@ -1476,16 +1462,15 @@ void spg2xx_device::check_irqs(const uint16_t changed)
// m_cpu->set_input_line(UNSP_IRQ1_LINE, ASSERT_LINE); // m_cpu->set_input_line(UNSP_IRQ1_LINE, ASSERT_LINE);
// } // }
if (true)
return;
if (changed & 0x0c00) // Timer A, Timer B IRQ if (changed & 0x0c00) // Timer A, Timer B IRQ
{ {
LOGMASKED(LOG_IRQS, "%ssserting IRQ2 (%04x)\n", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b) ? "A" : "Dea", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b));
m_cpu->set_input_line(UNSP_IRQ2_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x0c00) ? ASSERT_LINE : CLEAR_LINE); m_cpu->set_input_line(UNSP_IRQ2_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x0c00) ? ASSERT_LINE : CLEAR_LINE);
} }
if (changed & 0x2100) // UART, ADC IRQ if (changed & 0x2100) // UART, ADC IRQ
{ {
LOGMASKED(LOG_IRQS, "%ssserting IRQ3 (%04x)\n", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b) ? "A" : "Dea", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b));
m_cpu->set_input_line(UNSP_IRQ3_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x2100) ? ASSERT_LINE : CLEAR_LINE); m_cpu->set_input_line(UNSP_IRQ3_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x2100) ? ASSERT_LINE : CLEAR_LINE);
} }
@ -1505,17 +1490,19 @@ void spg2xx_device::check_irqs(const uint16_t changed)
if (changed & 0x1200) // External IRQ if (changed & 0x1200) // External IRQ
{ {
LOGMASKED(LOG_IRQS, "%ssserting IRQ5 (%04x)\n", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b) ? "A" : "Dea", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b));
m_cpu->set_input_line(UNSP_IRQ5_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x1200) ? ASSERT_LINE : CLEAR_LINE); m_cpu->set_input_line(UNSP_IRQ5_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x1200) ? ASSERT_LINE : CLEAR_LINE);
} }
if (changed & 0x0070) // 1024Hz, 2048Hz, 4096Hz IRQ if (changed & 0x0070) // 1024Hz, 2048Hz, 4096Hz IRQ
{ {
LOGMASKED(LOG_IRQS, "%ssserting IRQ6 (%04x)\n", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b) ? "A" : "Dea", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b));
m_cpu->set_input_line(UNSP_IRQ6_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x0070) ? ASSERT_LINE : CLEAR_LINE); m_cpu->set_input_line(UNSP_IRQ6_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x0070) ? ASSERT_LINE : CLEAR_LINE);
} }
if (changed & 0x008b) // TMB1, TMB2, 4Hz, key change IRQ if (changed & 0x008b) // TMB1, TMB2, 4Hz, key change IRQ
{ {
LOGMASKED(LOG_IRQS, "%ssserting timer IRQ (%04x)\n", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b) ? "A" : "Dea", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b)); LOGMASKED(LOG_IRQS, "%ssserting IRQ7 (%04x)\n", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b) ? "A" : "Dea", (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b));
m_cpu->set_input_line(UNSP_IRQ7_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b) ? ASSERT_LINE : CLEAR_LINE); m_cpu->set_input_line(UNSP_IRQ7_LINE, (IO_IRQ_ENABLE & IO_IRQ_STATUS & 0x008b) ? ASSERT_LINE : CLEAR_LINE);
} }
} }

8
src/devices/machine/spg2xx.h
View File

@ -225,16 +225,16 @@ protected:
AUDIO_ADPCM36_MASK = 0x8000, AUDIO_ADPCM36_MASK = 0x8000,
AUDIO_PHASE_HIGH = 0x200, AUDIO_PHASE_HIGH = 0x200,
AUDIO_PHASE_HIGH_MASK = 0xffff, AUDIO_PHASE_HIGH_MASK = 0x0007,
AUDIO_PHASE_ACCUM_HIGH = 0x201, AUDIO_PHASE_ACCUM_HIGH = 0x201,
AUDIO_PHASE_ACCUM_HIGH_MASK = 0xffff, AUDIO_PHASE_ACCUM_HIGH_MASK = 0x0007,
AUDIO_TARGET_PHASE_HIGH = 0x202, AUDIO_TARGET_PHASE_HIGH = 0x202,
AUDIO_TARGET_PHASE_HIGH_MASK= 0xffff, AUDIO_TARGET_PHASE_HIGH_MASK= 0x0007,
AUDIO_RAMP_DOWN_CLOCK = 0x203, AUDIO_RAMP_DOWN_CLOCK = 0x203,
AUDIO_RAMP_DOWN_CLOCK_MASK = 0xffff, AUDIO_RAMP_DOWN_CLOCK_MASK = 0x0007,
AUDIO_PHASE = 0x204, AUDIO_PHASE = 0x204,
AUDIO_PHASE_ACCUM = 0x205, AUDIO_PHASE_ACCUM = 0x205,