mirror of
https://github.com/holub/mame
synced 2025-04-22 08:22:15 +03:00
checkpoint (nw)
This commit is contained in:
Ryan Holtz
parent
90ec162ff8
commit
d1f2e2ca8e
1
.gitattributes
vendored
1
.gitattributes
vendored
@ -347,6 +347,7 @@ src/emu/cpu/arm7/arm7.h svneol=native#text/plain
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src/emu/cpu/arm7/arm7core.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7core.h svneol=native#text/plain
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src/emu/cpu/arm7/arm7dasm.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7drc.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7exec.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7help.h svneol=native#text/plain
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src/emu/cpu/arm7/arm7ops.c svneol=native#text/plain
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@ -46,12 +46,12 @@
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static DECLARE_WRITE32_DEVICE_HANDLER(arm7_do_callback);
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static DECLARE_READ32_DEVICE_HANDLER(arm7_rt_r_callback);
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static DECLARE_WRITE32_DEVICE_HANDLER(arm7_rt_w_callback);
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void arm7_dt_r_callback(arm_state *cpustate, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *cpustate, UINT32 addr));
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void arm7_dt_w_callback(arm_state *cpustate, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *cpustate, UINT32 addr, UINT32 data));
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void arm7_dt_r_callback(arm_state *arm, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *arm, UINT32 addr));
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void arm7_dt_w_callback(arm_state *arm, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *arm, UINT32 addr, UINT32 data));
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// holder for the co processor Data Transfer Read & Write Callback funcs
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void (*arm7_coproc_dt_r_callback)(arm_state *cpustate, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *cpustate, UINT32 addr));
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void (*arm7_coproc_dt_w_callback)(arm_state *cpustate, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *cpustate, UINT32 addr, UINT32 data));
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void (*arm7_coproc_dt_r_callback)(arm_state *arm, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *arm, UINT32 addr));
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void (*arm7_coproc_dt_w_callback)(arm_state *arm, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *arm, UINT32 addr, UINT32 data));
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INLINE arm_state *get_safe_token(device_t *device)
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@ -61,9 +61,9 @@ INLINE arm_state *get_safe_token(device_t *device)
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return (arm_state *)downcast<legacy_cpu_device *>(device)->token();
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}
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void set_cpsr( arm_state *cpustate, UINT32 val)
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void set_cpsr( arm_state *arm, UINT32 val)
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{
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if (cpustate->archFlags & eARM_ARCHFLAGS_MODE26)
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if (arm->archFlags & eARM_ARCHFLAGS_MODE26)
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{
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if ((val & 0x10) != (ARM7REG(eCPSR) & 0x10))
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{
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@ -113,13 +113,14 @@ enum
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FAULT_PERMISSION,
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};
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INLINE UINT32 arm7_tlb_get_first_level_descriptor( arm_state *cpustate, UINT32 vaddr )
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INLINE UINT32 arm7_tlb_get_first_level_descriptor( arm_state *arm, UINT32 vaddr )
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{
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UINT32 entry_paddr = ( COPRO_TLB_BASE & COPRO_TLB_BASE_MASK ) | ( ( vaddr & COPRO_TLB_VADDR_FLTI_MASK ) >> COPRO_TLB_VADDR_FLTI_MASK_SHIFT );
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return cpustate->program->read_dword( entry_paddr );
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return arm->program->read_dword( entry_paddr );
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}
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INLINE UINT32 arm7_tlb_get_second_level_descriptor( arm_state *cpustate, UINT32 granularity, UINT32 first_desc, UINT32 vaddr )
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// COARSE, desc_level1, vaddr
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INLINE UINT32 arm7_tlb_get_second_level_descriptor( arm_state *arm, UINT32 granularity, UINT32 first_desc, UINT32 vaddr )
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{
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UINT32 desc_lvl2 = vaddr;
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@ -137,10 +138,10 @@ INLINE UINT32 arm7_tlb_get_second_level_descriptor( arm_state *cpustate, UINT32
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break;
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}
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return cpustate->program->read_dword( desc_lvl2 );
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return arm->program->read_dword( desc_lvl2 );
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}
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INLINE int detect_fault( arm_state *cpustate, int permission, int ap, int flags)
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INLINE int detect_fault( arm_state *arm, int permission, int ap, int flags)
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{
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switch (permission)
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{
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@ -225,7 +226,7 @@ INLINE int detect_fault( arm_state *cpustate, int permission, int ap, int flags)
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return FAULT_NONE;
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}
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int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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int arm7_tlb_translate(arm_state *arm, UINT32 *addr, int flags)
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{
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UINT32 desc_lvl1;
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UINT32 desc_lvl2 = 0;
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@ -242,12 +243,12 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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}
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}
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desc_lvl1 = arm7_tlb_get_first_level_descriptor( cpustate, vaddr );
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desc_lvl1 = arm7_tlb_get_first_level_descriptor( arm, vaddr );
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paddr = vaddr;
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#if ARM7_MMU_ENABLE_HACK
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if ((R15 == (cpustate->mmu_enable_addr + 4)) || (R15 == (cpustate->mmu_enable_addr + 8)))
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if ((R15 == (arm->mmu_enable_addr + 4)) || (R15 == (arm->mmu_enable_addr + 8)))
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{
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LOG( ( "ARM7: fetch flat, PC = %08x, vaddr = %08x\n", R15, vaddr ) );
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*addr = vaddr;
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@ -255,7 +256,7 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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}
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else
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{
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cpustate->mmu_enable_addr = 1;
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arm->mmu_enable_addr = 1;
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}
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#endif
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@ -271,19 +272,19 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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LOG( ( "ARM7: Translation fault on unmapped virtual address, PC = %08x, vaddr = %08x\n", R15, vaddr ) );
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COPRO_FAULT_STATUS_D = (5 << 0); // 5 = section translation fault
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COPRO_FAULT_ADDRESS = vaddr;
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cpustate->pendingAbtD = 1;
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arm->pendingAbtD = 1;
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}
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else if (flags & ARM7_TLB_ABORT_P)
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{
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LOG( ( "ARM7: Translation fault on unmapped virtual address, PC = %08x, vaddr = %08x\n", R15, vaddr ) );
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cpustate->pendingAbtP = 1;
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arm->pendingAbtP = 1;
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}
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return FALSE;
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case COPRO_TLB_COARSE_TABLE:
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// Entry is the physical address of a coarse second-level table
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if ((permission == 1) || (permission == 3))
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{
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desc_lvl2 = arm7_tlb_get_second_level_descriptor( cpustate, TLB_COARSE, desc_lvl1, vaddr );
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desc_lvl2 = arm7_tlb_get_second_level_descriptor( arm, TLB_COARSE, desc_lvl1, vaddr );
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}
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else
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{
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@ -292,32 +293,32 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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break;
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case COPRO_TLB_SECTION_TABLE:
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{
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// Entry is a section
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UINT8 ap = (desc_lvl1 >> 10) & 3;
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int fault = detect_fault( cpustate, permission, ap, flags);
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if (fault == FAULT_NONE)
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{
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paddr = ( desc_lvl1 & COPRO_TLB_SECTION_PAGE_MASK ) | ( vaddr & ~COPRO_TLB_SECTION_PAGE_MASK );
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}
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else
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{
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if (flags & ARM7_TLB_ABORT_D)
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// Entry is a section
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UINT8 ap = (desc_lvl1 >> 10) & 3;
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int fault = detect_fault( arm, permission, ap, flags);
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if (fault == FAULT_NONE)
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{
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LOG( ( "ARM7: Section Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
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COPRO_FAULT_STATUS_D = ((fault == FAULT_DOMAIN) ? (9 << 0) : (13 << 0)) | (domain << 4); // 9 = section domain fault, 13 = section permission fault
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COPRO_FAULT_ADDRESS = vaddr;
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cpustate->pendingAbtD = 1;
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LOG( ( "vaddr %08X desc_lvl1 %08X domain %d permission %d ap %d s %d r %d mode %d read %d write %d\n",
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vaddr, desc_lvl1, domain, permission, ap, (COPRO_CTRL & COPRO_CTRL_SYSTEM) ? 1 : 0, (COPRO_CTRL & COPRO_CTRL_ROM) ? 1 : 0,
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GET_MODE, flags & ARM7_TLB_READ ? 1 : 0, flags & ARM7_TLB_WRITE ? 1 : 0) );
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paddr = ( desc_lvl1 & COPRO_TLB_SECTION_PAGE_MASK ) | ( vaddr & ~COPRO_TLB_SECTION_PAGE_MASK );
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}
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else if (flags & ARM7_TLB_ABORT_P)
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else
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{
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LOG( ( "ARM7: Section Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
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cpustate->pendingAbtP = 1;
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if (flags & ARM7_TLB_ABORT_D)
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{
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LOG( ( "ARM7: Section Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
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COPRO_FAULT_STATUS_D = ((fault == FAULT_DOMAIN) ? (9 << 0) : (13 << 0)) | (domain << 4); // 9 = section domain fault, 13 = section permission fault
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COPRO_FAULT_ADDRESS = vaddr;
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arm->pendingAbtD = 1;
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LOG( ( "vaddr %08X desc_lvl1 %08X domain %d permission %d ap %d s %d r %d mode %d read %d write %d\n",
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vaddr, desc_lvl1, domain, permission, ap, (COPRO_CTRL & COPRO_CTRL_SYSTEM) ? 1 : 0, (COPRO_CTRL & COPRO_CTRL_ROM) ? 1 : 0,
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GET_MODE, flags & ARM7_TLB_READ ? 1 : 0, flags & ARM7_TLB_WRITE ? 1 : 0) );
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}
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else if (flags & ARM7_TLB_ABORT_P)
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{
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LOG( ( "ARM7: Section Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
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arm->pendingAbtP = 1;
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}
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return FALSE;
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}
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return FALSE;
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}
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}
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break;
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case COPRO_TLB_FINE_TABLE:
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@ -340,12 +341,12 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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LOG( ( "ARM7: Translation fault on unmapped virtual address, vaddr = %08x, PC %08X\n", vaddr, R15 ) );
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COPRO_FAULT_STATUS_D = (7 << 0) | (domain << 4); // 7 = page translation fault
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COPRO_FAULT_ADDRESS = vaddr;
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cpustate->pendingAbtD = 1;
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arm->pendingAbtD = 1;
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}
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else if (flags & ARM7_TLB_ABORT_P)
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{
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LOG( ( "ARM7: Translation fault on unmapped virtual address, vaddr = %08x, PC %08X\n", vaddr, R15 ) );
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cpustate->pendingAbtP = 1;
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arm->pendingAbtP = 1;
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}
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return FALSE;
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case COPRO_TLB_LARGE_PAGE:
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@ -356,7 +357,7 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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// Small page descriptor
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{
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UINT8 ap = ((((desc_lvl2 >> 4) & 0xFF) >> (((vaddr >> 10) & 3) << 1)) & 3);
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int fault = detect_fault( cpustate, permission, ap, flags);
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int fault = detect_fault( arm, permission, ap, flags);
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if (fault == FAULT_NONE)
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{
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paddr = ( desc_lvl2 & COPRO_TLB_SMALL_PAGE_MASK ) | ( vaddr & ~COPRO_TLB_SMALL_PAGE_MASK );
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@ -369,7 +370,7 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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LOG( ( "ARM7: Page Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
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COPRO_FAULT_STATUS_D = ((fault == FAULT_DOMAIN) ? (11 << 0) : (15 << 0)) | (domain << 4); // 11 = page domain fault, 15 = page permission fault
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COPRO_FAULT_ADDRESS = vaddr;
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cpustate->pendingAbtD = 1;
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arm->pendingAbtD = 1;
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LOG( ( "vaddr %08X desc_lvl2 %08X domain %d permission %d ap %d s %d r %d mode %d read %d write %d\n",
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vaddr, desc_lvl2, domain, permission, ap, (COPRO_CTRL & COPRO_CTRL_SYSTEM) ? 1 : 0, (COPRO_CTRL & COPRO_CTRL_ROM) ? 1 : 0,
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GET_MODE, flags & ARM7_TLB_READ ? 1 : 0, flags & ARM7_TLB_WRITE ? 1 : 0) );
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@ -377,7 +378,7 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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else if (flags & ARM7_TLB_ABORT_P)
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{
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LOG( ( "ARM7: Page Table, Section %s fault on virtual address, vaddr = %08x, PC = %08x\n", (fault == FAULT_DOMAIN) ? "domain" : "permission", vaddr, R15 ) );
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cpustate->pendingAbtP = 1;
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arm->pendingAbtP = 1;
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}
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return FALSE;
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}
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@ -399,12 +400,12 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags)
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static CPU_TRANSLATE( arm7 )
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{
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arm_state *cpustate = (device != NULL) ? (arm_state *)device->token() : NULL;
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arm_state *arm = (device != NULL) ? (arm_state *)device->token() : NULL;
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/* only applies to the program address space and only does something if the MMU's enabled */
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if( space == AS_PROGRAM && ( COPRO_CTRL & COPRO_CTRL_MMU_EN ) )
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{
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return arm7_tlb_translate(cpustate, address, 0);
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return arm7_tlb_translate(arm, address, 0);
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}
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return TRUE;
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}
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@ -418,15 +419,15 @@ static CPU_TRANSLATE( arm7 )
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**************************************************************************/
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static CPU_INIT( arm7 )
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{
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arm_state *cpustate = get_safe_token(device);
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arm_state *arm = get_safe_token(device);
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// must call core
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arm7_core_init(device, "arm7");
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cpustate->irq_callback = irqcallback;
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cpustate->device = device;
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cpustate->program = &device->space(AS_PROGRAM);
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cpustate->direct = &cpustate->program->direct();
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arm->irq_callback = irqcallback;
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arm->device = device;
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arm->program = &device->space(AS_PROGRAM);
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arm->direct = &arm->program->direct();
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// setup co-proc callbacks
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arm7_coproc_do_callback = arm7_do_callback;
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@ -438,76 +439,76 @@ static CPU_INIT( arm7 )
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static CPU_RESET( arm7 )
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{
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arm_state *cpustate = get_safe_token(device);
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arm_state *arm = get_safe_token(device);
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// must call core reset
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arm7_core_reset(device);
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cpustate->archRev = 4; // ARMv4
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cpustate->archFlags = eARM_ARCHFLAGS_T; // has Thumb
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arm->archRev = 4; // ARMv4
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arm->archFlags = eARM_ARCHFLAGS_T; // has Thumb
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}
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static CPU_RESET( arm7_be )
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{
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arm_state *cpustate = get_safe_token(device);
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arm_state *arm = get_safe_token(device);
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CPU_RESET_CALL( arm7 );
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cpustate->endian = ENDIANNESS_BIG;
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arm->endian = ENDIANNESS_BIG;
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}
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static CPU_RESET( arm7500 )
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{
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arm_state *cpustate = get_safe_token(device);
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arm_state *arm = get_safe_token(device);
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// must call core reset
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arm7_core_reset(device);
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cpustate->archRev = 3; // ARMv3
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cpustate->archFlags = eARM_ARCHFLAGS_MODE26;
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arm->archRev = 3; // ARMv3
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arm->archFlags = eARM_ARCHFLAGS_MODE26;
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}
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static CPU_RESET( arm9 )
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{
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arm_state *cpustate = get_safe_token(device);
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arm_state *arm = get_safe_token(device);
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// must call core reset
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arm7_core_reset(device);
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cpustate->archRev = 5; // ARMv5
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cpustate->archFlags = eARM_ARCHFLAGS_T | eARM_ARCHFLAGS_E; // has TE extensions
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arm->archRev = 5; // ARMv5
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arm->archFlags = eARM_ARCHFLAGS_T | eARM_ARCHFLAGS_E; // has TE extensions
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}
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static CPU_RESET( arm920t )
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{
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arm_state *cpustate = get_safe_token(device);
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arm_state *arm = get_safe_token(device);
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// must call core reset
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arm7_core_reset(device);
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cpustate->archRev = 4; // ARMv4
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cpustate->archFlags = eARM_ARCHFLAGS_T; // has T extension
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arm->archRev = 4; // ARMv4
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arm->archFlags = eARM_ARCHFLAGS_T; // has T extension
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}
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static CPU_RESET( pxa255 )
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{
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arm_state *cpustate = get_safe_token(device);
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arm_state *arm = get_safe_token(device);
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// must call core reset
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arm7_core_reset(device);
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cpustate->archRev = 5; // ARMv5
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cpustate->archFlags = eARM_ARCHFLAGS_T | eARM_ARCHFLAGS_E | eARM_ARCHFLAGS_XSCALE; // has TE and XScale extensions
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arm->archRev = 5; // ARMv5
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arm->archFlags = eARM_ARCHFLAGS_T | eARM_ARCHFLAGS_E | eARM_ARCHFLAGS_XSCALE; // has TE and XScale extensions
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}
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static CPU_RESET( sa1110 )
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{
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arm_state *cpustate = get_safe_token(device);
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arm_state *arm = get_safe_token(device);
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// must call core reset
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arm7_core_reset(device);
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cpustate->archRev = 4; // ARMv4
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cpustate->archFlags = eARM_ARCHFLAGS_SA; // has StrongARM, no Thumb, no Enhanced DSP
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arm->archRev = 4; // ARMv4
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arm->archFlags = eARM_ARCHFLAGS_SA; // has StrongARM, no Thumb, no Enhanced DSP
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}
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static CPU_EXIT( arm7 )
|
||||
@ -522,11 +523,11 @@ static CPU_EXECUTE( arm7 )
|
||||
{
|
||||
UINT32 pc;
|
||||
UINT32 insn;
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
arm_state *arm = get_safe_token(device);
|
||||
|
||||
do
|
||||
{
|
||||
debugger_instruction_hook(cpustate->device, GET_PC);
|
||||
debugger_instruction_hook(arm->device, GET_PC);
|
||||
|
||||
/* handle Thumb instructions if active */
|
||||
if (T_IS_SET(GET_CPSR))
|
||||
@ -540,14 +541,14 @@ static CPU_EXECUTE( arm7 )
|
||||
|
||||
if ( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate(cpustate, &raddr, ARM7_TLB_ABORT_P | ARM7_TLB_READ))
|
||||
if (!arm7_tlb_translate(arm, &raddr, ARM7_TLB_ABORT_P | ARM7_TLB_READ))
|
||||
{
|
||||
goto skip_exec;
|
||||
}
|
||||
}
|
||||
|
||||
insn = cpustate->direct->read_decrypted_word(raddr);
|
||||
thumb_handler[(insn & 0xffc0) >> 6](cpustate, pc, insn);
|
||||
insn = arm->direct->read_decrypted_word(raddr);
|
||||
thumb_handler[(insn & 0xffc0) >> 6](arm, pc, insn);
|
||||
|
||||
}
|
||||
else
|
||||
@ -562,7 +563,7 @@ static CPU_EXECUTE( arm7 )
|
||||
|
||||
if ( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate(cpustate, &raddr, ARM7_TLB_ABORT_P | ARM7_TLB_READ))
|
||||
if (!arm7_tlb_translate(arm, &raddr, ARM7_TLB_ABORT_P | ARM7_TLB_READ))
|
||||
{
|
||||
goto skip_exec;
|
||||
}
|
||||
@ -578,7 +579,7 @@ static CPU_EXECUTE( arm7 )
|
||||
}
|
||||
#endif
|
||||
|
||||
insn = cpustate->direct->read_decrypted_dword(raddr);
|
||||
insn = arm->direct->read_decrypted_dword(raddr);
|
||||
|
||||
/* process condition codes for this instruction */
|
||||
switch (insn >> INSN_COND_SHIFT)
|
||||
@ -646,7 +647,7 @@ static CPU_EXECUTE( arm7 )
|
||||
/*******************************************************************/
|
||||
/* If we got here - condition satisfied, so decode the instruction */
|
||||
/*******************************************************************/
|
||||
ops_handler[((insn & 0xF000000) >> 24)](cpustate, insn);
|
||||
ops_handler[((insn & 0xF000000) >> 24)](arm, insn);
|
||||
}
|
||||
|
||||
skip_exec:
|
||||
@ -658,10 +659,10 @@ skip_exec:
|
||||
} while (ARM7_ICOUNT > 0);
|
||||
}
|
||||
|
||||
static void set_irq_line(arm_state *cpustate, int irqline, int state)
|
||||
static void set_irq_line(arm_state *arm, int irqline, int state)
|
||||
{
|
||||
// must call core
|
||||
arm7_core_set_irq_line(cpustate, irqline, state);
|
||||
arm7_core_set_irq_line(arm, irqline, state);
|
||||
}
|
||||
|
||||
static CPU_DISASSEMBLE( arm7 )
|
||||
@ -669,7 +670,7 @@ static CPU_DISASSEMBLE( arm7 )
|
||||
CPU_DISASSEMBLE( arm7arm );
|
||||
CPU_DISASSEMBLE( arm7thumb );
|
||||
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
arm_state *arm = get_safe_token(device);
|
||||
|
||||
if (T_IS_SET(GET_CPSR))
|
||||
return CPU_DISASSEMBLE_CALL(arm7thumb);
|
||||
@ -682,7 +683,7 @@ static CPU_DISASSEMBLE( arm7_be )
|
||||
CPU_DISASSEMBLE( arm7arm_be );
|
||||
CPU_DISASSEMBLE( arm7thumb_be );
|
||||
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
arm_state *arm = get_safe_token(device);
|
||||
|
||||
if (T_IS_SET(GET_CPSR))
|
||||
return CPU_DISASSEMBLE_CALL(arm7thumb_be);
|
||||
@ -697,18 +698,18 @@ static CPU_DISASSEMBLE( arm7_be )
|
||||
|
||||
static CPU_SET_INFO( arm7 )
|
||||
{
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
arm_state *arm = get_safe_token(device);
|
||||
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are set as 64-bit signed integers --- */
|
||||
|
||||
/* interrupt lines/exceptions */
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(cpustate, ARM7_IRQ_LINE, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(cpustate, ARM7_FIRQ_LINE, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(cpustate, ARM7_ABORT_EXCEPTION, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(cpustate, ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(cpustate, ARM7_UNDEFINE_EXCEPTION, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(arm, ARM7_IRQ_LINE, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(arm, ARM7_FIRQ_LINE, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(arm, ARM7_ABORT_EXCEPTION, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(arm, ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(arm, ARM7_UNDEFINE_EXCEPTION, info->i); break;
|
||||
|
||||
/* registers shared by all operating modes */
|
||||
case CPUINFO_INT_REGISTER + ARM7_R0: ARM7REG( 0) = info->i; break;
|
||||
@ -731,7 +732,7 @@ static CPU_SET_INFO( arm7 )
|
||||
|
||||
case CPUINFO_INT_PC:
|
||||
case CPUINFO_INT_REGISTER + ARM7_PC: R15 = info->i; break;
|
||||
case CPUINFO_INT_SP: SetRegister(cpustate, 13,info->i); break;
|
||||
case CPUINFO_INT_SP: SetRegister(arm, 13,info->i); break;
|
||||
|
||||
/* FIRQ Mode Shadowed Registers */
|
||||
case CPUINFO_INT_REGISTER + ARM7_FR8: ARM7REG(eR8_FIQ) = info->i; break;
|
||||
@ -773,7 +774,7 @@ static CPU_SET_INFO( arm7 )
|
||||
|
||||
CPU_GET_INFO( arm7 )
|
||||
{
|
||||
arm_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
||||
arm_state *arm = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
@ -802,11 +803,11 @@ CPU_GET_INFO( arm7 )
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
|
||||
|
||||
/* interrupt lines/exceptions */
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = cpustate->pendingIrq; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = cpustate->pendingFiq; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = cpustate->pendingAbtD; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = cpustate->pendingAbtP; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = cpustate->pendingUnd; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = arm->pendingIrq; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = arm->pendingFiq; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = arm->pendingAbtD; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = arm->pendingAbtP; break;
|
||||
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = arm->pendingUnd; break;
|
||||
|
||||
/* registers shared by all operating modes */
|
||||
case CPUINFO_INT_REGISTER + ARM7_R0: info->i = ARM7REG( 0); break;
|
||||
@ -829,7 +830,7 @@ CPU_GET_INFO( arm7 )
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* not implemented */ break;
|
||||
case CPUINFO_INT_PC:
|
||||
case CPUINFO_INT_REGISTER + ARM7_PC: info->i = GET_PC; break;
|
||||
case CPUINFO_INT_SP: info->i = GetRegister(cpustate, 13); break;
|
||||
case CPUINFO_INT_SP: info->i = GetRegister(arm, 13); break;
|
||||
|
||||
/* FIRQ Mode Shadowed Registers */
|
||||
case CPUINFO_INT_REGISTER + ARM7_FR8: info->i = ARM7REG(eR8_FIQ); break;
|
||||
@ -1015,13 +1016,13 @@ CPU_GET_INFO( sa1110 )
|
||||
|
||||
static WRITE32_DEVICE_HANDLER( arm7_do_callback )
|
||||
{
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
cpustate->pendingUnd = 1;
|
||||
arm_state *arm = get_safe_token(device);
|
||||
arm->pendingUnd = 1;
|
||||
}
|
||||
|
||||
static READ32_DEVICE_HANDLER( arm7_rt_r_callback )
|
||||
{
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
arm_state *arm = get_safe_token(device);
|
||||
UINT32 opcode = offset;
|
||||
UINT8 cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
|
||||
UINT8 op2 = ( opcode & INSN_COPRO_OP2 ) >> INSN_COPRO_OP2_SHIFT;
|
||||
@ -1029,12 +1030,12 @@ static READ32_DEVICE_HANDLER( arm7_rt_r_callback )
|
||||
UINT8 cpnum = (opcode & INSN_COPRO_CPNUM) >> INSN_COPRO_CPNUM_SHIFT;
|
||||
UINT32 data = 0;
|
||||
|
||||
// printf("cpnum %d cReg %d op2 %d op3 %d (%x)\n", cpnum, cReg, op2, op3, GET_REGISTER(cpustate, 15));
|
||||
// printf("cpnum %d cReg %d op2 %d op3 %d (%x)\n", cpnum, cReg, op2, op3, GET_REGISTER(arm, 15));
|
||||
|
||||
// we only handle system copro here
|
||||
if (cpnum != 15)
|
||||
{
|
||||
if (cpustate->archFlags & eARM_ARCHFLAGS_XSCALE)
|
||||
if (arm->archFlags & eARM_ARCHFLAGS_XSCALE)
|
||||
{
|
||||
// handle XScale specific CP14
|
||||
if (cpnum == 14)
|
||||
@ -1042,7 +1043,7 @@ static READ32_DEVICE_HANDLER( arm7_rt_r_callback )
|
||||
switch( cReg )
|
||||
{
|
||||
case 1: // clock counter
|
||||
data = (UINT32)cpustate->device->total_cycles();
|
||||
data = (UINT32)arm->device->total_cycles();
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -1051,15 +1052,15 @@ static READ32_DEVICE_HANDLER( arm7_rt_r_callback )
|
||||
}
|
||||
else
|
||||
{
|
||||
fatalerror("XScale: Unhandled coprocessor %d (archFlags %x)\n", cpnum, cpustate->archFlags);
|
||||
fatalerror("XScale: Unhandled coprocessor %d (archFlags %x)\n", cpnum, arm->archFlags);
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG( ("ARM7: Unhandled coprocessor %d (archFlags %x)\n", cpnum, cpustate->archFlags) );
|
||||
cpustate->pendingUnd = 1;
|
||||
LOG( ("ARM7: Unhandled coprocessor %d (archFlags %x)\n", cpnum, arm->archFlags) );
|
||||
arm->pendingUnd = 1;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
@ -1080,14 +1081,14 @@ static READ32_DEVICE_HANDLER( arm7_rt_r_callback )
|
||||
switch(op2)
|
||||
{
|
||||
case 0:
|
||||
switch (cpustate->archRev)
|
||||
switch (arm->archRev)
|
||||
{
|
||||
case 3: // ARM6 32-bit
|
||||
data = 0x41;
|
||||
break;
|
||||
|
||||
case 4: // ARM7/SA11xx
|
||||
if (cpustate->archFlags & eARM_ARCHFLAGS_SA)
|
||||
if (arm->archFlags & eARM_ARCHFLAGS_SA)
|
||||
{
|
||||
// ARM Architecture Version 4
|
||||
// Part Number 0xB11 (SA1110)
|
||||
@ -1113,11 +1114,11 @@ static READ32_DEVICE_HANDLER( arm7_rt_r_callback )
|
||||
|
||||
case 5: // ARM9/10/XScale
|
||||
data = 0x41 | (9 << 12);
|
||||
if (cpustate->archFlags & eARM_ARCHFLAGS_T)
|
||||
if (arm->archFlags & eARM_ARCHFLAGS_T)
|
||||
{
|
||||
if (cpustate->archFlags & eARM_ARCHFLAGS_E)
|
||||
if (arm->archFlags & eARM_ARCHFLAGS_E)
|
||||
{
|
||||
if (cpustate->archFlags & eARM_ARCHFLAGS_J)
|
||||
if (arm->archFlags & eARM_ARCHFLAGS_J)
|
||||
{
|
||||
data |= (6<<16); // v5TEJ
|
||||
}
|
||||
@ -1193,7 +1194,7 @@ static READ32_DEVICE_HANDLER( arm7_rt_r_callback )
|
||||
|
||||
static WRITE32_DEVICE_HANDLER( arm7_rt_w_callback )
|
||||
{
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
arm_state *arm = get_safe_token(device);
|
||||
UINT32 opcode = offset;
|
||||
UINT8 cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
|
||||
UINT8 op2 = ( opcode & INSN_COPRO_OP2 ) >> INSN_COPRO_OP2_SHIFT;
|
||||
@ -1211,7 +1212,7 @@ static WRITE32_DEVICE_HANDLER( arm7_rt_w_callback )
|
||||
else
|
||||
{
|
||||
LOG( ("ARM7: Unhandled coprocessor %d\n", cpnum) );
|
||||
cpustate->pendingUnd = 1;
|
||||
arm->pendingUnd = 1;
|
||||
return;
|
||||
}
|
||||
}
|
||||
@ -1241,11 +1242,11 @@ static WRITE32_DEVICE_HANDLER( arm7_rt_w_callback )
|
||||
#if ARM7_MMU_ENABLE_HACK
|
||||
if (((data & COPRO_CTRL_MMU_EN) != 0) && ((COPRO_CTRL & COPRO_CTRL_MMU_EN) == 0))
|
||||
{
|
||||
cpustate->mmu_enable_addr = R15;
|
||||
arm->mmu_enable_addr = R15;
|
||||
}
|
||||
if (((data & COPRO_CTRL_MMU_EN) == 0) && ((COPRO_CTRL & COPRO_CTRL_MMU_EN) != 0))
|
||||
{
|
||||
if (!arm7_tlb_translate( cpustate, &R15, 0))
|
||||
if (!arm7_tlb_translate( arm, &R15, 0))
|
||||
{
|
||||
fatalerror("ARM7_MMU_ENABLE_HACK translate failed\n");
|
||||
}
|
||||
@ -1295,29 +1296,29 @@ static WRITE32_DEVICE_HANDLER( arm7_rt_w_callback )
|
||||
}
|
||||
}
|
||||
|
||||
void arm7_dt_r_callback(arm_state *cpustate, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *cpustate, UINT32 addr))
|
||||
void arm7_dt_r_callback(arm_state *arm, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *arm, UINT32 addr))
|
||||
{
|
||||
UINT8 cpn = (insn >> 8) & 0xF;
|
||||
if ((cpustate->archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
|
||||
if ((arm->archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
|
||||
{
|
||||
LOG( ( "arm7_dt_r_callback: DSP Coprocessor 0 (CP0) not yet emulated (PC %08x)\n", GET_PC ) );
|
||||
}
|
||||
else
|
||||
{
|
||||
cpustate->pendingUnd = 1;
|
||||
arm->pendingUnd = 1;
|
||||
}
|
||||
}
|
||||
|
||||
void arm7_dt_w_callback(arm_state *cpustate, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *cpustate, UINT32 addr, UINT32 data))
|
||||
void arm7_dt_w_callback(arm_state *arm, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *arm, UINT32 addr, UINT32 data))
|
||||
{
|
||||
UINT8 cpn = (insn >> 8) & 0xF;
|
||||
if ((cpustate->archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
|
||||
if ((arm->archFlags & eARM_ARCHFLAGS_XSCALE) && (cpn == 0))
|
||||
{
|
||||
LOG( ( "arm7_dt_w_callback: DSP Coprocessor 0 (CP0) not yet emulated (PC %08x)\n", GET_PC ) );
|
||||
}
|
||||
else
|
||||
{
|
||||
cpustate->pendingUnd = 1;
|
||||
arm->pendingUnd = 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -34,6 +34,26 @@
|
||||
#define __ARM7_H__
|
||||
|
||||
|
||||
#define ARM7_MAX_FASTRAM 4
|
||||
#define ARM7_MAX_HOTSPOTS 16
|
||||
|
||||
enum
|
||||
{
|
||||
CPUINFO_INT_ARM7_DRC_OPTIONS = CPUINFO_INT_CPU_SPECIFIC,
|
||||
|
||||
CPUINFO_INT_ARM7_FASTRAM_SELECT,
|
||||
CPUINFO_INT_ARM7_FASTRAM_START,
|
||||
CPUINFO_INT_ARM7_FASTRAM_END,
|
||||
CPUINFO_INT_ARM7_FASTRAM_READONLY,
|
||||
|
||||
CPUINFO_INT_ARM7_HOTSPOT_SELECT,
|
||||
CPUINFO_INT_ARM7_HOTSPOT_PC,
|
||||
CPUINFO_INT_ARM7_HOTSPOT_OPCODE,
|
||||
CPUINFO_INT_ARM7_HOTSPOT_CYCLES,
|
||||
|
||||
CPUINFO_PTR_ARM7_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC
|
||||
};
|
||||
|
||||
/****************************************************************************************************
|
||||
* PUBLIC FUNCTIONS
|
||||
***************************************************************************************************/
|
||||
|
||||
@ -80,9 +80,9 @@
|
||||
/* Prototypes */
|
||||
|
||||
|
||||
extern UINT32 decodeShift(arm_state *cpustate, UINT32 insn, UINT32 *pCarry);
|
||||
extern UINT32 decodeShift(arm_state *arm, UINT32 insn, UINT32 *pCarry);
|
||||
|
||||
void arm7_check_irq_state(arm_state *cpustate);
|
||||
void arm7_check_irq_state(arm_state *arm);
|
||||
|
||||
|
||||
/* Static Vars */
|
||||
@ -93,9 +93,9 @@ write32_device_func arm7_coproc_rt_w_callback; // holder for the co processor R
|
||||
|
||||
#ifdef UNUSED_DEFINITION
|
||||
// custom dasm callback handlers for co-processor instructions
|
||||
char *(*arm7_dasm_cop_dt_callback)(arm_state *cpustate, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
char *(*arm7_dasm_cop_rt_callback)(arm_state *cpustate, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
char *(*arm7_dasm_cop_do_callback)(arm_state *cpustate, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
char *(*arm7_dasm_cop_dt_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
char *(*arm7_dasm_cop_rt_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
char *(*arm7_dasm_cop_do_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
#endif
|
||||
|
||||
|
||||
@ -119,40 +119,40 @@ static const char *GetModeText(int cpsr)
|
||||
// CPU INIT
|
||||
static void arm7_core_init(device_t *device, const char *cpuname)
|
||||
{
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
arm_state *arm = get_safe_token(device);
|
||||
|
||||
device->save_item(NAME(cpustate->sArmRegister));
|
||||
device->save_item(NAME(cpustate->pendingIrq));
|
||||
device->save_item(NAME(cpustate->pendingFiq));
|
||||
device->save_item(NAME(cpustate->pendingAbtD));
|
||||
device->save_item(NAME(cpustate->pendingAbtP));
|
||||
device->save_item(NAME(cpustate->pendingUnd));
|
||||
device->save_item(NAME(cpustate->pendingSwi));
|
||||
device->save_item(NAME(arm->r));
|
||||
device->save_item(NAME(arm->pendingIrq));
|
||||
device->save_item(NAME(arm->pendingFiq));
|
||||
device->save_item(NAME(arm->pendingAbtD));
|
||||
device->save_item(NAME(arm->pendingAbtP));
|
||||
device->save_item(NAME(arm->pendingUnd));
|
||||
device->save_item(NAME(arm->pendingSwi));
|
||||
}
|
||||
|
||||
// CPU RESET
|
||||
static void arm7_core_reset(legacy_cpu_device *device)
|
||||
{
|
||||
arm_state *cpustate = get_safe_token(device);
|
||||
arm_state *arm = get_safe_token(device);
|
||||
|
||||
device_irq_acknowledge_callback save_irqcallback = cpustate->irq_callback;
|
||||
device_irq_acknowledge_callback save_irqcallback = arm->irq_callback;
|
||||
|
||||
memset(cpustate, 0, sizeof(arm_state));
|
||||
cpustate->irq_callback = save_irqcallback;
|
||||
cpustate->device = device;
|
||||
cpustate->program = &device->space(AS_PROGRAM);
|
||||
cpustate->endian = ENDIANNESS_LITTLE;
|
||||
cpustate->direct = &cpustate->program->direct();
|
||||
memset(arm, 0, sizeof(arm_state));
|
||||
arm->irq_callback = save_irqcallback;
|
||||
arm->device = device;
|
||||
arm->program = &device->space(AS_PROGRAM);
|
||||
arm->endian = ENDIANNESS_LITTLE;
|
||||
arm->direct = &arm->program->direct();
|
||||
|
||||
/* start up in SVC mode with interrupts disabled. */
|
||||
ARM7REG(eCPSR) = I_MASK | F_MASK | 0x10;
|
||||
SwitchMode(cpustate, eARM7_MODE_SVC);
|
||||
SwitchMode(arm, eARM7_MODE_SVC);
|
||||
R15 = 0;
|
||||
}
|
||||
|
||||
// CPU CHECK IRQ STATE
|
||||
// Note: couldn't find any exact cycle counts for most of these exceptions
|
||||
void arm7_check_irq_state(arm_state *cpustate)
|
||||
void arm7_check_irq_state(arm_state *arm)
|
||||
{
|
||||
UINT32 cpsr = GET_CPSR; /* save current CPSR */
|
||||
UINT32 pc = R15 + 4; /* save old pc (already incremented in pipeline) */;
|
||||
@ -169,25 +169,25 @@ void arm7_check_irq_state(arm_state *cpustate)
|
||||
*/
|
||||
|
||||
// Data Abort
|
||||
if (cpustate->pendingAbtD) {
|
||||
if (arm->pendingAbtD) {
|
||||
if (MODE26) fatalerror( "pendingAbtD (todo)\n");
|
||||
SwitchMode(cpustate, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(cpustate, 14, pc - 8 + 8); /* save PC to R14 */
|
||||
SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */
|
||||
SwitchMode(arm, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(arm, 14, pc - 8 + 8); /* save PC to R14 */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x10; /* IRQ Vector address */
|
||||
if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 |= 0xFFFF0000;
|
||||
cpustate->pendingAbtD = 0;
|
||||
arm->pendingAbtD = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
// FIQ
|
||||
if (cpustate->pendingFiq && (cpsr & F_MASK) == 0) {
|
||||
if (arm->pendingFiq && (cpsr & F_MASK) == 0) {
|
||||
if (MODE26) fatalerror( "pendingFiq (todo)\n");
|
||||
SwitchMode(cpustate, eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(cpustate, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */
|
||||
SwitchMode(arm, eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK | F_MASK); /* Mask both IRQ & FIQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x1c; /* IRQ Vector address */
|
||||
@ -196,12 +196,12 @@ void arm7_check_irq_state(arm_state *cpustate)
|
||||
}
|
||||
|
||||
// IRQ
|
||||
if (cpustate->pendingIrq && (cpsr & I_MASK) == 0) {
|
||||
SwitchMode(cpustate, eARM7_MODE_IRQ); /* Set IRQ mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(cpustate, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
if (arm->pendingIrq && (cpsr & I_MASK) == 0) {
|
||||
SwitchMode(arm, eARM7_MODE_IRQ); /* Set IRQ mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
if (MODE32)
|
||||
{
|
||||
SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x18; /* IRQ Vector address */
|
||||
@ -218,56 +218,56 @@ void arm7_check_irq_state(arm_state *cpustate)
|
||||
}
|
||||
|
||||
// Prefetch Abort
|
||||
if (cpustate->pendingAbtP) {
|
||||
if (arm->pendingAbtP) {
|
||||
if (MODE26) fatalerror( "pendingAbtP (todo)\n");
|
||||
SwitchMode(cpustate, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(cpustate, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */
|
||||
SwitchMode(arm, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x0c; /* IRQ Vector address */
|
||||
if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 |= 0xFFFF0000;
|
||||
cpustate->pendingAbtP = 0;
|
||||
arm->pendingAbtP = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
// Undefined instruction
|
||||
if (cpustate->pendingUnd) {
|
||||
if (arm->pendingUnd) {
|
||||
if (MODE26) fatalerror( "pendingUnd (todo)\n");
|
||||
SwitchMode(cpustate, eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */
|
||||
SwitchMode(arm, eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */
|
||||
// compensate for prefetch (should this also be done for normal IRQ?)
|
||||
if (T_IS_SET(GET_CPSR))
|
||||
{
|
||||
SET_REGISTER(cpustate, 14, pc - 4 + 2); /* save PC to R14 */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 2); /* save PC to R14 */
|
||||
}
|
||||
else
|
||||
{
|
||||
SET_REGISTER(cpustate, 14, pc - 4 + 4 - 4); /* save PC to R14 */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4 - 4); /* save PC to R14 */
|
||||
}
|
||||
SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x04; /* IRQ Vector address */
|
||||
if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 |= 0xFFFF0000;
|
||||
cpustate->pendingUnd = 0;
|
||||
arm->pendingUnd = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
// Software Interrupt
|
||||
if (cpustate->pendingSwi) {
|
||||
SwitchMode(cpustate, eARM7_MODE_SVC); /* Set SVC mode so PC is saved to correct R14 bank */
|
||||
if (arm->pendingSwi) {
|
||||
SwitchMode(arm, eARM7_MODE_SVC); /* Set SVC mode so PC is saved to correct R14 bank */
|
||||
// compensate for prefetch (should this also be done for normal IRQ?)
|
||||
if (T_IS_SET(GET_CPSR))
|
||||
{
|
||||
SET_REGISTER(cpustate, 14, pc - 4 + 2); /* save PC to R14 */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 2); /* save PC to R14 */
|
||||
}
|
||||
else
|
||||
{
|
||||
SET_REGISTER(cpustate, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
}
|
||||
if (MODE32)
|
||||
{
|
||||
SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK); /* Go to ARM mode */
|
||||
R15 = 0x08; /* Jump to the SWI vector */
|
||||
@ -280,32 +280,32 @@ void arm7_check_irq_state(arm_state *cpustate)
|
||||
SET_CPSR(temp); /* Mask IRQ */
|
||||
}
|
||||
if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 |= 0xFFFF0000;
|
||||
cpustate->pendingSwi = 0;
|
||||
arm->pendingSwi = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// CPU - SET IRQ LINE
|
||||
static void arm7_core_set_irq_line(arm_state *cpustate, int irqline, int state)
|
||||
static void arm7_core_set_irq_line(arm_state *arm, int irqline, int state)
|
||||
{
|
||||
switch (irqline) {
|
||||
case ARM7_IRQ_LINE: /* IRQ */
|
||||
cpustate->pendingIrq = state & 1;
|
||||
arm->pendingIrq = state & 1;
|
||||
break;
|
||||
|
||||
case ARM7_FIRQ_LINE: /* FIRQ */
|
||||
cpustate->pendingFiq = state & 1;
|
||||
arm->pendingFiq = state & 1;
|
||||
break;
|
||||
|
||||
case ARM7_ABORT_EXCEPTION:
|
||||
cpustate->pendingAbtD = state & 1;
|
||||
arm->pendingAbtD = state & 1;
|
||||
break;
|
||||
case ARM7_ABORT_PREFETCH_EXCEPTION:
|
||||
cpustate->pendingAbtP = state & 1;
|
||||
arm->pendingAbtP = state & 1;
|
||||
break;
|
||||
|
||||
case ARM7_UNDEFINE_EXCEPTION:
|
||||
cpustate->pendingUnd = state & 1;
|
||||
arm->pendingUnd = state & 1;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
@ -89,11 +89,11 @@ enum
|
||||
/* Undefined Mode - Bank switched registers */
|
||||
eR13_UND, eR14_UND, eSPSR_UND,
|
||||
|
||||
kNumRegisters
|
||||
NUM_REGS
|
||||
};
|
||||
|
||||
/* Coprocessor-related macros */
|
||||
#define COPRO_TLB_BASE cpustate->tlbBase
|
||||
#define COPRO_TLB_BASE arm->tlbBase
|
||||
#define COPRO_TLB_BASE_MASK 0xffffc000
|
||||
#define COPRO_TLB_VADDR_FLTI_MASK 0xfff00000
|
||||
#define COPRO_TLB_VADDR_FLTI_MASK_SHIFT 18
|
||||
@ -115,7 +115,7 @@ enum
|
||||
#define COPRO_TLB_SECTION_TABLE 2
|
||||
#define COPRO_TLB_FINE_TABLE 3
|
||||
|
||||
#define COPRO_CTRL cpustate->control
|
||||
#define COPRO_CTRL arm->control
|
||||
#define COPRO_CTRL_MMU_EN 0x00000001
|
||||
#define COPRO_CTRL_ADDRFAULT_EN 0x00000002
|
||||
#define COPRO_CTRL_DCACHE_EN 0x00000004
|
||||
@ -139,14 +139,14 @@ enum
|
||||
#define COPRO_CTRL_INTVEC_F 1
|
||||
#define COPRO_CTRL_MASK 0x0000338f
|
||||
|
||||
#define COPRO_DOMAIN_ACCESS_CONTROL cpustate->domainAccessControl
|
||||
#define COPRO_DOMAIN_ACCESS_CONTROL arm->domainAccessControl
|
||||
|
||||
#define COPRO_FAULT_STATUS_D cpustate->faultStatus[0]
|
||||
#define COPRO_FAULT_STATUS_P cpustate->faultStatus[1]
|
||||
#define COPRO_FAULT_STATUS_D arm->faultStatus[0]
|
||||
#define COPRO_FAULT_STATUS_P arm->faultStatus[1]
|
||||
|
||||
#define COPRO_FAULT_ADDRESS cpustate->faultAddress
|
||||
#define COPRO_FAULT_ADDRESS arm->faultAddress
|
||||
|
||||
#define COPRO_FCSE_PID cpustate->fcsePID
|
||||
#define COPRO_FCSE_PID arm->fcsePID
|
||||
|
||||
/* Coprocessor Registers */
|
||||
#define ARM7COPRO_REGS \
|
||||
@ -169,20 +169,28 @@ enum
|
||||
};
|
||||
|
||||
#define ARM7CORE_REGS \
|
||||
UINT32 sArmRegister[kNumRegisters]; \
|
||||
UINT8 pendingIrq; \
|
||||
UINT8 pendingFiq; \
|
||||
UINT8 pendingAbtD; \
|
||||
UINT8 pendingAbtP; \
|
||||
UINT8 pendingUnd; \
|
||||
UINT8 pendingSwi; \
|
||||
INT32 iCount; \
|
||||
UINT32 r[NUM_REGS]; \
|
||||
UINT32 pendingIrq; \
|
||||
UINT32 pendingFiq; \
|
||||
UINT32 pendingAbtD; \
|
||||
UINT32 pendingAbtP; \
|
||||
UINT32 pendingUnd; \
|
||||
UINT32 pendingSwi; \
|
||||
int icount; \
|
||||
endianness_t endian; \
|
||||
device_irq_acknowledge_callback irq_callback; \
|
||||
legacy_cpu_device *device; \
|
||||
address_space *program; \
|
||||
direct_read_data *direct;
|
||||
|
||||
//#define ARM7_USE_DRC
|
||||
|
||||
/* forward declaration of implementation-specific state */
|
||||
#ifndef ARM7_USE_DRC
|
||||
struct arm7imp_state {};
|
||||
#else
|
||||
struct arm7imp_state;
|
||||
#endif
|
||||
|
||||
/* CPU state struct */
|
||||
struct arm_state
|
||||
@ -196,6 +204,7 @@ struct arm_state
|
||||
#if ARM7_MMU_ENABLE_HACK
|
||||
UINT32 mmu_enable_addr; // workaround for "MMU is enabled when PA != VA" problem
|
||||
#endif
|
||||
arm7imp_state impstate;
|
||||
};
|
||||
|
||||
/****************************************************************************************************
|
||||
@ -493,7 +502,7 @@ enum
|
||||
#define R15 ARM7REG(eR15)
|
||||
#define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18]
|
||||
#define GET_CPSR ARM7REG(eCPSR)
|
||||
#define SET_CPSR(v) set_cpsr(cpustate,v)
|
||||
#define SET_CPSR(v) set_cpsr(arm,v)
|
||||
#define MODE_FLAG 0xF // Mode bits are 4:0 of CPSR, but we ignore bit 4.
|
||||
#define GET_MODE (GET_CPSR & MODE_FLAG)
|
||||
#define SIGN_BIT ((UINT32)(1 << 31))
|
||||
@ -502,8 +511,10 @@ enum
|
||||
#define THUMB_SIGN_BIT ((UINT32)(1 << 31))
|
||||
#define THUMB_SIGN_BITS_DIFFER(a, b) (((a)^(b)) >> 31)
|
||||
|
||||
#define MODE32 (GET_CPSR & 0x10)
|
||||
#define MODE26 (!(GET_CPSR & 0x10))
|
||||
#define SR_MODE32 0x10
|
||||
|
||||
#define MODE32 (GET_CPSR & SR_MODE32)
|
||||
#define MODE26 (!(GET_CPSR & SR_MODE32))
|
||||
#define GET_PC (MODE32 ? R15 : R15 & 0x03FFFFFC)
|
||||
|
||||
#define ARM7_TLB_ABORT_D (1 << 0)
|
||||
@ -516,18 +527,33 @@ enum
|
||||
#define SET_REGISTER(state, reg, val) SetRegister(state, reg, val)
|
||||
#define GET_MODE_REGISTER(state, mode, reg) GetModeRegister(state, mode, reg)
|
||||
#define SET_MODE_REGISTER(state, mode, reg, val) SetModeRegister(state, mode, reg, val)
|
||||
#define ARM7_CHECKIRQ arm7_check_irq_state(cpustate)
|
||||
#define ARM7_CHECKIRQ arm7_check_irq_state(arm)
|
||||
|
||||
extern write32_device_func arm7_coproc_do_callback;
|
||||
extern read32_device_func arm7_coproc_rt_r_callback;
|
||||
extern write32_device_func arm7_coproc_rt_w_callback;
|
||||
extern void arm7_dt_r_callback(arm_state *cpustate, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *cpustate, UINT32 addr));
|
||||
extern void arm7_dt_w_callback(arm_state *cpustate, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *cpustate, UINT32 addr, UINT32 data));
|
||||
extern void arm7_dt_r_callback(arm_state *arm, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *arm, UINT32 addr));
|
||||
extern void arm7_dt_w_callback(arm_state *arm, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *arm, UINT32 addr, UINT32 data));
|
||||
|
||||
#ifdef UNUSED_DEFINITION
|
||||
extern char *(*arm7_dasm_cop_dt_callback)(arm_state *cpustate, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
extern char *(*arm7_dasm_cop_rt_callback)(arm_state *cpustate, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
extern char *(*arm7_dasm_cop_do_callback)(arm_state *cpustate, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
extern char *(*arm7_dasm_cop_dt_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
extern char *(*arm7_dasm_cop_rt_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
extern char *(*arm7_dasm_cop_do_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
#endif
|
||||
|
||||
/* ARM flavors */
|
||||
enum arm_flavor
|
||||
{
|
||||
/* ARM7 variants */
|
||||
ARM_TYPE_ARM7,
|
||||
ARM_TYPE_ARM7BE,
|
||||
ARM_TYPE_ARM7500,
|
||||
ARM_TYPE_PXA255,
|
||||
ARM_TYPE_SA1110,
|
||||
|
||||
/* ARM9 variants */
|
||||
ARM_TYPE_ARM9,
|
||||
ARM_TYPE_ARM920T
|
||||
};
|
||||
|
||||
#endif /* __ARM7CORE_H__ */
|
||||
|
||||
2081
src/emu/cpu/arm7/arm7drc.c
Normal file
2081
src/emu/cpu/arm7/arm7drc.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,11 +1,11 @@
|
||||
/* ARM7 core helper Macros / Functions */
|
||||
|
||||
/* Macros that need to be defined according to the cpu implementation specific need */
|
||||
#define ARM7REG(reg) cpustate->sArmRegister[reg]
|
||||
#define ARM7_ICOUNT cpustate->iCount
|
||||
#define ARM7REG(reg) arm->r[reg]
|
||||
#define ARM7_ICOUNT arm->icount
|
||||
|
||||
|
||||
extern void SwitchMode(arm_state *cpustate, int cpsr_mode_val);
|
||||
extern void SwitchMode(arm_state *arm, int cpsr_mode_val);
|
||||
|
||||
#if 0
|
||||
#define LOG(x) mame_printf_debug x
|
||||
@ -76,17 +76,17 @@ extern void SwitchMode(arm_state *cpustate, int cpsr_mode_val);
|
||||
| (((sc) != 0) << C_BIT))); \
|
||||
R15 += 4;
|
||||
|
||||
void set_cpsr( arm_state *cpustate, UINT32 val);
|
||||
void set_cpsr( arm_state *arm, UINT32 val);
|
||||
|
||||
// used to be functions, but no longer a need, so we'll use define for better speed.
|
||||
#define GetRegister(cpustate, rIndex) ARM7REG(sRegisterTable[GET_MODE][rIndex])
|
||||
#define SetRegister(cpustate, rIndex, value) ARM7REG(sRegisterTable[GET_MODE][rIndex]) = value
|
||||
#define GetRegister(arm, rIndex) ARM7REG(sRegisterTable[GET_MODE][rIndex])
|
||||
#define SetRegister(arm, rIndex, value) ARM7REG(sRegisterTable[GET_MODE][rIndex]) = value
|
||||
|
||||
#define GetModeRegister(cpustate, mode, rIndex) ARM7REG(sRegisterTable[mode][rIndex])
|
||||
#define SetModeRegister(cpustate, mode, rIndex, value) ARM7REG(sRegisterTable[mode][rIndex]) = value
|
||||
#define GetModeRegister(arm, mode, rIndex) ARM7REG(sRegisterTable[mode][rIndex])
|
||||
#define SetModeRegister(arm, mode, rIndex, value) ARM7REG(sRegisterTable[mode][rIndex]) = value
|
||||
|
||||
int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags);
|
||||
void arm7_check_irq_state(arm_state *cpustate);
|
||||
int arm7_tlb_translate(arm_state *arm, UINT32 *addr, int flags);
|
||||
void arm7_check_irq_state(arm_state *arm);
|
||||
|
||||
typedef const void (*arm7thumb_ophandler)(arm_state*, UINT32, UINT32);
|
||||
|
||||
@ -96,71 +96,71 @@ typedef const void (*arm7ops_ophandler)(arm_state*, UINT32);
|
||||
|
||||
extern arm7ops_ophandler ops_handler[0x10];
|
||||
|
||||
extern void (*arm7_coproc_dt_r_callback)(arm_state *cpustate, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *cpustate, UINT32 addr));
|
||||
extern void (*arm7_coproc_dt_w_callback)(arm_state *cpustate, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *cpustate, UINT32 addr, UINT32 data));
|
||||
extern void (*arm7_coproc_dt_r_callback)(arm_state *arm, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *arm, UINT32 addr));
|
||||
extern void (*arm7_coproc_dt_w_callback)(arm_state *arm, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *arm, UINT32 addr, UINT32 data));
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* Default Memory Handlers
|
||||
***************************************************************************/
|
||||
INLINE void arm7_cpu_write32(arm_state *cpustate, UINT32 addr, UINT32 data)
|
||||
INLINE void arm7_cpu_write32(arm_state *arm, UINT32 addr, UINT32 data)
|
||||
{
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( cpustate, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
addr &= ~3;
|
||||
if ( cpustate->endian == ENDIANNESS_BIG )
|
||||
cpustate->program->write_dword(addr, data);
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
arm->program->write_dword(addr, data);
|
||||
else
|
||||
cpustate->program->write_dword(addr, data);
|
||||
arm->program->write_dword(addr, data);
|
||||
}
|
||||
|
||||
|
||||
INLINE void arm7_cpu_write16(arm_state *cpustate, UINT32 addr, UINT16 data)
|
||||
INLINE void arm7_cpu_write16(arm_state *arm, UINT32 addr, UINT16 data)
|
||||
{
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( cpustate, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
addr &= ~1;
|
||||
if ( cpustate->endian == ENDIANNESS_BIG )
|
||||
cpustate->program->write_word(addr, data);
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
arm->program->write_word(addr, data);
|
||||
else
|
||||
cpustate->program->write_word(addr, data);
|
||||
arm->program->write_word(addr, data);
|
||||
}
|
||||
|
||||
INLINE void arm7_cpu_write8(arm_state *cpustate, UINT32 addr, UINT8 data)
|
||||
INLINE void arm7_cpu_write8(arm_state *arm, UINT32 addr, UINT8 data)
|
||||
{
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( cpustate, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if ( cpustate->endian == ENDIANNESS_BIG )
|
||||
cpustate->program->write_byte(addr, data);
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
arm->program->write_byte(addr, data);
|
||||
else
|
||||
cpustate->program->write_byte(addr, data);
|
||||
arm->program->write_byte(addr, data);
|
||||
}
|
||||
|
||||
INLINE UINT32 arm7_cpu_read32(arm_state *cpustate, UINT32 addr)
|
||||
INLINE UINT32 arm7_cpu_read32(arm_state *arm, UINT32 addr)
|
||||
{
|
||||
UINT32 result;
|
||||
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( cpustate, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@ -168,39 +168,39 @@ INLINE UINT32 arm7_cpu_read32(arm_state *cpustate, UINT32 addr)
|
||||
|
||||
if (addr & 3)
|
||||
{
|
||||
if ( cpustate->endian == ENDIANNESS_BIG )
|
||||
result = cpustate->program->read_dword(addr & ~3);
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
result = arm->program->read_dword(addr & ~3);
|
||||
else
|
||||
result = cpustate->program->read_dword(addr & ~3);
|
||||
result = arm->program->read_dword(addr & ~3);
|
||||
result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3))));
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( cpustate->endian == ENDIANNESS_BIG )
|
||||
result = cpustate->program->read_dword(addr);
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
result = arm->program->read_dword(addr);
|
||||
else
|
||||
result = cpustate->program->read_dword(addr);
|
||||
result = arm->program->read_dword(addr);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
INLINE UINT16 arm7_cpu_read16(arm_state *cpustate, UINT32 addr)
|
||||
INLINE UINT16 arm7_cpu_read16(arm_state *arm, UINT32 addr)
|
||||
{
|
||||
UINT16 result;
|
||||
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( cpustate, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if ( cpustate->endian == ENDIANNESS_BIG )
|
||||
result = cpustate->program->read_word(addr & ~1);
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
result = arm->program->read_word(addr & ~1);
|
||||
else
|
||||
result = cpustate->program->read_word(addr & ~1);
|
||||
result = arm->program->read_word(addr & ~1);
|
||||
|
||||
if (addr & 1)
|
||||
{
|
||||
@ -210,32 +210,32 @@ INLINE UINT16 arm7_cpu_read16(arm_state *cpustate, UINT32 addr)
|
||||
return result;
|
||||
}
|
||||
|
||||
INLINE UINT8 arm7_cpu_read8(arm_state *cpustate, UINT32 addr)
|
||||
INLINE UINT8 arm7_cpu_read8(arm_state *arm, UINT32 addr)
|
||||
{
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( cpustate, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
// Handle through normal 8 bit handler (for 32 bit cpu)
|
||||
if ( cpustate->endian == ENDIANNESS_BIG )
|
||||
return cpustate->program->read_byte(addr);
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
return arm->program->read_byte(addr);
|
||||
else
|
||||
return cpustate->program->read_byte(addr);
|
||||
return arm->program->read_byte(addr);
|
||||
}
|
||||
|
||||
|
||||
/* Macros that can be re-defined for custom cpu implementations - The core expects these to be defined */
|
||||
/* In this case, we are using the default arm7 handlers (supplied by the core)
|
||||
- but simply changes these and define your own if needed for cpu implementation specific needs */
|
||||
#define READ8(addr) arm7_cpu_read8(cpustate, addr)
|
||||
#define WRITE8(addr,data) arm7_cpu_write8(cpustate, addr,data)
|
||||
#define READ16(addr) arm7_cpu_read16(cpustate, addr)
|
||||
#define WRITE16(addr,data) arm7_cpu_write16(cpustate, addr,data)
|
||||
#define READ32(addr) arm7_cpu_read32(cpustate, addr)
|
||||
#define WRITE32(addr,data) arm7_cpu_write32(cpustate, addr,data)
|
||||
#define READ8(addr) arm7_cpu_read8(arm, addr)
|
||||
#define WRITE8(addr,data) arm7_cpu_write8(arm, addr,data)
|
||||
#define READ16(addr) arm7_cpu_read16(arm, addr)
|
||||
#define WRITE16(addr,data) arm7_cpu_write16(arm, addr,data)
|
||||
#define READ32(addr) arm7_cpu_read32(arm, addr)
|
||||
#define WRITE32(addr,data) arm7_cpu_write32(arm, addr,data)
|
||||
#define PTR_READ32 &arm7_cpu_read32
|
||||
#define PTR_WRITE32 &arm7_cpu_write32
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,8 +1,8 @@
|
||||
|
||||
const void arm7ops_0123(arm_state *cpustate, UINT32 insn);
|
||||
const void arm7ops_4567(arm_state *cpustate, UINT32 insn);
|
||||
const void arm7ops_89(arm_state *cpustate, UINT32 insn);
|
||||
const void arm7ops_ab(arm_state *cpustate, UINT32 insn);
|
||||
const void arm7ops_cd(arm_state *cpustate, UINT32 insn);
|
||||
const void arm7ops_e(arm_state *cpustate, UINT32 insn);
|
||||
const void arm7ops_f(arm_state *cpustate, UINT32 insn);
|
||||
const void arm7ops_0123(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_4567(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_89(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_ab(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_cd(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_e(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_f(arm_state *arm, UINT32 insn);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,103 +1,103 @@
|
||||
|
||||
|
||||
|
||||
const void tg00_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg00_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg01_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg01_10(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg01_11(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg01_12(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg01_13(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg02_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg02_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg03_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg03_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_00(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_01(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_02(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_03(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_04(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_05(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_06(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_07(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_08(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_09(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0a(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0b(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0c(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0d(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0e(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0f(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_00(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_01(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_02(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_03(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_10(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_11(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_12(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_13(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_20(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_21(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_22(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_23(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_30(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_31(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_32(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_33(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg04_0203(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg05_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg05_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg05_2(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg05_3(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg05_4(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg05_5(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg05_6(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg05_7(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg06_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg06_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg07_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg07_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg08_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg08_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg09_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg09_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0a_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0a_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_2(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_3(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_4(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_5(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_6(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_7(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_8(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_9(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_a(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_b(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_c(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_d(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_e(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_f(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0c_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0c_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_2(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_3(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_4(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_5(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_6(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_7(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_8(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_9(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_a(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_b(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_c(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_d(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_e(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_f(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0e_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0e_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0f_0(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg0f_1(arm_state *cpustate, UINT32 pc, UINT32 insn);
|
||||
const void tg00_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg00_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_10(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_11(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_12(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_13(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg02_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg02_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg03_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg03_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_00(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_01(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_02(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_03(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_04(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_05(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_06(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_07(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_08(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_09(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0a(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0b(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0c(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0d(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0e(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0f(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_00(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_01(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_02(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_03(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_10(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_11(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_12(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_13(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_20(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_21(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_22(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_23(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_30(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_31(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_32(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_33(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_0203(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_2(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_3(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_4(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_5(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_6(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_7(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg06_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg06_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg07_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg07_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg08_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg08_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg09_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg09_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0a_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0a_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_2(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_3(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_4(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_5(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_6(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_7(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_8(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_9(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_a(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_b(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_c(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_d(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_e(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_f(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0c_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0c_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_2(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_3(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_4(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_5(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_6(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_7(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_8(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_9(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_a(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_b(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_c(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_d(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_e(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_f(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0e_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0e_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0f_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0f_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user