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Merge pull request #1055 from JoakimLarsson/s4_75_sccbug_2
Fixed problem with dropped characters for Sun4_75
This commit is contained in:
R. Belmont
GitHub
commit
d252e41b4f
@ -1580,27 +1580,50 @@ void z80scc_channel::do_sccreg_wr3(UINT8 data)
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LOG(("- Receiver Enable %u\n", (data & WR3_RX_ENABLE) ? 1 : 0));
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LOG(("- Auto Enables %u\n", (data & WR3_AUTO_ENABLES) ? 1 : 0));
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LOG(("- Receiver Bits/Character %u\n", get_rx_word_length()));
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update_serial();
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receive_register_reset();
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}
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void z80scc_channel::do_sccreg_wr4(UINT8 data)
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{
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LOG(("%s(%02x) Setting up asynchronous frame format and clock\n", FUNCNAME, data));
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m_wr4 = data;
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LOG(("- Parity Enable %u\n", (data & WR4_PARITY_ENABLE) ? 1 : 0));
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LOG(("- Parity %s\n", (data & WR4_PARITY_EVEN) ? "Even" : "Odd"));
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LOG(("- Stop Bits %s\n", stop_bits_tostring(get_stop_bits())));
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LOG(("- Clock Mode %uX\n", get_clock_mode()));
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if (data == m_wr4)
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{
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logerror("- supressing reinit of Tx as write to wr4 is identical to previous value\n");
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}
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else
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{
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m_wr4 = data;
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LOG(("- Parity Enable %u\n", (data & WR4_PARITY_ENABLE) ? 1 : 0));
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LOG(("- Parity %s\n", (data & WR4_PARITY_EVEN) ? "Even" : "Odd"));
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LOG(("- Stop Bits %s\n", stop_bits_tostring(get_stop_bits())));
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LOG(("- Clock Mode %uX\n", get_clock_mode()));
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update_serial();
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safe_transmit_register_reset();
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receive_register_reset();
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}
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}
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void z80scc_channel::do_sccreg_wr5(UINT8 data)
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{
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LOG(("%s(%02x) Setting up the transmitter\n", FUNCNAME, data));
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m_wr5 = data;
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LOG(("- Transmitter Enable %u\n", (data & WR5_TX_ENABLE) ? 1 : 0));
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LOG(("- Transmitter Bits/Character %u\n", get_tx_word_length()));
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LOG(("- Send Break %u\n", (data & WR5_SEND_BREAK) ? 1 : 0));
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LOG(("- Request to Send %u\n", (data & WR5_RTS) ? 1 : 0));
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LOG(("- Data Terminal Ready %u\n", (data & WR5_DTR) ? 1 : 0));
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if (data == m_wr5)
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{
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logerror("- supressing reinit of Tx as write to wr5 is identical to previous value\n");
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}
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else
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{
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m_wr5 = data;
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LOG(("- Transmitter Enable %u\n", (data & WR5_TX_ENABLE) ? 1 : 0));
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LOG(("- Transmitter Bits/Character %u\n", get_tx_word_length()));
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LOG(("- Send Break %u\n", (data & WR5_SEND_BREAK) ? 1 : 0));
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LOG(("- Request to Send %u\n", (data & WR5_RTS) ? 1 : 0));
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LOG(("- Data Terminal Ready %u\n", (data & WR5_DTR) ? 1 : 0));
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update_serial();
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safe_transmit_register_reset();
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update_rts();
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m_rr0 |= RR0_TX_BUFFER_EMPTY;
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}
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}
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void z80scc_channel::do_sccreg_wr6(UINT8 data)
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@ -1929,37 +1952,22 @@ void z80scc_channel::control_write(UINT8 data)
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/* TODO. Sort out 80X30 & other SCC variants limitations in register access */
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switch (reg)
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{
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case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); ;break;
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case REG_WR1_INT_DMA_ENABLE: do_sccreg_wr1(data); m_uart->check_interrupts(); break;
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case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break;
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case REG_WR3_RX_CONTROL:
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do_sccreg_wr3(data);
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update_serial();
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receive_register_reset();
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break;
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case REG_WR4_RX_TX_MODES:
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do_sccreg_wr4(data);
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update_serial();
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transmit_register_reset();
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receive_register_reset();
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break;
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case REG_WR5_TX_CONTROL:
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do_sccreg_wr5(data);
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update_serial();
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transmit_register_reset();
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update_rts();
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m_rr0 |= RR0_TX_BUFFER_EMPTY;
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break;
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case REG_WR6_SYNC_OR_SDLC_A: do_sccreg_wr6(data); break;
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case REG_WR7_SYNC_OR_SDLC_F: do_sccreg_wr7(data); break;
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case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break;
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case REG_WR9_MASTER_INT_CTRL: do_sccreg_wr9(data); break;
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case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break;
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case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break;
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case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break;
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case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break;
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case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break;
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case REG_WR15_EXT_ST_INT_CTRL:do_sccreg_wr15(data); break;
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case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); ;break;
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case REG_WR1_INT_DMA_ENABLE: do_sccreg_wr1(data); m_uart->check_interrupts(); break;
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case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break;
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case REG_WR3_RX_CONTROL: do_sccreg_wr3(data); break;
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case REG_WR4_RX_TX_MODES: do_sccreg_wr4(data); break;
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case REG_WR5_TX_CONTROL: do_sccreg_wr5(data); break;
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case REG_WR6_SYNC_OR_SDLC_A: do_sccreg_wr6(data); break;
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case REG_WR7_SYNC_OR_SDLC_F: do_sccreg_wr7(data); break;
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case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break;
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case REG_WR9_MASTER_INT_CTRL: do_sccreg_wr9(data); break;
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case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break;
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case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break;
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case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break;
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case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break;
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case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break;
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case REG_WR15_EXT_ST_INT_CTRL: do_sccreg_wr15(data); break;
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default:
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logerror("\"%s\": %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
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}
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@ -2342,6 +2350,27 @@ WRITE_LINE_MEMBER( z80scc_channel::txc_w )
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}
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}
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//--------------------------------------------------------------------------------------------------------
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// safe_transmit_register_reset - wait for the transmitter shift register to be
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// emptied before apply the new value of wr5 and/or wr4. In the case of a Tx FIFO
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// the change will occur before next character is started. From the specification:
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//
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// "The character length may be changed on the fly, but the desired length must be selected before the
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// character is loaded into the Transmit Shift register from the transmit data FIFO. The easiest way to
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// ensure this is to write to WR5 to change the character length before writing the data to the transmit
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// buffer."
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//
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// Right now we only detect the problem and log an error
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//---------------------------------------------------------------------------------------------------------
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void z80scc_channel::safe_transmit_register_reset()
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{
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if (!is_transmit_register_empty())
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{
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logerror("Attempt to reset transmit shift register while busy detected, please report\n");
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}
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transmit_register_reset();
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}
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//-------------------------------------------------
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// update_serial -
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//-------------------------------------------------
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@ -534,6 +534,7 @@ protected:
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stop_bits_t get_stop_bits();
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int get_rx_word_length();
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int get_tx_word_length();
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void safe_transmit_register_reset();
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// receiver state
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UINT8 m_rx_data_fifo[8]; // receive data FIFO
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@ -664,9 +665,11 @@ protected:
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void reset_interrupts();
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UINT8 modify_vector(UINT8 vect, int i, UINT8 src);
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void trigger_interrupt(int index, int state);
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int get_channel_index(z80scc_channel *ch) { return (ch == m_chanA) ? 0 : 1; }
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// Variants in the SCC family
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// Variants in the SCC family
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enum
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{
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TYPE_Z80SCC = 0x001,
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