mirror of
https://github.com/holub/mame
synced 2025-07-04 01:18:59 +03:00
r9751: Fix floppy disk access and add log defines
This commit is contained in:
Brandon Munger
parent
ce577865e7
commit
d256291daf
@ -22,6 +22,11 @@
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#define HDC_TAG "hdc"
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#define FDCDMA_TAG "i8237dma"
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#define TRACE_PDC_FDC 0
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#define TRACE_PDC_HDC 0
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#define TRACE_PDC_DMA 0
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#define TRACE_PDC_CMD 0
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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@ -65,9 +70,10 @@ static ADDRESS_MAP_START( pdc_io, AS_IO, 8, pdc_device )
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AM_RANGE(0x21, 0x2F) AM_READWRITE(fdd_68k_r,fdd_68k_w) AM_MIRROR(0xFF00)
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AM_RANGE(0x38, 0x38) AM_READ(p38_r) AM_MIRROR(0xFF00) // Possibly UPD765 interrupt
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AM_RANGE(0x39, 0x39) AM_READ(p39_r) AM_MIRROR(0xFF00) // HDD related
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AM_RANGE(0x3c, 0x3d) AM_READ(ds_r) AM_MIRROR(0xFF00) // Dipswitches??
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AM_RANGE(0x40, 0x41) AM_DEVREADWRITE(HDC_TAG, hdc9224_device,read,write) AM_MIRROR(0xFF00)
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AM_RANGE(0x42, 0x43) AM_DEVICE(FDC_TAG, upd765a_device, map) AM_MIRROR(0xFF00)
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AM_RANGE(0x50, 0x53) AM_WRITE(p50_53_w) AM_MIRROR(0xFF00)
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AM_RANGE(0x50, 0x5f) AM_WRITE(p50_5f_w) AM_MIRROR(0xFF00)
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AM_RANGE(0x60, 0x6f) AM_DEVREADWRITE(FDCDMA_TAG,am9517a_device,read,write) AM_MIRROR(0xFF00)
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ADDRESS_MAP_END
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@ -116,7 +122,6 @@ static MACHINE_CONFIG_FRAGMENT( pdc )
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// Floppy disk drive
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MCFG_FLOPPY_DRIVE_ADD(FDC_TAG":0", pdc_floppies, "35hd", pdc_device::floppy_formats)
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//MCFG_FLOPPY_DRIVE_ADD(FDC_TAG":0", pdc_floppies, "35hd", floppy_image_device::default_floppy_formats)
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/* DMA Controller - Intel P8237A-5 */
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/* Channel 0: uPD765a Floppy Disk Controller */
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@ -130,7 +135,6 @@ static MACHINE_CONFIG_FRAGMENT( pdc )
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MCFG_I8237_OUT_IOW_0_CB(WRITE8(pdc_device, i8237_fdc_dma_w))
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MCFG_I8237_IN_IOR_1_CB(READ8(pdc_device, m68k_dma_r))
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MCFG_I8237_OUT_IOW_1_CB(WRITE8(pdc_device, m68k_dma_w))
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// MCFG_AM9517A_OUT_DACK_0_CB(WRITELINE(pdc_device, fdc_dack_w))
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/* Hard Disk Controller - HDC9224 */
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MCFG_DEVICE_ADD(HDC_TAG, HDC9224, 0)
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@ -160,8 +164,6 @@ pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t
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m_pdccpu(*this, Z80_TAG),
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m_dma8237(*this, FDCDMA_TAG),
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m_fdc(*this, FDC_TAG),
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//m_floppy(*this, FDC_TAG ":0"),
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//m_floppy(*this, FDC_TAG ":0:35hd"),
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m_hdc9224(*this, HDC_TAG),
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m_pdc_ram(*this, "pdc_ram"),
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m_m68k_r_cb(*this),
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@ -175,10 +177,6 @@ pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t
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void pdc_device::device_start()
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{
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// m_fdc->set_floppy(m_floppy);
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// floppy_image_device *m_floppy;
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// m_floppy = machine().device<floppy_connector>("fdc:0")->get_device();
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}
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//-------------------------------------------------
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@ -191,11 +189,6 @@ void pdc_device::device_reset()
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reg_p38 = 0;
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reg_p38 |= 4; /* ready for 68k ram DMA */
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//reg_p38 |= 0x20; // no idea at all - bit 5 (32)
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//m_fdc->ready_w(true);
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//m_floppy->mon_w(0);
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//m_fdc->set_floppy(m_floppy);
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//m_fdc->tc_w(1);
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//m_floppy->ready_w(true);
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/* Reset CPU */
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m_pdccpu->reset();
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@ -204,8 +197,6 @@ void pdc_device::device_reset()
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m_m68k_r_cb.resolve_safe(0);
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m_m68k_w_cb.resolve_safe();
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//machine().device<floppy_connector>(FDC_TAG":0")->get_device()->mon_w(false);
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//subdevice<floppy_connector>("fdc:0")->get_device()->mon_w(true);
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m_fdc->set_rate(500000) ;
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}
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@ -239,13 +230,13 @@ WRITE8_MEMBER(pdc_device::i8237_dma_mem_w)
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READ8_MEMBER(pdc_device::i8237_fdc_dma_r)
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{
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UINT8 ret = m_fdc->dma_r();
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logerror("PDC: 8237 DMA CHANNEL 0 READ ADDRESS: %08X, DATA: %02X\n", offset, ret );
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if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 0 READ ADDRESS: %08X, DATA: %02X\n", offset, ret );
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return ret;
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}
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WRITE8_MEMBER(pdc_device::i8237_fdc_dma_w)
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{
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logerror("PDC: 8237 DMA CHANNEL 0 WRITE ADDRESS: %08X, DATA: %02X\n", offset, data );
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if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 0 WRITE ADDRESS: %08X, DATA: %02X\n", offset, data );
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m_fdc->dma_w(data);
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}
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@ -254,17 +245,17 @@ READ8_MEMBER(pdc_device::m68k_dma_r)
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UINT32 address;
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UINT8 data;
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address = fdd_68k_dma_r_address++;
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address = fdd_68k_dma_address++;
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data = m_m68k_r_cb(address);
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logerror("PDC: 8237 DMA CHANNEL 1 READ ADDRESS: %08X, DATA: %02X\n", address, data );
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if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 1 READ ADDRESS: %08X, DATA: %02X\n", address, data );
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return data;
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}
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WRITE8_MEMBER(pdc_device::m68k_dma_w)
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{
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logerror("PDC: 8237 DMA CHANNEL 1 WRITE ADDRESS: %08X, DATA: %02X\n", fdd_68k_dma_w_address, data );
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if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 1 WRITE ADDRESS: %08X, DATA: %02X\n", fdd_68k_dma_address, data );
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m_m68k_w_cb(data);
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fdd_68k_dma_w_address++;
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fdd_68k_dma_address++;
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}
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WRITE_LINE_MEMBER(pdc_device::hdd_irq)
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@ -281,27 +272,25 @@ READ8_MEMBER(pdc_device::p0_7_r)
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switch(offset)
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{
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case 0: /* Port 0: Old style command low byte [0x5FF041B0] */
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logerror("PDC: Port 0x00 READ: %02X\n", reg_p0);
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if(TRACE_PDC_CMD) logerror("PDC: Port 0x00 READ: %02X\n", reg_p0);
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return reg_p0;
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case 1: /* Port 1: Old style command high byte [0x5FF041B0] */
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logerror("PDC: Port 0x01 READ: %02X\n", reg_p1);
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if(TRACE_PDC_CMD) logerror("PDC: Port 0x01 READ: %02X\n", reg_p1);
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return reg_p1;
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case 2: /* Port 2: FDD command address low byte [0x5FF0C0B0][0x5FF0C1B0] */
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logerror("PDC: Port 0x02 READ: %02X\n", reg_p2);
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fdd_68k_dma_r_address = (fdd_68k_dma_r_address & (0xFF<<9)) | (reg_p2 << 1);
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x02 READ: %02X\n", reg_p2);
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return reg_p2;
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case 3: /* Port 3: FDD command address high byte [0x5FF0C0B0][0x5FF0C1B0] */
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logerror("PDC: Port 0x03 READ: %02X\n", reg_p3);
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fdd_68k_dma_r_address = (fdd_68k_dma_r_address & (0xFF<<1)) | (reg_p3 << 9);
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x03 READ: %02X\n", reg_p3);
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return reg_p3;
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case 6: /* Port 6: FDD data destination address low byte [0x5FF080B0] */
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logerror("PDC: Port 0x06 READ: %02X\n", reg_p6);
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x06 READ: %02X\n", reg_p6);
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return reg_p6;
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case 7: /* Port 7: FDD data destination address high byte [0x5FF080B0] */
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logerror("PDC: Port 0x07 READ: %02X\n", reg_p7);
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x07 READ: %02X\n", reg_p7);
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return reg_p7;
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default:
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logerror("(!)PDC: Port %02X READ: \n", offset);
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if(TRACE_PDC_CMD) logerror("(!)PDC: Port %02X READ: \n", offset);
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return 0;
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}
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}
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@ -311,15 +300,15 @@ WRITE8_MEMBER(pdc_device::p0_7_w)
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switch(offset)
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{
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case 4: /* Port 4: FDD command completion status low byte [0x5FF030B0] */
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logerror("PDC: Port 0x04 WRITE: %02X\n", data);
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x04 WRITE: %02X\n", data);
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reg_p4 = data;
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break;
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case 5: /* Port 5: FDD command completion status high byte [0x5FF030B0] */
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logerror("PDC: Port 0x05 WRITE: %02X\n", data);
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x05 WRITE: %02X\n", data);
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reg_p5 = data;
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break;
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default:
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logerror("(!)PDC: Port %02X WRITE: %02X\n", offset, data);
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if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X WRITE: %02X\n", offset, data);
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break;
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}
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}
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@ -330,7 +319,7 @@ READ8_MEMBER(pdc_device::fdd_68k_r)
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switch(address)
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{
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default:
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logerror("(!)PDC: Port %02X READ: \n", address);
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if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X READ: \n", address);
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return 0;
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}
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}
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@ -340,20 +329,20 @@ WRITE8_MEMBER(pdc_device::fdd_68k_w)
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switch(address)
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{
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case 0x21: /* Port 21: ?? */
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logerror("PDC: Port 0x21 WRITE: %02X\n", data);
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logerror("PDC: Resetting 0x38 bit 1\n");
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x21 WRITE: %02X\n", data);
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if(TRACE_PDC_FDC) logerror("PDC: Resetting 0x38 bit 1\n");
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reg_p38 &= ~2; // Clear bit 1
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reg_p21 = data;
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break;
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case 0x23: /* Port 23: FDD 68k DMA high byte */
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/* The address is << 1 on the 68k side */
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fdd_68k_dma_w_address = (fdd_68k_dma_w_address & (0xFF<<1)) | (data << 9);
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logerror("PDC: Port %02X WRITE: %02X\n", address, data);
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fdd_68k_dma_address = (fdd_68k_dma_address & (0xFF<<1)) | (data << 9);
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if(TRACE_PDC_FDC) logerror("PDC: Port %02X WRITE: %02X\n", address, data);
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break;
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case 0x24: /* Port 24: FDD 68k DMA low byte */
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/* The address is << 1 on the 68k side */
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fdd_68k_dma_w_address = (fdd_68k_dma_w_address & (0xFF<<9)) | (data << 1);
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logerror("PDC: Port %02X WRITE: %02X\n", address, data);
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fdd_68k_dma_address = (fdd_68k_dma_address & (0xFF<<9)) | (data << 1);
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if(TRACE_PDC_FDC) logerror("PDC: Port %02X WRITE: %02X\n", address, data);
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break;
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case 0x26:
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switch(data)
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@ -361,7 +350,7 @@ WRITE8_MEMBER(pdc_device::fdd_68k_w)
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case 0x80:
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m_dma8237->dreq1_w(1);
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reg_p38 &= ~4; // Clear bit 4
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logerror("PDC: Port 0x26 WRITE: 0x80, DMA REQ CH 1\n");
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if(TRACE_PDC_DMA) logerror("PDC: Port 0x26 WRITE: 0x80, DMA REQ CH 1\n");
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break;
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}
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break;
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@ -370,19 +359,19 @@ WRITE8_MEMBER(pdc_device::fdd_68k_w)
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{
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case 0xFF:
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m_dma8237->dreq1_w(0);
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logerror("PDC: Port 0x2C WRITE: 0xFF, DMA REQ CH 1 OFF\n");
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if(TRACE_PDC_DMA) logerror("PDC: Port 0x2C WRITE: 0xFF, DMA REQ CH 1 OFF\n");
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break;
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}
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break;
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default:
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logerror("(!)PDC: Port %02X WRITE: %02X, PC: %X\n", address, data, space.device().safe_pc());
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if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X WRITE: %02X, PC: %X\n", address, data, space.device().safe_pc());
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break;
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}
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}
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WRITE8_MEMBER(pdc_device::p38_w)
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{
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logerror("PDC: Port 0x38 WRITE: %i\n", data);
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if(TRACE_PDC_CMD) logerror("PDC: Port 0x38 WRITE: %i\n", data);
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//reg_p38 |= data;
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reg_p38 = data;
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}
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@ -390,11 +379,7 @@ WRITE8_MEMBER(pdc_device::p38_w)
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READ8_MEMBER(pdc_device::p38_r)
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{
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reg_p38 ^= 0x20; /* Invert bit 5 (32) */
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//UINT8 retn;
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logerror("PDC: Port 0x38 READ: %02X, PC: %X\n", reg_p38, space.device().safe_pc());
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//retn = reg_p38;
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//reg_p38 &= ~2; // Clear bit 1
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//return retn;
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if(TRACE_PDC_CMD) logerror("PDC: Port 0x38 READ: %02X, PC: %X\n", reg_p38, space.device().safe_pc());
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return reg_p38;
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}
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@ -402,27 +387,75 @@ READ8_MEMBER(pdc_device::p39_r)
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{
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UINT8 data = 1;
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if(b_fdc_irq) data |= 8; // Set bit 3
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logerror("PDC: Port 0x39 READ: %02X, PC: %X\n", data, space.device().safe_pc());
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if(TRACE_PDC_CMD) logerror("PDC: Port 0x39 READ: %02X, PC: %X\n", data, space.device().safe_pc());
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return data;
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}
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WRITE8_MEMBER(pdc_device::p50_53_w)
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WRITE8_MEMBER(pdc_device::p50_5f_w)
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{
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UINT8 address = 0x50 + offset;
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switch(address)
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{
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case 0x53: /* Port 53: Almost certainly not FDD motor control, but seems to work */
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case 0x52:
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switch(data)
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{
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case 0x00:
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if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor off.\n");
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m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(1);
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break;
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case 0x80:
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logerror("PDC: FDD Motor on.\n");
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if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor on.\n");
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m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0);
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break;
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default:
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logerror("PDC: Port 0x53 WRITE: %x\n", data);
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x52 WRITE: %x\n", data);
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}
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break;
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case 0x53: /* Probably set_rate here */
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x53 WRITE: %x\n", data);
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break;
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case 0x54: /* Port 54: FDD Unit 1 Motor control */
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switch(data)
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{
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case 0x00:
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if(TRACE_PDC_FDC) logerror("PDC: FDD 1 Motor off.\n");
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m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(1);
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break;
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case 0x80:
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if(TRACE_PDC_FDC) logerror("PDC: FDD 1 Motor on.\n");
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m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0);
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break;
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default:
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if(TRACE_PDC_FDC) logerror("PDC: Port 0x54 WRITE: %x\n", data);
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}
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break;
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case 0x55: /* Port 54: FDD Unit 2 Motor control */
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if(TRACE_PDC_FDC) logerror("PDC: FDD 2 motor control: %02X\n", data);
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break;
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case 0x56: /* Port 54: FDD Unit 3 Motor control */
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if(TRACE_PDC_FDC) logerror("PDC: FDD 3 motor control: %02X\n", data);
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break;
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case 0x57: /* Port 54: FDD Unit 4 Motor control */
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if(TRACE_PDC_FDC) logerror("PDC: FDD 4 motor control: %02X\n", data);
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break;
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default:
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logerror("PDC: Port %02x WRITE: %x\n", address, data);
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if(TRACE_PDC_FDC) logerror("PDC: Port %02x WRITE: %x\n", address, data);
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}
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}
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READ8_MEMBER(pdc_device::ds_r)
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{
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switch(offset)
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{
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case 0x00:
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logerror("PDC: Dipswitch %02X READ\n", offset);
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return 0xFE;
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break;
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case 0x01:
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logerror("PDC: Dipswitch %02X READ\n", offset);
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return 0x0;
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break;
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default:
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return 0;
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}
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}
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@ -62,8 +62,9 @@ public:
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DECLARE_WRITE8_MEMBER(p38_w);
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DECLARE_READ8_MEMBER(p38_r);
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DECLARE_READ8_MEMBER(p39_r);
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DECLARE_WRITE8_MEMBER(p50_53_w);
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DECLARE_WRITE8_MEMBER(p50_5f_w);
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|
||||
DECLARE_READ8_MEMBER(ds_r); // Dip switches???
|
||||
DECLARE_READ8_MEMBER(m68k_dma_r);
|
||||
DECLARE_WRITE8_MEMBER(m68k_dma_w);
|
||||
|
||||
@ -81,8 +82,7 @@ public:
|
||||
UINT8 reg_p7;
|
||||
UINT8 reg_p21;
|
||||
UINT8 reg_p38;
|
||||
UINT32 fdd_68k_dma_r_address; /* m68k -> FDD DMA read address */
|
||||
UINT32 fdd_68k_dma_w_address; /* FDD -> m68k DMA write address */
|
||||
UINT32 fdd_68k_dma_address; /* FDD <-> m68k DMA read/write address */
|
||||
protected:
|
||||
/* Device-level overrides */
|
||||
virtual void device_start();
|
||||
|
||||
@ -44,6 +44,13 @@
|
||||
|
||||
#define TERMINAL_TAG "terminal"
|
||||
|
||||
/* Log defines */
|
||||
#define TRACE_FDC 0
|
||||
#define TRACE_HDC 0
|
||||
#define TRACE_SMIOC 0
|
||||
#define TRACE_CPU_REG 0
|
||||
#define TRACE_LED 0
|
||||
|
||||
class r9751_state : public driver_device
|
||||
{
|
||||
public:
|
||||
@ -110,7 +117,7 @@ READ8_MEMBER(r9751_state::pdc_dma_r)
|
||||
WRITE8_MEMBER(r9751_state::pdc_dma_w)
|
||||
{
|
||||
/* NOTE: This needs to be changed to a function that accepts an address and data */
|
||||
m_maincpu->space(AS_PROGRAM).write_byte(m_pdc->fdd_68k_dma_w_address,data);
|
||||
m_maincpu->space(AS_PROGRAM).write_byte(m_pdc->fdd_68k_dma_address,data);
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(r9751_state,r9751)
|
||||
@ -153,7 +160,7 @@ READ32_MEMBER( r9751_state::r9751_mmio_5ff_r )
|
||||
break;
|
||||
case 0x5FF03024: /* HDD SCSI command completed successfully */
|
||||
data = 0x1;
|
||||
logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
if(TRACE_HDC) logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
return data;
|
||||
break;
|
||||
/* SMIOC region (0x98, device 26) */
|
||||
@ -165,19 +172,15 @@ READ32_MEMBER( r9751_state::r9751_mmio_5ff_r )
|
||||
return 0x10;
|
||||
break;
|
||||
case 0x5FF010B0: /* Clear 5FF030B0 ?? */
|
||||
//m_pdc->reg_p4 = 0;
|
||||
//m_pdc->reg_p5 = 0;
|
||||
//logerror("--- FDD 0x5FF010B0 READ (0) - CLEARING 0x5FF30B0 (PDC 0x4, 0x5)\n");
|
||||
logerror("--- FDD 0x5FF010B0 READ (0)\n");
|
||||
if(TRACE_FDC) logerror("--- FDD 0x5FF010B0 READ (0)\n");
|
||||
return 0;
|
||||
case 0x5FF030B0: /* FDD command completion status */
|
||||
data = (m_pdc->reg_p5 << 8) + m_pdc->reg_p4;
|
||||
logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
return data;
|
||||
//return m_pdc->reg_p21;
|
||||
break;
|
||||
default:
|
||||
logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, 0, mem_mask);
|
||||
if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, 0, mem_mask);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
@ -191,24 +194,24 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
|
||||
{
|
||||
/* PDC HDD region (0x24, device 9 */
|
||||
case 0x5FF00224: /* HDD SCSI read command */
|
||||
logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF08024: /* HDD SCSI read command */
|
||||
logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF0C024: /* HDD SCSI read command */
|
||||
logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
/* SMIOC region (0x98, device 26) */
|
||||
case 0x5FF04098: /* Serial DMA Command */
|
||||
switch(data)
|
||||
{
|
||||
case 0x4100: /* Send byte to serial */
|
||||
logerror("Serial byte: %02X\n", m_mem->read_dword(smioc_out_addr));
|
||||
if(TRACE_SMIOC) logerror("Serial byte: %02X\n", m_mem->read_dword(smioc_out_addr));
|
||||
m_terminal->write(space,0,m_mem->read_dword(smioc_out_addr));
|
||||
break;
|
||||
default:
|
||||
logerror("Uknown serial DMA command: %X\n", data);
|
||||
if(TRACE_SMIOC) logerror("Uknown serial DMA command: %X\n", data);
|
||||
}
|
||||
break;
|
||||
case 0x5FF0C098: /* Serial DMA output address */
|
||||
@ -216,18 +219,16 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
|
||||
break;
|
||||
/* PDC FDD region (0xB0, device 44 */
|
||||
case 0x5FF001B0: /* FDD SCSI read command */
|
||||
logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF002B0: /* FDD SCSI read command */
|
||||
logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF008B0: /* FDD SCSI read command */
|
||||
logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF041B0: /* Unknown - Probably old style commands */
|
||||
logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
//UINT8 data_b0;
|
||||
//UINT8 data_b1;
|
||||
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
|
||||
/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5)*/
|
||||
m_pdc->reg_p4 = 0;
|
||||
@ -238,11 +239,11 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
|
||||
m_pdc->reg_p0 = data_b0;
|
||||
m_pdc->reg_p1 = data_b1;
|
||||
m_pdc->reg_p38 |= 0x2; /* Set bit 1 on port 38 register, PDC polls this port looking for a command */
|
||||
logerror("--- FDD Old Command: %02X and %02X\n", data_b0, data_b1);
|
||||
if(TRACE_FDC) logerror("--- FDD Old Command: %02X and %02X\n", data_b0, data_b1);
|
||||
break;
|
||||
case 0x5FF080B0: /* fdd_dest_address register */
|
||||
fdd_dest_address = data << 1;
|
||||
logerror("--- FDD destination address: %08X\n", fdd_dest_address);
|
||||
if(TRACE_FDC) logerror("--- FDD destination address: %08X\n", fdd_dest_address);
|
||||
data_b0 = data & 0xFF;
|
||||
data_b1 = (data & 0xFF00) >> 8;
|
||||
m_pdc->reg_p6 = data_b0;
|
||||
@ -252,8 +253,6 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
|
||||
case 0x5FF0C1B0: /* FDD command address register */
|
||||
UINT32 fdd_scsi_command;
|
||||
UINT32 fdd_scsi_command2;
|
||||
//UINT8 data_b0;
|
||||
//UINT8 data_b1;
|
||||
unsigned char c_fdd_scsi_command[8]; // Array for SCSI command
|
||||
int scsi_lba; // FDD LBA location here, extracted from command
|
||||
|
||||
@ -262,7 +261,7 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
|
||||
m_pdc->reg_p5 = 0;
|
||||
|
||||
/* Send FDD SCSI command location address to PDC 0x2, 0x3 */
|
||||
logerror("--- FDD command address: %08X\n", data);
|
||||
if(TRACE_FDC) logerror("--- FDD command address: %08X\n", data);
|
||||
data_b0 = data & 0xFF;
|
||||
data_b1 = (data & 0xFF00) >> 8;
|
||||
m_pdc->reg_p2 = data_b0;
|
||||
@ -274,20 +273,23 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
|
||||
memcpy(c_fdd_scsi_command,&fdd_scsi_command,4);
|
||||
memcpy(c_fdd_scsi_command+4,&fdd_scsi_command2,4);
|
||||
|
||||
logerror("--- FDD SCSI Command: ");
|
||||
for(int i = 0; i < 8; i++)
|
||||
logerror("%02X ", c_fdd_scsi_command[i]);
|
||||
logerror("\n");
|
||||
if(TRACE_FDC)
|
||||
{
|
||||
logerror("--- FDD SCSI Command: ");
|
||||
for(int i = 0; i < 8; i++)
|
||||
logerror("%02X ", c_fdd_scsi_command[i]);
|
||||
logerror("\n");
|
||||
}
|
||||
|
||||
scsi_lba = c_fdd_scsi_command[3] | (c_fdd_scsi_command[2]<<8) | ((c_fdd_scsi_command[1]&0x1F)<<16);
|
||||
logerror("--- FDD SCSI LBA: %i\n", scsi_lba);
|
||||
if(TRACE_FDC) logerror("--- FDD SCSI LBA: %i\n", scsi_lba);
|
||||
|
||||
m_pdc->reg_p38 |= 0x2; // Set bit 1 on port 38 register, PDC polls this port looking for a command
|
||||
logerror("--- FDD SET PDC Port 38: %X\n",m_pdc->reg_p38);
|
||||
if(TRACE_FDC)logerror("--- FDD SET PDC Port 38: %X\n",m_pdc->reg_p38);
|
||||
break;
|
||||
|
||||
default:
|
||||
logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
@ -322,7 +324,7 @@ READ32_MEMBER( r9751_state::r9751_mmio_ff05_r )
|
||||
break;
|
||||
default:
|
||||
data = 0;
|
||||
logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
return data;
|
||||
}
|
||||
}
|
||||
@ -338,11 +340,12 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_ff05_w )
|
||||
return;
|
||||
break;
|
||||
case 0xFF05000C: /* CPU LED hex display indicator */
|
||||
logerror("\n*** LED: %02x, Instruction: %08x ***\n\n", data, space.machine().firstcpu->pc());
|
||||
if(TRACE_LED) logerror("\n*** LED: %02x, Instruction: %08x ***\n\n", data, space.machine().firstcpu->pc());
|
||||
return;
|
||||
break;
|
||||
default:
|
||||
logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
@ -358,7 +361,7 @@ READ32_MEMBER( r9751_state::r9751_mmio_fff8_r )
|
||||
break;
|
||||
default:
|
||||
data = 0;
|
||||
logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
return data;
|
||||
}
|
||||
}
|
||||
@ -374,7 +377,7 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_fff8_w )
|
||||
return;
|
||||
break;
|
||||
default:
|
||||
logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user