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i8275: Simplify read/write handlers (nw)

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This commit is contained in:
AJR 2019-10-05 01:09:18 -04:00
parent 52cd97b79a
commit d2d205a57d
14 changed files with 47 additions and 53 deletions
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8
src/devices/video/i8275.cpp
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@ -469,7 +469,7 @@ void i8275_device::device_timer(emu_timer &timer, device_timer_id id, int param,
// read -
//-------------------------------------------------
READ8_MEMBER( i8275_device::read )
uint8_t i8275_device::read(offs_t offset)
{
if (offset & 0x01)
{
@ -510,7 +510,7 @@ READ8_MEMBER( i8275_device::read )
// write -
//-------------------------------------------------
WRITE8_MEMBER( i8275_device::write )
void i8275_device::write(offs_t offset, uint8_t data)
{
if (offset & 0x01)
{
@ -624,9 +624,9 @@ WRITE8_MEMBER( i8275_device::write )
// dack_w -
//-------------------------------------------------
WRITE8_MEMBER( i8275_device::dack_w )
void i8275_device::dack_w(uint8_t data)
{
//LOG("I8275 y %u x %u DACK %04x:%02x %u (%u)\n", screen().vpos(), screen().hpos(), offset, data, m_buffer_idx, m_dma_idx);
//LOG("I8275 y %u x %u DACK %02x %u (%u)\n", screen().vpos(), screen().hpos(), data, m_buffer_idx, m_dma_idx);
m_write_drq(0);

6
src/devices/video/i8275.h
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@ -83,10 +83,10 @@ public:
auto vrtc_wr_callback() { return m_write_vrtc.bind(); }
auto lc_wr_callback() { return m_write_lc.bind(); }
DECLARE_READ8_MEMBER( read );
DECLARE_WRITE8_MEMBER( write );
uint8_t read(offs_t offset);
void write(offs_t offset, uint8_t data);
DECLARE_WRITE8_MEMBER( dack_w );
void dack_w(uint8_t data);
DECLARE_WRITE_LINE_MEMBER( lpen_w );

4
src/mame/drivers/argo.cpp
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@ -132,7 +132,7 @@ READ8_MEMBER(argo_state::argo_io_r)
case 0xC0:
case 0xC4:
offset >>= 2;
return m_crtc->read(space, offset&1);
return m_crtc->read(offset&1);
case 0xE8: // wants bit 4 low then high
{
@ -175,7 +175,7 @@ WRITE8_MEMBER(argo_state::argo_io_w)
case 0xC0:
case 0xC4:
offset >>= 2;
m_crtc->write(space, offset&1, data);
m_crtc->write(offset&1, data);
break;
case 0xE8: // hardware scroll

2
src/mame/drivers/dwarfd.cpp
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@ -369,7 +369,7 @@ READ8_MEMBER(dwarfd_state::dwarfd_ram_r)
}
else
{
m_crtc->dack_w(space, 0, m_dw_ram[offset], mem_mask);
m_crtc->dack_w(m_dw_ram[offset]);
return m_dw_ram[offset];
}
}

4
src/mame/drivers/hp64k.cpp
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@ -448,7 +448,7 @@ uint8_t hp64k_state::hp64k_crtc_filter(uint8_t data)
WRITE16_MEMBER(hp64k_state::hp64k_crtc_w)
{
m_crtc->write(space , offset == 0 , hp64k_crtc_filter((uint8_t)data));
m_crtc->write(offset == 0 , hp64k_crtc_filter((uint8_t)data));
}
WRITE_LINE_MEMBER(hp64k_state::hp64k_crtc_drq_w)
@ -465,7 +465,7 @@ WRITE_LINE_MEMBER(hp64k_state::hp64k_crtc_drq_w)
m_crtc_ptr++;
m_crtc->dack_w(prog_space , 0 , hp64k_crtc_filter(data));
m_crtc->dack_w(hp64k_crtc_filter(data));
}
}

12
src/mame/drivers/ms6102.cpp
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@ -201,14 +201,14 @@ I8275_DRAW_CHARACTER_MEMBER(ms6102_state::display_attr) // TODO: attributes
READ8_MEMBER(ms6102_state::crtc_r)
{
m_crtc2->read(space, offset);
return m_crtc1->read(space, offset); // cs is same for both crtcs so they should return the same thing
m_crtc2->read(offset);
return m_crtc1->read(offset); // cs is same for both crtcs so they should return the same thing
}
WRITE8_MEMBER(ms6102_state::crtc_w)
{
m_crtc1->write(space, offset, data);
m_crtc2->write(space, offset, data);
m_crtc1->write(offset, data);
m_crtc2->write(offset, data);
}
READ8_MEMBER(ms6102_state::misc_status_r)
@ -240,9 +240,9 @@ WRITE8_MEMBER(ms6102_state::pic_w)
WRITE8_MEMBER(ms6102_state::vdack_w)
{
if(m_dmaaddr & 1)
m_crtc1->dack_w(space, offset, data);
m_crtc1->dack_w(data);
else
m_crtc2->dack_w(space, offset, data | 0x80);
m_crtc2->dack_w(data | 0x80);
}
IRQ_CALLBACK_MEMBER(ms6102_state::ms6102_int_ack)

3
src/mame/drivers/rt1715.cpp
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@ -331,8 +331,7 @@ WRITE_LINE_MEMBER(rt1715_state::crtc_drq_w)
{
if (state)
{
address_space &mem = m_maincpu->space(AS_PROGRAM);
m_crtc->dack_w(mem, 0, m_p_videoram[m_dma_adr++]);
m_crtc->dack_w(m_p_videoram[m_dma_adr++]);
m_dma_adr %= (80 * 24);
}
}

5
src/mame/drivers/tim100.cpp
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@ -143,10 +143,7 @@ I8275_DRAW_CHARACTER_MEMBER( tim100_state::crtc_display_pixels )
WRITE_LINE_MEMBER( tim100_state::drq_w )
{
if (state)
{
address_space& mem = m_maincpu->space(AS_PROGRAM);
m_crtc->dack_w(mem, 0, m_p_videoram[m_dma_adr++]);
}
m_crtc->dack_w(m_p_videoram[m_dma_adr++]);
}
WRITE_LINE_MEMBER( tim100_state::irq_w )

8
src/mame/drivers/trs80dt1.cpp
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@ -93,17 +93,17 @@ void trs80dt1_state::machine_reset()
READ8_MEMBER( trs80dt1_state::dma_r )
{
m_crtc->dack_w(space, 0, m_p_videoram[offset]); // write to /BS pin
m_crtc->dack_w(m_p_videoram[offset]); // write to /BS pin
// Temporary hack to work around a timing issue
// timer interrupts fires too early and ends the psuedo-dma transfer after only 77 chars
// we send the last three manually until this is fixed
if (offset%80 == 76) {
offset++;
m_crtc->dack_w(space, 0, m_p_videoram[offset]);
m_crtc->dack_w(m_p_videoram[offset]);
offset++;
m_crtc->dack_w(space, 0, m_p_videoram[offset]);
m_crtc->dack_w(m_p_videoram[offset]);
offset++;
m_crtc->dack_w(space, 0, m_p_videoram[offset]);
m_crtc->dack_w(m_p_videoram[offset]);
}
return 0x7f;
}

12
src/mame/drivers/vp60.cpp
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@ -28,8 +28,8 @@ public:
private:
I8275_DRAW_CHARACTER_MEMBER(draw_character);
DECLARE_READ8_MEMBER(crtc_r);
DECLARE_WRITE8_MEMBER(crtc_w);
u8 crtc_r(offs_t offset);
void crtc_w(offs_t offset, u8 data);
void io_map(address_map &map);
void kbd_map(address_map &map);
@ -44,14 +44,14 @@ I8275_DRAW_CHARACTER_MEMBER(vp60_state::draw_character)
{
}
READ8_MEMBER(vp60_state::crtc_r)
u8 vp60_state::crtc_r(offs_t offset)
{
return m_crtc->read(space, offset >> 8);
return m_crtc->read(offset >> 8);
}
WRITE8_MEMBER(vp60_state::crtc_w)
void vp60_state::crtc_w(offs_t offset, u8 data)
{
m_crtc->write(space, offset >> 8, data);
m_crtc->write(offset >> 8, data);
}
void vp60_state::mem_map(address_map &map)

8
src/mame/drivers/wicat.cpp
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@ -551,9 +551,9 @@ READ8_MEMBER(wicat_state::video_r)
switch(offset)
{
case 0x00:
return m_crtc->read(space,0);
return m_crtc->read(0);
case 0x02:
return m_crtc->read(space,1);
return m_crtc->read(1);
default:
return 0xff;
}
@ -564,10 +564,10 @@ WRITE8_MEMBER(wicat_state::video_w)
switch(offset)
{
case 0x00:
m_crtc->write(space,0,data);
m_crtc->write(0,data);
break;
case 0x02:
m_crtc->write(space,1,data);
m_crtc->write(1,data);
break;
}
}

10
src/mame/drivers/wy100.cpp
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@ -151,10 +151,9 @@ u8 wy100_state::memory_r(offs_t offset)
logerror("%s: Reading %02X from PCI register %d\n", machine().describe_context(), data, p2 & 3);
if (m_bs_enable && !machine().side_effects_disabled())
{
address_space &space = machine().dummy_space();
u8 chardata = (data & 0xe0) == 0x80 ? data : data & 0x7f;
m_crtc[0]->dack_w(space, 0, chardata);
m_crtc[1]->dack_w(space, 0, (chardata & 0xfe) | (BIT(data, 7) ? 0x00 : 0x01));
m_crtc[0]->dack_w(chardata);
m_crtc[1]->dack_w((chardata & 0xfe) | (BIT(data, 7) ? 0x00 : 0x01));
}
return data;
}
@ -166,9 +165,8 @@ void wy100_state::memory_w(offs_t offset, u8 data)
// CRTC access is write-only
if (!BIT(p2, 6))
{
address_space &space = machine().dummy_space();
m_crtc[0]->write(space, p2 & 1, data);
m_crtc[1]->write(space, p2 & 1, data);
m_crtc[0]->write(p2 & 1, data);
m_crtc[1]->write(p2 & 1, data);
}
else if (m_brdy)
m_bs_enable = true;

16
src/mame/drivers/z29.cpp
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@ -36,8 +36,8 @@ protected:
private:
void p3_w(u8 data);
DECLARE_READ8_MEMBER(bs_24k_r);
DECLARE_WRITE8_MEMBER(crtc_w);
DECLARE_WRITE8_MEMBER(latch_12k_w);
void crtc_w(offs_t offset, u8 data);
void latch_12k_w(u8 data);
void prg_map(address_map &map);
void ext_map(address_map &map);
@ -72,8 +72,8 @@ READ8_MEMBER(z29_state::bs_24k_r)
u8 chardata = m_charmem[offset];
u8 attrdata = m_attrmem[offset] & 0xf;
m_crtc[0]->dack_w(space, 0, chardata & 0x7f);
m_crtc[1]->dack_w(space, 0, (chardata & 0x60) | (BIT(chardata, 7) ? 0x10 : 0) | attrdata);
m_crtc[0]->dack_w(chardata & 0x7f);
m_crtc[1]->dack_w((chardata & 0x60) | (BIT(chardata, 7) ? 0x10 : 0) | attrdata);
}
else
{
@ -85,13 +85,13 @@ READ8_MEMBER(z29_state::bs_24k_r)
return m_dmatype ? 0x24 : 0x20;
}
WRITE8_MEMBER(z29_state::crtc_w)
void z29_state::crtc_w(offs_t offset, u8 data)
{
m_crtc[0]->write(space, offset, data);
m_crtc[1]->write(space, offset, data);
m_crtc[0]->write(offset, data);
m_crtc[1]->write(offset, data);
}
WRITE8_MEMBER(z29_state::latch_12k_w)
void z29_state::latch_12k_w(u8 data)
{
m_nvram->store(!BIT(data, 0));
m_nvram->recall(!BIT(data, 3));

2
src/mame/drivers/zorba.cpp
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@ -409,7 +409,7 @@ WRITE8_MEMBER(zorba_state::io_write_byte)
address_space& prog_space = m_maincpu->space(AS_IO);
if (offset == 0x10)
m_crtc->dack_w(space, 0, data);
m_crtc->dack_w(data);
else
prog_space.write_byte(offset, data);
}