mirror of
https://github.com/holub/mame
synced 2025-05-30 17:41:47 +03:00
mc68hc11: Added ROLA, ROLB, SUBD INDX, SUBD INDY, SBCA INDX, SBCA INDY, SBCB INDX, SBCB INDY, added basic hook-up for TEST opcode.
This commit is contained in:
Angelo Salese
parent
38cc1f2cc9
commit
d2d36ebe02
@ -2268,6 +2268,45 @@ static void HC11OP(puly)(hc11_state *cpustate)
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CYCLES(cpustate, 6);
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}
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/* ROLA 0x49 */
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static void HC11OP(rola)(hc11_state *cpustate)
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{
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UINT8 c = (REG_A & 0x80);
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UINT16 r = ((REG_A & 0x7f) << 1) | (cpustate->ccr & CC_C ? 1 : 0);
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CLEAR_NZVC(cpustate);
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cpustate->ccr |= (c & 0x80) ? CC_C : 0;
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REG_A = (UINT16)(r);
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SET_N8(REG_A);
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SET_Z8(REG_A);
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if (((cpustate->ccr & CC_N) == CC_N && (cpustate->ccr & CC_C) == 0) ||
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((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C) == CC_C))
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{
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cpustate->ccr |= CC_V;
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}
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CYCLES(cpustate, 2);
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}
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/* ROLB 0x59 */
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static void HC11OP(rolb)(hc11_state *cpustate)
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{
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UINT8 c = (REG_B & 0x80);
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UINT16 r = (REG_B << 1) | (cpustate->ccr & CC_C ? 1 : 0);
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CLEAR_NZVC(cpustate);
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cpustate->ccr |= (c & 0x80) ? CC_C : 0;
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REG_B = (UINT16)(r);
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SET_N8(REG_B);
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SET_Z8(REG_B);
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if (((cpustate->ccr & CC_N) == CC_N && (cpustate->ccr & CC_C) == 0) ||
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((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C) == CC_C))
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{
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cpustate->ccr |= CC_V;
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}
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CYCLES(cpustate, 2);
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}
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/* RTS 0x39 */
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static void HC11OP(rts)(hc11_state *cpustate)
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@ -2277,6 +2316,74 @@ static void HC11OP(rts)(hc11_state *cpustate)
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CYCLES(cpustate, 5);
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}
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/* SBCA IND, X 0xA2 */
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static void HC11OP(sbca_indx)(hc11_state *cpustate)
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{
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int c = (cpustate->ccr & CC_C) ? 1 : 0;
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UINT8 offset = FETCH(cpustate);
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UINT8 i = READ8(cpustate, cpustate->ix + offset);
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UINT16 r = REG_A - i - c;
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CLEAR_NZVC(cpustate);
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// SET_H(r, i-c, REG_B);
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SET_N8(r);
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SET_Z8(r);
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SET_V_SUB8(r, i-c, REG_A);
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SET_C8(r);
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REG_A = (UINT8)r;
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CYCLES(cpustate, 4);
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}
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/* SBCA IND, Y 0x18, 0xA2 */
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static void HC11OP(sbca_indy)(hc11_state *cpustate)
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{
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int c = (cpustate->ccr & CC_C) ? 1 : 0;
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UINT8 offset = FETCH(cpustate);
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UINT8 i = READ8(cpustate, cpustate->iy + offset);
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UINT16 r = REG_A - i - c;
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CLEAR_NZVC(cpustate);
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// SET_H(r, i-c, REG_B);
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SET_N8(r);
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SET_Z8(r);
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SET_V_SUB8(r, i-c, REG_A);
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SET_C8(r);
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REG_A = (UINT8)r;
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CYCLES(cpustate, 5);
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}
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/* SBCB IND, X 0xE2 */
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static void HC11OP(sbcb_indx)(hc11_state *cpustate)
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{
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int c = (cpustate->ccr & CC_C) ? 1 : 0;
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UINT8 offset = FETCH(cpustate);
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UINT8 i = READ8(cpustate, cpustate->ix + offset);
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UINT16 r = REG_B - i - c;
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CLEAR_NZVC(cpustate);
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// SET_H(r, i-c, REG_B);
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SET_N8(r);
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SET_Z8(r);
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SET_V_SUB8(r, i-c, REG_B);
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SET_C8(r);
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REG_B = (UINT8)r;
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CYCLES(cpustate, 4);
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}
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/* SBCB IND, Y 0x18, 0xE2 */
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static void HC11OP(sbcb_indy)(hc11_state *cpustate)
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{
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int c = (cpustate->ccr & CC_C) ? 1 : 0;
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UINT8 offset = FETCH(cpustate);
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UINT8 i = READ8(cpustate, cpustate->iy + offset);
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UINT16 r = REG_B - i - c;
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CLEAR_NZVC(cpustate);
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// SET_H(r, i-c, REG_B);
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SET_N8(r);
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SET_Z8(r);
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SET_V_SUB8(r, i-c, REG_B);
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SET_C8(r);
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REG_B = (UINT8)r;
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CYCLES(cpustate, 5);
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}
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/* SEC 0x0D */
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static void HC11OP(sec)(hc11_state *cpustate)
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{
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@ -2578,6 +2685,36 @@ static void HC11OP(subd_imm)(hc11_state *cpustate)
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CYCLES(cpustate, 4);
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}
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/* SUBD INDX 0xA3 */
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static void HC11OP(subd_indx)(hc11_state *cpustate)
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{
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UINT8 offset = FETCH(cpustate);
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UINT16 i = READ16(cpustate, cpustate->ix + offset);
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UINT32 r = REG_D - i;
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CLEAR_NZVC(cpustate);
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SET_N16(r);
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SET_Z16(r);
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SET_V_SUB16(r, i, REG_D);
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SET_C16(r);
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REG_D = (UINT16)r;
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CYCLES(cpustate, 6);
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}
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/* SUBD INDY 0x18 0xA3 */
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static void HC11OP(subd_indy)(hc11_state *cpustate)
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{
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UINT8 offset = FETCH(cpustate);
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UINT16 i = READ16(cpustate, cpustate->iy + offset);
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UINT32 r = REG_D - i;
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CLEAR_NZVC(cpustate);
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SET_N16(r);
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SET_Z16(r);
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SET_V_SUB16(r, i, REG_D);
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SET_C16(r);
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REG_D = (UINT16)r;
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CYCLES(cpustate, 7);
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}
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/* TAB 0x16 */
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static void HC11OP(tab)(hc11_state *cpustate)
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{
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@ -2606,6 +2743,18 @@ static void HC11OP(tba)(hc11_state *cpustate)
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CYCLES(cpustate, 2);
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}
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/* TEST 0x00 */
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static void HC11OP(test)(hc11_state *cpustate)
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{
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// if(cpustate->test_mode)
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SET_PC(cpustate, cpustate->ppc); // Note: docs says "incremented" but the behaviour makes me think that's actually "decremented".
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// else
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// {
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// TODO: execute an illegal opcode exception here (NMI)
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// }
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CYCLES(cpustate, 1);
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}
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/* TPA 0x07 */
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static void HC11OP(tpa)(hc11_state *cpustate)
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@ -232,8 +232,8 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
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{ 0, 0x33, HC11OP(pulb) },
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{ 0, 0x38, HC11OP(pulx) },
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{ 0x18, 0x38, HC11OP(puly) },
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// { 0, 0x49, HC11OP(rola) },
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// { 0, 0x59, HC11OP(rolb) },
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{ 0, 0x49, HC11OP(rola) },
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{ 0, 0x59, HC11OP(rolb) },
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// { 0, 0x79, HC11OP(rol_ext) },
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// { 0, 0x69, HC11OP(rol_indx) },
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// { 0x18, 0x69, HC11OP(rol_indy) },
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@ -248,13 +248,13 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
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// { 0, 0x82, HC11OP(sbca_imm) },
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// { 0, 0x92, HC11OP(sbca_dir) },
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// { 0, 0xb2, HC11OP(sbca_ext) },
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// { 0, 0xa2, HC11OP(sbca_indx) },
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// { 0x18, 0xa2, HC11OP(sbca_indy) },
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{ 0, 0xa2, HC11OP(sbca_indx) },
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{ 0x18, 0xa2, HC11OP(sbca_indy) },
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// { 0, 0xc2, HC11OP(sbcb_imm) },
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// { 0, 0xd2, HC11OP(sbcb_dir) },
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// { 0, 0xf2, HC11OP(sbcb_ext) },
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// { 0, 0xe2, HC11OP(sbcb_indx) },
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// { 0x18, 0xe2, HC11OP(sbcb_indy) },
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{ 0, 0xe2, HC11OP(sbcb_indx) },
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{ 0x18, 0xe2, HC11OP(sbcb_indy) },
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{ 0, 0x0d, HC11OP(sec) },
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{ 0, 0x0f, HC11OP(sei) },
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{ 0, 0x0b, HC11OP(sev) },
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@ -299,13 +299,13 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
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{ 0, 0x83, HC11OP(subd_imm) },
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// { 0, 0x93, HC11OP(subd_dir) },
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// { 0, 0xb3, HC11OP(subd_ext) },
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// { 0, 0xa3, HC11OP(subd_indx) },
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// { 0x18, 0xa3, HC11OP(subd_indy) },
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{ 0, 0xa3, HC11OP(subd_indx) },
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{ 0x18, 0xa3, HC11OP(subd_indy) },
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// { 0, 0x3f, HC11OP(swi) },
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{ 0, 0x16, HC11OP(tab) },
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{ 0, 0x06, HC11OP(tap) },
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{ 0, 0x17, HC11OP(tba) },
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// { 0, 0x00, HC11OP(test) },
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{ 0, 0x00, HC11OP(test) },
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{ 0, 0x07, HC11OP(tpa) },
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{ 0, 0x4d, HC11OP(tsta) },
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{ 0, 0x5d, HC11OP(tstb) },
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@ -410,7 +410,7 @@ static CPU_SET_INFO( mc68hc11 )
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{
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/* --- the following bits of info are set as 64-bit signed integers --- */
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case CPUINFO_INT_PC: cpustate->pc = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break;
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