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Imported the Hitachi HCD62121 CPU core from MESS.

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This commit is contained in:
Curt Coder 2010-08-20 17:32:03 +00:00
parent 5cfa64098e
commit d303a4f17d
5 changed files with 1867 additions and 0 deletions
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4
.gitattributes vendored
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@ -137,6 +137,10 @@ src/emu/cpu/h83002/h8disasm.c svneol=native#text/plain
src/emu/cpu/h83002/h8ops.h svneol=native#text/plain
src/emu/cpu/h83002/h8periph.c svneol=native#text/plain
src/emu/cpu/h83002/h8priv.h svneol=native#text/plain
src/emu/cpu/hcd62121/hcd62121.c svneol=native#text/plain
src/emu/cpu/hcd62121/hcd62121.h svneol=native#text/plain
src/emu/cpu/hcd62121/hcd62121_ops.h svneol=native#text/plain
src/emu/cpu/hcd62121/hcd62121d.c svneol=native#text/plain
src/emu/cpu/hd6309/6309dasm.c svneol=native#text/plain
src/emu/cpu/hd6309/6309ops.c svneol=native#text/plain
src/emu/cpu/hd6309/6309tbl.c svneol=native#text/plain

505
src/emu/cpu/hcd62121/hcd62121.c Normal file
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/**********************************************************************
Hitachi hcd62121 cpu core emulation.
The Hitachi hcd62121 is the custom cpu which was used in the Casio
CFX-9850 (and maybe some other things too).
This CPU core is based on the information provided by Martin Poupe.
Martin Poupe's site can be found at http://prg.rkk.cz/~mpoupe/
**********************************************************************/
#include "emu.h"
#include "debugger.h"
#include "hcd62121.h"
struct _hcd62121_state
{
UINT32 prev_pc;
UINT16 sp;
UINT16 ip;
UINT8 dsize;
UINT8 cseg;
UINT8 dseg;
UINT8 sseg;
UINT8 f;
UINT16 lar;
UINT8 reg[0x80];
UINT8 temp1[0x10];
UINT8 temp2[0x10];
device_irq_callback irq_callback;
legacy_cpu_device *device;
address_space *program;
address_space *io;
int icount;
};
typedef struct _hcd62121_state hcd62121_state;
/* From the battery check routine at 20:e874 it looks like
bit 3 of the flag register should be the Zero flag. */
#define _FLAG_Z 0x08
#define _FLAG_C 0x02
#define _FLAG_ZL 0x04
#define _FLAG_CL 0x01
#define _FLAG_ZH 0x10
#define mem_readbyte(cs,A) ((UINT8)(cs)->program->read_byte(A))
#define mem_writebyte(cs,A,V) ((cs)->program->write_byte(A,V))
#define io_readbyte(cs,A) ((UINT8)(cs)->io->read_byte(A))
#define io_writebyte(cs,A,V) ((cs)->io->write_byte(A,V))
INLINE UINT8 read_op(hcd62121_state *cpustate)
{
UINT8 d = mem_readbyte(cpustate, ( cpustate->cseg << 16 ) | cpustate->ip );
cpustate->ip++;
return d;
}
INLINE UINT8 datasize( hcd62121_state *cpustate, UINT8 op )
{
switch( op & 0x03 )
{
case 0:
return 1;
case 1:
return 2;
case 2:
return ( cpustate->dsize >> 4 ) + 1;
case 3:
return ( cpustate->dsize & 0x0f ) + 1;
}
return 1;
}
INLINE void read_reg( hcd62121_state *cpustate, int size, UINT8 op1 )
{
int i;
if ( op1 & 0x80 )
{
for ( i = 0; i < size; i++ )
cpustate->temp1[i] = cpustate->reg[ ( op1 - i ) & 0x7f ];
}
else
{
for ( i = 0; i < size; i++ )
cpustate->temp1[i] = cpustate->reg[ ( op1 + i ) & 0x7f ];
}
}
INLINE void write_reg( hcd62121_state *cpustate, int size, UINT8 op1 )
{
int i;
if ( op1 & 0x80 )
{
for ( i = 0; i < size; i++ )
cpustate->reg[ ( op1 - i ) & 0x7f ] = cpustate->temp1[i];
}
else
{
for ( i = 0; i < size; i++ )
cpustate->reg[ ( op1 + i ) & 0x7f ] = cpustate->temp1[i];
}
}
INLINE void read_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
{
int i;
for ( i = 0; i < size; i++ )
cpustate->temp1[i] = cpustate->reg[ (op1 + i) & 0x7f];
if ( op1 & 0x80 )
{
cpustate->temp2[0] = op2;
for ( i = 1; i < size; i++ )
cpustate->temp2[i] = 0;
}
else
{
for ( i = 0; i < size; i++ )
cpustate->temp2[i] = cpustate->reg[ (op2 + i) & 0x7f ];
}
if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) )
{
/* We need to swap parameters */
for ( i = 0; i < size; i++ )
{
UINT8 v = cpustate->temp1[i];
cpustate->temp1[i] = cpustate->temp2[i];
cpustate->temp2[i] = v;
}
}
}
INLINE void write_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
{
int i;
if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) )
{
/* store in reg1 */
for ( i = 0; i < size; i++ )
cpustate->reg[ (op1 + i) & 0x7f] = cpustate->temp1[i];
}
else
{
/* store in reg2 */
for ( i = 0; i < size; i++ )
cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp1[i];
}
}
INLINE void read_iregreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
{
int i;
UINT16 ad;
ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
for ( i = 0; i < size; i++ )
{
cpustate->temp1[i] = mem_readbyte( cpustate, ( cpustate->dseg << 16 ) | ad );
ad += ( op1 & 0x40 ) ? -1 : 1;
}
cpustate->lar = ad;
if ( op1 & 0x80 )
{
cpustate->temp2[0] = op2;
for ( i = 1; i < size; i++ )
cpustate->temp2[i] = 0;
}
else
{
for ( i = 0; i < size; i++ )
cpustate->temp2[i] = cpustate->reg[ (op2 + i) & 0x7f ];
}
if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) )
{
/* We need to swap parameters */
for ( i = 0; i < size; i++ )
{
UINT8 v = cpustate->temp1[i];
cpustate->temp1[i] = cpustate->temp2[i];
cpustate->temp2[i] = v;
}
}
}
INLINE void write_iregreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
{
int i;
if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) )
{
/* store in (reg1) */
UINT16 ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
for ( i = 0; i < size; i++ )
{
mem_writebyte( cpustate, ( cpustate->dseg << 16 ) | ad, cpustate->temp1[i] );
ad += ( op1 & 0x40 ) ? -1 : 1;
}
cpustate->lar = ad;
}
else
{
/* store in reg2 */
for ( i = 0; i < size; i++ )
cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp1[i];
}
}
INLINE void write_iregreg2( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
{
int i;
if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) )
{
/* store in reg2 */
for ( i = 0; i < size; i++ )
cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp2[i];
}
else
{
/* store in (reg1) */
UINT16 ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
for ( i = 0; i < size; i++ )
{
mem_writebyte( cpustate, ( cpustate->dseg << 16 ) | ad, cpustate->temp2[i] );
ad += ( op1 & 0x40 ) ? -1 : 1;
}
cpustate->lar = ad;
}
}
INLINE int check_cond( hcd62121_state *cpustate, UINT8 op )
{
switch ( op & 0x07 )
{
case 0x00: /* ZH set */
if ( cpustate->f & _FLAG_ZH )
return 1;
break;
case 0x01: /* ZL set */
if ( cpustate->f & _FLAG_ZL )
return 1;
break;
case 0x02: /* C set */
if ( cpustate->f & _FLAG_C )
return 1;
break;
case 0x03: /* Z set */
if ( cpustate->f & _FLAG_Z )
return 1;
break;
case 0x04: /* Z or C set */
if ( cpustate->f & ( _FLAG_Z | _FLAG_C ) )
return 1;
break;
case 0x05: /* CL set */
if ( cpustate->f & _FLAG_CL )
return 1;
break;
case 0x06: /* C clear */
if ( ! ( cpustate->f & _FLAG_C ) )
return 1;
break;
case 0x07: /* Z clear */
if ( ! ( cpustate->f & _FLAG_Z ) )
return 1;
break;
}
return 0;
}
INLINE hcd62121_state *get_safe_token(running_device *device)
{
assert(device != NULL);
assert(device->type() == HCD62121);
return (hcd62121_state *)downcast<legacy_cpu_device *>(device)->token();
}
static CPU_INIT( hcd62121 )
{
hcd62121_state *cpustate = get_safe_token(device);
cpustate->irq_callback = irqcallback;
cpustate->device = device;
cpustate->program = device->space(AS_PROGRAM);
cpustate->io = device->space(AS_IO);
}
static CPU_RESET( hcd62121 )
{
hcd62121_state *cpustate = get_safe_token(device);
cpustate->sp = 0x0000;
cpustate->ip = 0x0000;
cpustate->cseg = 0;
cpustate->dseg = 0;
cpustate->sseg = 0;
cpustate->lar = 0;
cpustate->f = 0;
cpustate->dsize = 0;
for( int i = 0; i < 0x80; i++ )
{
cpustate->reg[i] = 0;
}
}
static CPU_EXECUTE( hcd62121 )
{
hcd62121_state *cpustate = get_safe_token(device);
do
{
UINT32 pc = ( cpustate->cseg << 16 ) | cpustate->ip;
UINT8 op;
debugger_instruction_hook(device, pc);
cpustate->prev_pc = pc;
op = read_op( cpustate );
cpustate->icount -= 4;
switch ( op )
{
#include "hcd62121_ops.h"
};
} while (cpustate->icount > 0);
}
static CPU_SET_INFO( hcd62121 )
{
hcd62121_state *cpustate = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0:
case CPUINFO_INT_INPUT_STATE + 1:
break;
case CPUINFO_INT_SP: cpustate->sp = info->i; break;
case CPUINFO_INT_PC: cpustate->ip = info->i; break;
case CPUINFO_INT_REGISTER + HCD62121_IP: cpustate->ip = info->i; break;
case CPUINFO_INT_REGISTER + HCD62121_SP: cpustate->sp = info->i; break;
// case CPUINFO_INT_REGISTER + HCD62121_R00: break;
// case CPUINFO_INT_REGISTER + HCD62121_R02: break;
}
}
CPU_GET_INFO( hcd62121 )
{
hcd62121_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hcd62121_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 2; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
case DEVINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 18; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 4; /* right? */ break;
case CPUINFO_INT_MAX_CYCLES: info->i = 48; /* right? */ break;
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 8; break;
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 24; break;
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_SP: info->i = cpustate->sp; break;
case CPUINFO_INT_PC: info->i = ( cpustate->cseg << 16 ) | cpustate->ip; break;
case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->prev_pc; break;
case CPUINFO_INT_INPUT_STATE + 0:
case CPUINFO_INT_INPUT_STATE + 1:
/* TODO */ break;
case CPUINFO_INT_REGISTER + HCD62121_IP: info->i = cpustate->ip; break;
case CPUINFO_INT_REGISTER + HCD62121_SP: info->i = cpustate->sp; break;
case CPUINFO_INT_REGISTER + HCD62121_LAR: info->i = cpustate->lar; break;
case CPUINFO_INT_REGISTER + HCD62121_CS: info->i = cpustate->cseg; break;
case CPUINFO_INT_REGISTER + HCD62121_DS: info->i = cpustate->dseg; break;
case CPUINFO_INT_REGISTER + HCD62121_SS: info->i = cpustate->sseg; break;
case CPUINFO_INT_REGISTER + HCD62121_DSIZE: info->i = cpustate->dsize; break;
case CPUINFO_INT_REGISTER + HCD62121_R00: info->i = ( cpustate->reg[0x00] << 24 ) | ( cpustate->reg[0x01] << 16 ) | ( cpustate->reg[0x02] << 8 ) | cpustate->reg[0x03]; break;
// case CPUINFO_INT_REGISTER + HCD62121_R02: info->i = cpustate->; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(hcd62121); break;
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hcd62121); break;
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hcd62121); break;
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hcd62121); break;
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hcd62121); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case DEVINFO_STR_NAME: strcpy(info->s, "HCD62121"); break;
case DEVINFO_STR_FAMILY: strcpy(info->s, "Hitachi HCD62121"); break;
case DEVINFO_STR_VERSION: strcpy(info->s, "0.1"); break;
case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright The MESS Team."); break;
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%s-%s-%s-%c-%c",
cpustate->f & _FLAG_ZH ? "ZH":"__",
cpustate->f & _FLAG_CL ? "CL":"__",
cpustate->f & _FLAG_ZL ? "ZL":"__",
cpustate->f & _FLAG_C ? 'C':'_',
cpustate->f & _FLAG_Z ? 'Z':'_'
);
break;
case CPUINFO_STR_REGISTER + HCD62121_IP: sprintf(info->s, "IP:%04X", cpustate->ip); break;
case CPUINFO_STR_REGISTER + HCD62121_SP: sprintf(info->s, "SP:%04X", cpustate->sp); break;
case CPUINFO_STR_REGISTER + HCD62121_LAR: sprintf(info->s, "LAR:%04X", cpustate->lar); break;
case CPUINFO_STR_REGISTER + HCD62121_CS: sprintf(info->s, "CS:%02X", cpustate->cseg); break;
case CPUINFO_STR_REGISTER + HCD62121_DS: sprintf(info->s, "DS:%02X", cpustate->dseg); break;
case CPUINFO_STR_REGISTER + HCD62121_SS: sprintf(info->s, "SS:%02X", cpustate->sseg); break;
case CPUINFO_STR_REGISTER + HCD62121_DSIZE: sprintf(info->s, "DSIZE:%02X", cpustate->dsize); break;
case CPUINFO_STR_REGISTER + HCD62121_R00: sprintf(info->s, "R00:%02X%02X%02X%02X", cpustate->reg[0x00], cpustate->reg[0x01], cpustate->reg[0x02], cpustate->reg[0x03]); break;
case CPUINFO_STR_REGISTER + HCD62121_R04: sprintf(info->s, "R04:%02X%02X%02X%02X", cpustate->reg[0x04], cpustate->reg[0x05], cpustate->reg[0x06], cpustate->reg[0x07]); break;
case CPUINFO_STR_REGISTER + HCD62121_R08: sprintf(info->s, "R08:%02X%02X%02X%02X", cpustate->reg[0x08], cpustate->reg[0x09], cpustate->reg[0x0a], cpustate->reg[0x0b]); break;
case CPUINFO_STR_REGISTER + HCD62121_R0C: sprintf(info->s, "R0C:%02X%02X%02X%02X", cpustate->reg[0x0c], cpustate->reg[0x0d], cpustate->reg[0x0e], cpustate->reg[0x0f]); break;
case CPUINFO_STR_REGISTER + HCD62121_R10: sprintf(info->s, "R10:%02X%02X%02X%02X", cpustate->reg[0x10], cpustate->reg[0x11], cpustate->reg[0x12], cpustate->reg[0x13]); break;
case CPUINFO_STR_REGISTER + HCD62121_R14: sprintf(info->s, "R14:%02X%02X%02X%02X", cpustate->reg[0x14], cpustate->reg[0x15], cpustate->reg[0x16], cpustate->reg[0x17]); break;
case CPUINFO_STR_REGISTER + HCD62121_R18: sprintf(info->s, "R18:%02X%02X%02X%02X", cpustate->reg[0x18], cpustate->reg[0x19], cpustate->reg[0x1a], cpustate->reg[0x1b]); break;
case CPUINFO_STR_REGISTER + HCD62121_R1C: sprintf(info->s, "R1C:%02X%02X%02X%02X", cpustate->reg[0x1c], cpustate->reg[0x1d], cpustate->reg[0x1e], cpustate->reg[0x1f]); break;
case CPUINFO_STR_REGISTER + HCD62121_R20: sprintf(info->s, "R20:%02X%02X%02X%02X", cpustate->reg[0x20], cpustate->reg[0x21], cpustate->reg[0x22], cpustate->reg[0x23]); break;
case CPUINFO_STR_REGISTER + HCD62121_R24: sprintf(info->s, "R24:%02X%02X%02X%02X", cpustate->reg[0x24], cpustate->reg[0x25], cpustate->reg[0x26], cpustate->reg[0x27]); break;
case CPUINFO_STR_REGISTER + HCD62121_R28: sprintf(info->s, "R28:%02X%02X%02X%02X", cpustate->reg[0x28], cpustate->reg[0x29], cpustate->reg[0x2a], cpustate->reg[0x2b]); break;
case CPUINFO_STR_REGISTER + HCD62121_R2C: sprintf(info->s, "R2C:%02X%02X%02X%02X", cpustate->reg[0x2c], cpustate->reg[0x2d], cpustate->reg[0x2e], cpustate->reg[0x2f]); break;
case CPUINFO_STR_REGISTER + HCD62121_R30: sprintf(info->s, "R30:%02X%02X%02X%02X", cpustate->reg[0x30], cpustate->reg[0x31], cpustate->reg[0x32], cpustate->reg[0x33]); break;
case CPUINFO_STR_REGISTER + HCD62121_R34: sprintf(info->s, "R34:%02X%02X%02X%02X", cpustate->reg[0x34], cpustate->reg[0x35], cpustate->reg[0x36], cpustate->reg[0x37]); break;
case CPUINFO_STR_REGISTER + HCD62121_R38: sprintf(info->s, "R38:%02X%02X%02X%02X", cpustate->reg[0x38], cpustate->reg[0x39], cpustate->reg[0x3a], cpustate->reg[0x3b]); break;
case CPUINFO_STR_REGISTER + HCD62121_R3C: sprintf(info->s, "R3C:%02X%02X%02X%02X", cpustate->reg[0x3c], cpustate->reg[0x3d], cpustate->reg[0x3e], cpustate->reg[0x3f]); break;
case CPUINFO_STR_REGISTER + HCD62121_R40: sprintf(info->s, "R40:%02X%02X%02X%02X", cpustate->reg[0x40], cpustate->reg[0x41], cpustate->reg[0x42], cpustate->reg[0x43]); break;
case CPUINFO_STR_REGISTER + HCD62121_R44: sprintf(info->s, "R44:%02X%02X%02X%02X", cpustate->reg[0x44], cpustate->reg[0x45], cpustate->reg[0x46], cpustate->reg[0x47]); break;
case CPUINFO_STR_REGISTER + HCD62121_R48: sprintf(info->s, "R48:%02X%02X%02X%02X", cpustate->reg[0x48], cpustate->reg[0x49], cpustate->reg[0x4a], cpustate->reg[0x4b]); break;
case CPUINFO_STR_REGISTER + HCD62121_R4C: sprintf(info->s, "R4C:%02X%02X%02X%02X", cpustate->reg[0x4c], cpustate->reg[0x4d], cpustate->reg[0x4e], cpustate->reg[0x4f]); break;
case CPUINFO_STR_REGISTER + HCD62121_R50: sprintf(info->s, "R50:%02X%02X%02X%02X", cpustate->reg[0x50], cpustate->reg[0x51], cpustate->reg[0x52], cpustate->reg[0x53]); break;
case CPUINFO_STR_REGISTER + HCD62121_R54: sprintf(info->s, "R54:%02X%02X%02X%02X", cpustate->reg[0x54], cpustate->reg[0x55], cpustate->reg[0x56], cpustate->reg[0x57]); break;
case CPUINFO_STR_REGISTER + HCD62121_R58: sprintf(info->s, "R58:%02X%02X%02X%02X", cpustate->reg[0x58], cpustate->reg[0x59], cpustate->reg[0x5a], cpustate->reg[0x5b]); break;
case CPUINFO_STR_REGISTER + HCD62121_R5C: sprintf(info->s, "R5C:%02X%02X%02X%02X", cpustate->reg[0x5c], cpustate->reg[0x5d], cpustate->reg[0x5e], cpustate->reg[0x5f]); break;
case CPUINFO_STR_REGISTER + HCD62121_R60: sprintf(info->s, "R60:%02X%02X%02X%02X", cpustate->reg[0x60], cpustate->reg[0x61], cpustate->reg[0x62], cpustate->reg[0x63]); break;
case CPUINFO_STR_REGISTER + HCD62121_R64: sprintf(info->s, "R64:%02X%02X%02X%02X", cpustate->reg[0x64], cpustate->reg[0x65], cpustate->reg[0x66], cpustate->reg[0x67]); break;
case CPUINFO_STR_REGISTER + HCD62121_R68: sprintf(info->s, "R68:%02X%02X%02X%02X", cpustate->reg[0x68], cpustate->reg[0x69], cpustate->reg[0x6a], cpustate->reg[0x6b]); break;
case CPUINFO_STR_REGISTER + HCD62121_R6C: sprintf(info->s, "R6C:%02X%02X%02X%02X", cpustate->reg[0x6c], cpustate->reg[0x6d], cpustate->reg[0x6e], cpustate->reg[0x6f]); break;
case CPUINFO_STR_REGISTER + HCD62121_R70: sprintf(info->s, "R70:%02X%02X%02X%02X", cpustate->reg[0x70], cpustate->reg[0x71], cpustate->reg[0x72], cpustate->reg[0x73]); break;
case CPUINFO_STR_REGISTER + HCD62121_R74: sprintf(info->s, "R74:%02X%02X%02X%02X", cpustate->reg[0x74], cpustate->reg[0x75], cpustate->reg[0x76], cpustate->reg[0x77]); break;
case CPUINFO_STR_REGISTER + HCD62121_R78: sprintf(info->s, "R78:%02X%02X%02X%02X", cpustate->reg[0x78], cpustate->reg[0x79], cpustate->reg[0x7a], cpustate->reg[0x7b]); break;
case CPUINFO_STR_REGISTER + HCD62121_R7C: sprintf(info->s, "R7C:%02X%02X%02X%02X", cpustate->reg[0x7c], cpustate->reg[0x7d], cpustate->reg[0x7e], cpustate->reg[0x7f]); break;
}
}
DEFINE_LEGACY_CPU_DEVICE(HCD62121, hcd62121);

38
src/emu/cpu/hcd62121/hcd62121.h Normal file
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#ifndef __HCD62121_H__
#define __HCD62121_H__
enum
{
HCD62121_IP=1, HCD62121_SP, HCD62121_F, HCD62121_LAR,
HCD62121_CS, HCD62121_DS, HCD62121_SS, HCD62121_DSIZE,
/* 128 byte register file */
HCD62121_R00, HCD62121_R04, HCD62121_R08, HCD62121_R0C,
HCD62121_R10, HCD62121_R14, HCD62121_R18, HCD62121_R1C,
HCD62121_R20, HCD62121_R24, HCD62121_R28, HCD62121_R2C,
HCD62121_R30, HCD62121_R34, HCD62121_R38, HCD62121_R3C,
HCD62121_R40, HCD62121_R44, HCD62121_R48, HCD62121_R4C,
HCD62121_R50, HCD62121_R54, HCD62121_R58, HCD62121_R5C,
HCD62121_R60, HCD62121_R64, HCD62121_R68, HCD62121_R6C,
HCD62121_R70, HCD62121_R74, HCD62121_R78, HCD62121_R7C,
};
/* I/O ports */
enum
{
/* Output ports */
HCD62121_KOL=0x00,
HCD62121_KOH,
/* Input ports */
HCD62121_KI,
};
DECLARE_LEGACY_CPU_DEVICE(HCD62121, hcd62121);
extern CPU_DISASSEMBLE( hcd62121 );
#endif /* __HCD62121_H__ */

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#define HCD62121_MSK \
{ \
int i; \
UINT8 mskres = 1; \
\
for ( i = 0; i < size; i++ ) \
{ \
if ( ( cpustate->temp1[i] & cpustate->temp2[i] ) != cpustate->temp2[i] ) \
mskres = 0; \
} \
\
if ( mskres ) \
cpustate->f &= ~_FLAG_Z; \
else \
cpustate->f |= _FLAG_Z; \
}
#define HCD62121_IMSK \
{ \
int i; \
UINT8 mskres = 1; \
UINT8 set_zero = 0; \
\
for ( i = 0; i < size; i++ ) \
{ \
if ( ( cpustate->temp1[i] & ~cpustate->temp2[i] ) != ~cpustate->temp2[i] ) \
mskres = 0; \
if ( cpustate->temp1[i] | cpustate->temp2[i] ) \
set_zero = 1; \
} \
\
if ( set_zero ) \
cpustate->f |= _FLAG_Z; \
else \
cpustate->f &= ~_FLAG_Z; \
\
if ( mskres ) \
cpustate->f &= ~_FLAG_C; \
else \
cpustate->f |= _FLAG_C; \
}
#define HCD62121_AND \
{ \
int i; \
UINT8 is_zero = 1; \
\
for ( i = 0; i < size; i++ ) \
{ \
cpustate->temp1[i] = cpustate->temp1[i] & cpustate->temp2[i]; \
if ( cpustate->temp1[i] ) \
is_zero = 0; \
} \
\
if ( is_zero ) \
cpustate->f |= _FLAG_Z; \
else \
cpustate->f &= ~_FLAG_Z; \
\
if ( cpustate->temp1[0] & 0x0f ) \
cpustate->f &= ~_FLAG_ZL; \
else \
cpustate->f |= _FLAG_ZL; \
\
if ( cpustate->temp1[0] & 0xf0 ) \
cpustate->f &= ~_FLAG_ZH; \
else \
cpustate->f |= _FLAG_ZH; \
}
#define HCD62121_OR \
{ \
int i; \
UINT8 is_zero = 1; \
\
for ( i = 0; i < size; i++ ) \
{ \
cpustate->temp1[i] = cpustate->temp1[i] | cpustate->temp2[i]; \
if ( cpustate->temp1[i] ) \
is_zero = 0; \
} \
\
if ( is_zero ) \
cpustate->f |= _FLAG_Z; \
else \
cpustate->f &= ~_FLAG_Z; \
\
if ( cpustate->temp1[0] & 0x0f ) \
cpustate->f &= ~_FLAG_ZL; \
else \
cpustate->f |= _FLAG_ZL; \
\
if ( cpustate->temp1[0] & 0xf0 ) \
cpustate->f &= ~_FLAG_ZH; \
else \
cpustate->f |= _FLAG_ZH; \
}
#define HCD62121_ADD \
{ \
int i; \
UINT8 is_zero = 1, carry = 0; \
\
if ( ( cpustate->temp1[0] & 0x0f ) + ( cpustate->temp2[0] & 0x0f ) > 15 ) \
cpustate->f |= _FLAG_CL; \
else \
cpustate->f &= ~_FLAG_CL; \
\
for ( i = 0; i < size; i++ ) \
{ \
UINT16 res = cpustate->temp1[i] + cpustate->temp2[i] + carry; \
\
cpustate->temp1[i] = res & 0xff; \
if ( cpustate->temp1[i] ) \
is_zero = 0; \
\
carry = ( res & 0xff00 ) ? 1 : 0; \
} \
\
if ( is_zero ) \
cpustate->f |= _FLAG_Z; \
else \
cpustate->f &= ~_FLAG_Z; \
\
if ( carry ) \
cpustate->f |= _FLAG_C; \
else \
cpustate->f &= ~_FLAG_C; \
\
if ( cpustate->temp1[0] & 0x0f ) \
cpustate->f &= ~_FLAG_ZL; \
else \
cpustate->f |= _FLAG_ZL; \
\
if ( cpustate->temp1[0] & 0xf0 ) \
cpustate->f &= ~_FLAG_ZH; \
else \
cpustate->f |= _FLAG_ZH; \
}
/* BCD ADD */
#define HCD62121_ADDB \
{ \
int i; \
UINT8 is_zero = 1, carry = 0; \
\
if ( ( cpustate->temp1[0] & 0x0f ) + ( cpustate->temp2[0] & 0x0f ) > 9 ) \
cpustate->f |= _FLAG_CL; \
else \
cpustate->f &= ~_FLAG_CL; \
\
for ( i = 0; i < size; i++ ) \
{ \
UINT16 res = ( cpustate->temp1[i] & 0x0f ) + ( cpustate->temp2[i] & 0x0f ) + carry; \
\
carry = 0; \
if ( res > 9 ) \
{ \
res += 6; \
} \
res += ( cpustate->temp1[i] & 0xf0 ) + ( cpustate->temp2[i] & 0xf0 ); \
if ( res > 0x9f ) \
{ \
res += 0x60; \
} \
cpustate->temp1[i] = res & 0xff; \
if ( cpustate->temp1[i] ) \
is_zero = 0; \
\
carry = ( res & 0xff00 ) ? 1 : 0; \
} \
\
if ( is_zero ) \
cpustate->f |= _FLAG_Z; \
else \
cpustate->f &= ~_FLAG_Z; \
\
if ( carry ) \
cpustate->f |= _FLAG_C; \
else \
cpustate->f &= ~_FLAG_C; \
\
if ( cpustate->temp1[0] & 0x0f ) \
cpustate->f &= ~_FLAG_ZL; \
else \
cpustate->f |= _FLAG_ZL; \
\
if ( cpustate->temp1[0] & 0xf0 ) \
cpustate->f &= ~_FLAG_ZH; \
else \
cpustate->f |= _FLAG_ZH; \
}
#define HCD62121_SUB \
{ \
int i; \
UINT8 is_zero = 1, carry = 0; \
\
if ( ( cpustate->temp1[0] & 0x0f ) < ( cpustate->temp2[0] & 0x0f ) ) \
cpustate->f |= _FLAG_CL; \
else \
cpustate->f &= ~_FLAG_CL; \
\
for ( i = 0; i < size; i++ ) \
{ \
UINT16 res = cpustate->temp1[i] - cpustate->temp2[i] - carry; \
\
cpustate->temp1[i] = res & 0xff; \
if ( cpustate->temp1[i] ) \
is_zero = 0; \
\
carry = ( res & 0xff00 ) ? 1 : 0; \
} \
\
if ( is_zero ) \
cpustate->f |= _FLAG_Z; \
else \
cpustate->f &= ~_FLAG_Z; \
\
if ( carry ) \
cpustate->f |= _FLAG_C; \
else \
cpustate->f &= ~_FLAG_C; \
\
if ( cpustate->temp1[0] & 0x0f ) \
cpustate->f &= ~_FLAG_ZL; \
else \
cpustate->f |= _FLAG_ZL; \
\
if ( cpustate->temp1[0] & 0xf0 ) \
cpustate->f &= ~_FLAG_ZH; \
else \
cpustate->f |= _FLAG_ZH; \
}
#define HCD62121_PUSHW(source) \
{ \
UINT16 address = source; \
mem_writebyte( cpustate, ( cpustate->sseg << 16 ) | cpustate->sp, ( address ) & 0xff ); \
cpustate->sp--; \
mem_writebyte( cpustate, ( cpustate->sseg << 16 ) | cpustate->sp, ( address ) >> 8 ); \
cpustate->sp--; \
}
#define HCD62121_POPW(dest) \
{ \
UINT16 res; \
cpustate->sp++; \
res = mem_readbyte( cpustate, ( cpustate->sseg << 16 ) | cpustate->sp ) << 8; \
cpustate->sp++; \
res |= mem_readbyte( cpustate, ( cpustate->sseg << 16 ) | cpustate->sp ); \
dest = res; \
}
case 0x04: /* mskb r1,r2 */
case 0x05: /* mskw r1,r2 */
case 0x06: /* mskq r1,r2 */
case 0x07: /* mskt r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_MSK;
}
break;
case 0x08: /* shrb r1 */
case 0x09: /* shrb r1 */
case 0x0A: /* shrq r1 */
case 0x0B: /* shrt r1 */
/* Shift is a nibble shift! */
{
int i;
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 d1 = 0, d2 = 0;
read_reg( cpustate, size, reg1 );
for ( i = 0; i < size; i++ )
{
d1 = ( cpustate->temp1[i] & 0x0f ) << 4;
cpustate->temp1[i] = ( cpustate->temp1[i] >> 4 ) | d2;
d2 = d1;
}
write_reg( cpustate, size, reg1 );
}
break;
case 0x0C: /* testb r1,r2 */
case 0x0D: /* testw r1,r2 */
case 0x0E: /* testq r1,r2 */
case 0x0F: /* testt r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_AND;
}
break;
case 0x14: /* cmpb r1,r2 */
case 0x15: /* cmpw r1,r2 */
case 0x16: /* cmpq r1,r2 */
case 0x17: /* cmpt r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_SUB;
}
break;
case 0x18: /* movb r1,r2 */
case 0x19: /* movw r1,r2 */
case 0x1A: /* movq r1,r2 */
case 0x1B: /* movt r1,r2 */
{
int i;
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
for ( i = 0; i < size; i++ )
cpustate->temp1[i] = cpustate->temp2[i];
write_regreg( cpustate, size, reg1, reg2 );
}
break;
case 0x1C: /* imskb r1,r2 */
case 0x1D: /* imskw r1,r2 */
case 0x1E: /* imskq r1,r2 */
case 0x1F: /* imskt r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_IMSK;
}
break;
case 0x20: /* shrb r1 */
case 0x21: /* shrw r1 */
case 0x22: /* shrq r1 */
case 0x23: /* shrt r1 */
/* Shift is a single shift! */
{
int i;
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 d1 = 0, d2 = 0;
read_reg( cpustate, size, reg1 );
for ( i = 0; i < size; i++ )
{
d1 = ( cpustate->temp1[i] & 0x01 ) << 7;
cpustate->temp1[i] = ( cpustate->temp1[i] >> 1 ) | d2;
d2 = d1;
}
write_reg( cpustate, size, reg1 );
}
break;
case 0x24: /* orb r1,r2 */
case 0x25: /* orb r1,r2 */
case 0x26: /* orb r1,r2 */
case 0x27: /* orb r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_OR;
write_regreg( cpustate, size, reg1, reg2 );
}
break;
case 0x28: /* shlb r1 */
case 0x29: /* shlw r1 */
case 0x2A: /* shlq r1 */
case 0x2B: /* shlt r1 */
/* Shift is a single shift! */
{
int i;
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 d1 = 0, d2 = 0;
read_reg( cpustate, size, reg1 );
for ( i = 0; i < size; i++ )
{
d1 = ( cpustate->temp1[i] & 0x80 ) >> 7;
cpustate->temp1[i] = ( cpustate->temp1[i] << 1 ) | d2;
d2 = d1;
}
write_reg( cpustate, size, reg1 );
}
break;
case 0x2C: /* andb r1,r2 */
case 0x2D: /* andw r1,r2 */
case 0x2E: /* andq r1,r2 */
case 0x2F: /* andt r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_AND;
write_regreg( cpustate, size, reg1, reg2 );
}
break;
case 0x34: /* subb r1,r2 */
case 0x35: /* subw r1,r2 */
case 0x36: /* subq r1,r2 */
case 0x37: /* subt r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_SUB;
write_regreg( cpustate, size, reg1, reg2 );
}
break;
case 0x38: /* adbb r1,r2 */
case 0x39: /* adbw r1,r2 */
case 0x3A: /* adbq r1,r2 */
case 0x3B: /* adbt r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_ADDB;
write_regreg( cpustate, size, reg1, reg2 );
}
break;
case 0x3C: /* addb r1,r2 */
case 0x3D: /* addw r1,r2 */
case 0x3E: /* addq r1,r2 */
case 0x3F: /* addt r1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_regreg( cpustate, size, reg1, reg2 );
HCD62121_ADD;
write_regreg( cpustate, size, reg1, reg2 );
}
break;
case 0x4C: /* testb ir1,r2 */
case 0x4D: /* testw ir1,r2 */
case 0x4E: /* testq ir1,r2 */
case 0x4F: /* testt ir1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_iregreg( cpustate, size, reg1, reg2 );
HCD62121_AND;
}
break;
case 0x54: /* cmpb ir1,r2 */
case 0x55: /* cmpw ir1,r2 */
case 0x56: /* cmpq ir1,r2 */
case 0x57: /* cmpt ir1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_iregreg( cpustate, size, reg1, reg2 );
HCD62121_SUB;
}
break;
case 0x58: /* movb ir1,r2 */
case 0x59: /* movw ir1,r2 */
case 0x5A: /* movq ir1,r2 */
case 0x5B: /* movt ir1,r2 */
{
int i;
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_iregreg( cpustate, size, reg1, reg2 );
for ( i = 0; i < size; i++ )
cpustate->temp1[i] = cpustate->temp2[i];
write_iregreg( cpustate, size, reg1, reg2 );
}
break;
case 0x64: /* orb ir1,r2 */
case 0x65: /* orb ir1,r2 */
case 0x66: /* orb ir1,r2 */
case 0x67: /* orb ir1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_iregreg( cpustate, size, reg1, reg2 );
HCD62121_OR;
write_iregreg( cpustate, size, reg1, reg2 );
}
break;
case 0x6C: /* andb ir1,r2 */
case 0x6D: /* andw ir1,r2 */
case 0x6E: /* andq ir1,r2 */
case 0x6F: /* andt ir1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_iregreg( cpustate, size, reg1, reg2 );
HCD62121_AND;
write_iregreg( cpustate, size, reg1, reg2 );
}
break;
case 0x7C: /* addb ir1,r2 */
case 0x7D: /* addw ir1,r2 */
case 0x7E: /* addq ir1,r2 */
case 0x7F: /* addt ir1,r2 */
{
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_iregreg( cpustate, size, reg1, reg2 );
HCD62121_ADD;
write_iregreg( cpustate, size, reg1, reg2 );
}
break;
case 0x88: /* jump _a16 */
cpustate->ip = ( read_op( cpustate ) << 8 ) | read_op( cpustate );
break;
case 0x89: /* jumpf cs:a16 */
{
UINT8 cs = read_op( cpustate );
UINT8 a1 = read_op( cpustate );
UINT8 a2 = read_op( cpustate );
cpustate->cseg = cs;
cpustate->ip = ( a1 << 8 ) | a2;
}
break;
case 0x8A: /* call a16 */
{
UINT8 a1 = read_op( cpustate );
UINT8 a2 = read_op( cpustate );
HCD62121_PUSHW( cpustate->ip );
cpustate->ip = ( a1 << 8 ) | a2;
}
break;
case 0x8C: /* unk_8C */
case 0x8D: /* unk_8D */
case 0x8E: /* unk_8E */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
break;
case 0x90: /* retzh */
case 0x91: /* retzl */
case 0x92: /* retc */
case 0x93: /* retz */
case 0x94: /* retzc */
case 0x95: /* retcl */
case 0x96: /* retnc */
case 0x97: /* retnz */
if ( check_cond( cpustate, op ) )
HCD62121_POPW( cpustate->ip );
break;
case 0x98: /* jump (r1) */
{
UINT8 reg1 = read_op( cpustate );
UINT16 ad = cpustate->reg[ ( reg1 | 0x40 ) & 0x7f ] << 8;
if ( reg1 & 0x40 )
ad |= cpustate->reg[ ( ( reg1 - 1 ) | 0x40 ) & 0x7f ];
else
ad |= cpustate->reg[ ( ( reg1 + 1 ) | 0x40 ) & 0x7f ];
cpustate->ip = ad;
}
break;
case 0x9F: /* ret */
HCD62121_POPW( cpustate->ip );
break;
case 0xA0: /* jmpzh a16 */
case 0xA1: /* jmpzl a16 */
case 0xA2: /* jmpc a16 */
case 0xA3: /* jmpz a16 */
case 0xA4: /* jmpzc a16 */
case 0xA5: /* jmpcl a16 */
case 0xA6: /* jmpnc a16 */
case 0xA7: /* jmpnz a16 */
{
UINT8 a1 = read_op( cpustate );
UINT8 a2 = read_op( cpustate );
if ( check_cond( cpustate, op ) )
cpustate->ip = ( a1 << 8 ) | a2;
}
break;
case 0xA8: /* callzh a16 */
case 0xA9: /* callzl a16 */
case 0xAA: /* callc a16 */
case 0xAB: /* callz a16 */
case 0xAC: /* callzc a16 */
case 0xAD: /* callcl a16 */
case 0xAE: /* callnc a16 */
case 0xAF: /* callnz a16 */
{
UINT8 a1 = read_op( cpustate );
UINT8 a2 = read_op( cpustate );
if ( check_cond( cpustate, op ) )
{
HCD62121_PUSHW( cpustate->ip );
cpustate->ip = ( a1 << 8 ) | a2;
}
}
break;
case 0xB1: /* unk_B1 reg/i8 */
case 0xB3: /* unk_B3 reg/i8 */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
read_op( cpustate );
break;
case 0xB4: /* out koh,reg */
io_writebyte( cpustate, HCD62121_KOH, cpustate->reg[ read_op( cpustate ) & 0x7f ] );
break;
case 0xB5: /* out koh,i8 */
io_writebyte( cpustate, HCD62121_KOH, read_op( cpustate ) );
break;
case 0xB6: /* out kol,reg */
io_writebyte( cpustate, HCD62121_KOL, cpustate->reg[ read_op( cpustate ) & 0x7f ] );
break;
case 0xB7: /* out kol,i8 */
io_writebyte( cpustate, HCD62121_KOL, read_op( cpustate ) );
break;
case 0xB9: /* unk_B9 reg/i8 */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
read_op( cpustate );
break;
case 0xBB: /* jmpcl? a16 */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
{
UINT8 a1 = read_op( cpustate );
UINT8 a2 = read_op( cpustate );
if ( cpustate->f & _FLAG_CL )
cpustate->ip = ( a1 << 8 ) | a2;
}
break;
case 0xBF: /* jmpncl? a16 */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
{
UINT8 a1 = read_op( cpustate );
UINT8 a2 = read_op( cpustate );
if ( ! ( cpustate->f & _FLAG_CL ) )
cpustate->ip = ( a1 << 8 ) | a2;
}
break;
case 0xC0: /* movb reg,i8 */
case 0xC1: /* movw reg,i16 */
case 0xC2: /* movw reg,i64 */
case 0xC3: /* movw reg,i80 */
{
int i;
int size = datasize( cpustate, op );
UINT8 reg = read_op( cpustate );
for( i = 0; i < size; i++ )
{
cpustate->reg[(reg + i) & 0x7f] = read_op( cpustate );
}
}
break;
case 0xC4: /* movb (lar),r1 / r1,(lar) */
case 0xC5: /* movw (lar),r1 / r1,(lar) */
case 0xC6: /* movq (lar),r1 / r1,(lar) */
case 0xC7: /* movt (lar),r1 / r1,(lar) */
{
int i;
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
int pre_inc = 0;
int post_inc = 1;
switch( reg1 & 0x60 )
{
case 0x00:
pre_inc = 0;
post_inc = 1;
break;
case 0x20:
pre_inc = 1;
post_inc = 0;
break;
case 0x40:
pre_inc = 0;
post_inc = -1;
break;
case 0x60:
pre_inc = -1;
post_inc = 0;
break;
}
if ( reg1 & 0x80 )
{
/* (lar) <- r1 */
for ( i = 0; i < size; i++ )
{
cpustate->lar += pre_inc;
mem_writebyte( cpustate, ( cpustate->dseg << 16 ) | cpustate->lar, cpustate->reg[ ( reg2 + i ) & 0x7f ] );
cpustate->lar += post_inc;
}
}
else
{
/* r1 <- (lar) */
for ( i = 0; i < size; i++ )
{
cpustate->lar += pre_inc;
cpustate->reg[ ( reg2 + i ) & 0x7f ] = mem_readbyte( cpustate, ( cpustate->dseg << 16 ) | cpustate->lar );
cpustate->lar += post_inc;
}
}
}
break;
case 0xCC: /* swapb ir1,r2 */
case 0xCD: /* swapw ir1,r2 */
case 0xCE: /* swapq ir1,r2 */
case 0xCF: /* swapt ir1,r2? */
{
int i;
int size = datasize( cpustate, op );
UINT8 reg1 = read_op( cpustate );
UINT8 reg2 = read_op( cpustate );
read_iregreg( cpustate, size, reg1, reg2 );
for ( i = 0; i < size; i++ )
{
UINT8 d = cpustate->temp1[i];
cpustate->temp1[i] = cpustate->temp2[i];
cpustate->temp2[i] = d;
}
write_iregreg( cpustate, size, reg1, reg2 );
write_iregreg2( cpustate, size, reg1, reg2 );
}
break;
case 0xD0: /* movb cs,reg */
cpustate->cseg = cpustate->reg[ read_op( cpustate ) & 0x7f ];
break;
case 0xD1: /* movb cs,i8 */
cpustate->cseg = read_op( cpustate );
break;
case 0xD2: /* movb dsize,reg */
cpustate->dsize = cpustate->reg[ read_op( cpustate ) & 0x7f ];
break;
case 0xD3: /* movb dsize,i8 */
cpustate->dsize = read_op( cpustate );
break;
case 0xD4: /* movb ss,reg */
cpustate->sseg = cpustate->reg[ read_op( cpustate ) & 0x7f ];
break;
case 0xD5: /* movb ss,i8 */
cpustate->sseg = read_op( cpustate );
break;
case 0xD6: /* movw sp,reg */
{
UINT8 reg1 = read_op( cpustate );
cpustate->sp = cpustate->reg[ reg1 & 0x7f ] | ( cpustate->reg[ ( reg1 + 1 ) & 0x7f ] << 8 );
}
break;
case 0xD7: /* movw sp,i16 */
cpustate->sp = read_op( cpustate) << 8;
cpustate->sp |= read_op( cpustate );
break;
case 0xD8: /* movb f,reg */
cpustate->f = cpustate->reg[ read_op( cpustate ) & 0x7f ];
break;
case 0xD9: /* movb f,i8 */
cpustate->f = read_op( cpustate );
break;
case 0xDC: /* movb ds,reg */
cpustate->dseg = cpustate->reg[ read_op( cpustate ) & 0x7f ];
break;
case 0xDD: /* movb ds,i8 */
cpustate->dseg = read_op( cpustate );
break;
case 0xDE: /* movw lar,reg */
{
UINT8 reg1 = read_op( cpustate );
cpustate->lar = cpustate->reg[ reg1 & 0x7f ] | ( cpustate->reg[ ( reg1 + 1 ) & 0x7f ] << 8 );
}
break;
case 0xE0: /* ld0,b? reg (in?) */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
{
UINT8 reg1 = read_op( cpustate );
/* This is incorrect. _Something_ gets stored to the register */
/* This is to hack around the testb instruction at 001039. */
cpustate->reg[ reg1 & 0x7f ] = 0x10;
}
break;
case 0xE1: /* unk_E1 reg/i8 (in?) */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
break;
case 0xE2: /* in kb, reg */
cpustate->reg[ read_op( cpustate ) & 0x7f ] = io_readbyte( cpustate, HCD62121_KI );
break;
case 0xE3: /* unk_e3 reg/i8 (in?) */
case 0xE4: /* unk_e4 reg/i8 (in?) */
case 0xE5: /* unk_e5 reg/i8 (in?) */
case 0xE6: /* unk_e6 reg/i8 (in?) */
case 0xE7: /* unk_e7 reg/i8 (in?) */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
read_op( cpustate );
break;
case 0xE8: /* movw r1,lar */
{
UINT8 reg1 = read_op( cpustate );
cpustate->reg[ reg1 & 0x7f ] = cpustate->lar & 0xff;
cpustate->reg[ ( reg1 + 1 ) & 0x7f ] = cpustate->lar >> 8;
}
break;
case 0xEB: /* movw reg,ss */
{
UINT8 reg1 = read_op( cpustate );
cpustate->reg[ reg1 & 0x7f ] = cpustate->sp & 0xff;
cpustate->reg[ ( reg1 + 1 ) & 0x7f ] = cpustate->sp >> 8;
}
break;
case 0xEF: /* movb reg,ss */
cpustate->reg[ read_op( cpustate ) & 0x7f ] = cpustate->sseg;
break;
case 0xF0: /* unk_F0 reg/i8 (out?) */
case 0xF1: /* unk_F1 reg/i8 (out?) */
case 0xF2: /* unk_F2 reg/i8 (out?) */
case 0xF3: /* unk_F3 reg/i8 (out?) */
case 0xF4: /* unk_F4 reg/i8 (out?) */
case 0xF5: /* unk_F5 reg/i8 (out?) */
case 0xF6: /* unk_F6 reg/i8 (out?) */
case 0xF7: /* unk_F7 reg/i8 (out?) */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
read_op( cpustate );
break;
case 0xFC: /* unk_FC */
case 0xFD: /* unk_FD */
case 0xFE: /* unk_FE */
logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
break;
case 0xFF: /* nop */
break;
default:
/*logerror*/fatalerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
break;

348
src/emu/cpu/hcd62121/hcd62121d.c Normal file
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@ -0,0 +1,348 @@
#include "emu.h"
#include "debugger.h"
#include "hcd62121.h"
enum
{
_REG=1, /* register */
_REGREG, /* register1, register2, or register2, register1 or register1, imm byte */
_IRG, /* register indirect */
_IRGREG, /* 2 register indirect */
_A16, /* 16bit address */
_A24, /* seg:address */
_F, /* flag register */
_CS, /* cs register */
_DS, /* ds register */
_SS, /* ss register */
_PC, /* program counter */
_SP, /* stack pointer */
_I8, /* immediate 8 bit value */
_I16, /* immediate 16 bit value */
_I64, /* immediate 64 bit value */
_I80, /* immediate 80 bit value */
_ILR, /* indirect last address register access */
_LAR, /* last address register */
_DSZ, /* dsize register? */
_TIM, /* timing related register? */
_KLO, /* KO1 - KO8 output lines */
_KHI, /* KO9 - KO14(?) output lines */
_KI, /* K input lines */
_4, /* for nibble shifts */
};
typedef struct
{
const char *str;
UINT8 arg1;
UINT8 arg2;
} hcd62121_dasm;
static const hcd62121_dasm hcd62121_ops[256] =
{
/* 0x00 */
{ "shlb", _REG, _4 }, { "shlw", _REG, _4 }, { "shlq", _REG, _4 }, { "shlt", _REG, _4 },
{ "mskb", _REGREG, 0 }, { "mskw", _REGREG, 0 }, { "mskq", _REGREG, 0 }, { "mskt", _REGREG, 0 },
{ "shrb", _REG, _4 }, { "shrw", _REG, _4 }, { "shrq", _REG, _4 }, { "shrt", _REG, _4 },
{ "tstb", _REGREG, 0 }, { "tstw", _REGREG, 0 }, { "tstq", _REGREG, 0 }, { "tstt", _REGREG, 0 },
{ "xorb", _REGREG, 0 }, { "xorw", _REGREG, 0 }, { "xorq", _REGREG, 0 }, { "xort", _REGREG, 0 },
{ "cmpb", _REGREG, 0 }, { "cmpw", _REGREG, 0 }, { "cmpq", _REGREG, 0 }, { "cmpt", _REGREG, 0 },
{ "movb", _REGREG, 0 }, { "movw", _REGREG, 0 }, { "movq", _REGREG, 0 }, { "movt", _REGREG, 0 },
{ "imskb", _REGREG, 0 }, { "imskw", _REGREG, 0 }, { "imskq", _REGREG, 0 }, { "imskt", _REGREG, 0 },
/* 0x20 */
{ "shrb", _REG, 0 }, { "shrw", _REG, 0 }, { "shrq", _REG, 0 }, { "shrt", _REG, 0 },
{ "orb", _REGREG, 0 }, { "orw", _REGREG, 0 }, { "orq", _REGREG, 0 }, { "ort", _REGREG, 0 },
{ "shlb", _REG, 0 }, { "shlw", _REG, 0 }, { "shlq", _REG, 0 }, { "shlt", _REG, 0 },
{ "andb", _REGREG, 0 }, { "andw", _REGREG, 0 }, { "andq", _REGREG, 0 }, { "andt", _REGREG, 0 },
{ "sbbb", _REGREG, 0 }, { "sbbw", _REGREG, 0 }, { "sbbq", _REGREG, 0 }, { "sbbt", _REGREG, 0 }, /* BCD SUB */
{ "subb", _REGREG, 0 }, { "subw", _REGREG, 0 }, { "subq", _REGREG, 0 }, { "subt", _REGREG, 0 },
{ "adbb", _REGREG, 0 }, { "adbw", _REGREG, 0 }, { "adbq", _REGREG, 0 }, { "adbt", _REGREG, 0 }, /* BCD ADD */
{ "addb", _REGREG, 0 }, { "addw", _REGREG, 0 }, { "addq", _REGREG, 0 }, { "addt", _REGREG, 0 },
/* 0x40 */
{ "shrb?", _IRG, 0 }, { "shrw?", _IRG, 0 }, { "shrq?", _IRG, 0 }, { "shrt?", _IRG, 0 },
{ "mskb", _IRGREG, 0 }, { "mskw", _IRGREG, 0 }, { "mskq", _IRGREG, 0 }, { "mskt", _IRGREG, 0 },
{ "shrb", _IRG, 0 }, { "shrw", _IRG, 0 }, { "shrq", _IRG, 0 }, { "shrt", _IRG, 0 },
{ "tstb", _IRGREG, 0 }, { "tstw", _IRGREG, 0 }, { "tstq", _IRGREG, 0 }, { "tstt", _IRGREG, 0 },
{ "xorb", _IRGREG, 0 }, { "xorw", _IRGREG, 0 }, { "xorq", _IRGREG, 0 }, { "xort", _IRGREG, 0 },
{ "cmpb", _IRGREG, 0 }, { "cmpw", _IRGREG, 0 }, { "cmpq", _IRGREG, 0 }, { "cmpt", _IRGREG, 0 },
{ "movb", _IRGREG, 0 }, { "movw", _IRGREG, 0 }, { "movq", _IRGREG, 0 }, { "movt", _IRGREG, 0 },
{ "imskb", _IRGREG, 0 }, { "imskw", _IRGREG, 0 }, { "imskq", _IRGREG, 0 }, { "imskt", _IRGREG, 0 },
/* 0x60 */
{ "shrb", _IRG, 0 }, { "shrw", _IRG, 0 }, { "shrq", _IRG, 0 }, { "shrt", _IRG, 0 },
{ "orb", _IRGREG, 0 }, { "orw", _IRGREG, 0 }, { "orq", _IRGREG, 0 }, { "ort", _IRGREG, 0 },
{ "shlb", _IRG, 0 }, { "shlw", _IRG, 0 }, { "shlq", _IRG, 0 }, { "shlt", _IRG, 0 },
{ "andb", _IRGREG, 0 }, { "andw", _IRGREG, 0 }, { "andq", _IRGREG, 0 }, { "andt", _IRGREG, 0 },
{ "sbbb", _IRGREG, 0 }, { "sbbw", _IRGREG, 0 }, { "sbbq", _IRGREG, 0 }, { "sbbt", _IRGREG, 0 }, /* BCD SUB */
{ "subb", _IRGREG, 0 }, { "subw", _IRGREG, 0 }, { "subq", _IRGREG, 0 }, { "subt", _IRGREG, 0 },
{ "adbb", _IRGREG, 0 }, { "adbw", _IRGREG, 0 }, { "adbq", _IRGREG, 0 }, { "adbt", _IRGREG, 0 }, /* BCD ADD */
{ "addb", _IRGREG, 0 }, { "addw", _IRGREG, 0 }, { "addq", _IRGREG, 0 }, { "addt", _IRGREG, 0 },
/* 0x80 */
{ "un80?", 0, 0 }, { "un81?", 0, 0 }, { "un82?", 0, 0 }, { "un83?", 0, 0 },
{ "un84?", 0, 0 }, { "un85?", 0, 0 }, { "un86?", 0, 0 }, { "un87?", 0, 0 },
{ "jump", _A16, 0 }, { "jump", _A24, 0 }, { "call", _A16, 0 }, { "un8b?", 0, 0 },
{ "un8C?", 0, 0 }, { "un8D?", 0, 0 }, { "un8E?", 0, 0 }, { "un8F?", 0, 0 },
{ "retzh", 0, 0 }, { "retzl", 0, 0 }, { "retc", 0, 0 }, { "retz", 0, 0 },
{ "retzc", 0, 0 }, { "retcl", 0, 0 }, { "retnc", 0, 0 }, { "retnz", 0, 0 },
{ "jump", _IRG, 0 }, { "un99?", 0, 0 }, { "un9A?", 0, 0 }, { "un9b?", 0, 0 },
{ "un9C?", 0, 0 }, { "un9D?", 0, 0 }, { "reti", 0, 0 }, { "ret", 0, 0 },
/* 0xa0 */
{ "jmpzh", _A16, 0 }, { "jmpzl", _A16, 0 }, { "jmpc", _A16, 0 }, { "jmpz", _A16, 0 },
{ "jmpzc", _A16, 0 }, { "jmpcl", _A16, 0 }, { "jmpnc", _A16, 0 }, { "jmpnz", _A16, 0 },
{ "callzh", _A16, 0 }, { "callzl", _A16, 0 }, { "callc", _A16, 0 }, { "callz", _A16, 0 },
{ "callzc", _A16, 0 }, { "callcl", _A16, 0 }, { "callnc", _A16, 0 }, { "callnz", _A16, 0 },
{ "unB0?", 0, 0 }, { "unB1?", _I8, 0 }, { "unB2?", 0, 0 }, { "unB3?", _I8, 0 },
{ "out", _KHI, _REG }, { "out", _KHI, _I8 }, { "out", _KLO, _REG }, { "out", _KLO, _I8 },
{ "unB8?", 0, 0 }, { "unB9?", _I8, 0 }, { "unBA?", 0, 0 }, { "jmpcl?", _A16, 0 },
{ "unBC?", 0, 0 }, { "unBD?", 0, 0 }, { "unBE?", 0, 0 }, { "jmpncl?", _A16, 0 },
/* 0xc0 */
{ "movb", _REG, _I8 }, { "movw", _REG, _I16 }, { "movq", _REG, _I64 }, { "movt", _REG, _I80 },
{ "movb", _ILR, _ILR }, { "movw", _ILR, _ILR }, { "movq", _ILR, _ILR }, { "movt", _ILR, _ILR },
{ "unC8?", 0, 0 }, { "unC9?", 0, 0 }, { "unCA?", 0, 0 }, { "unCb?", 0, 0 },
{ "swapb", _IRGREG, 0 }, { "swapw", _IRGREG, 0 }, { "swapq", _IRGREG, 0 }, { "swapt", _IRGREG, 0 },
{ "movb", _CS, _REG }, { "movb", _CS, _I8 }, { "movb", _DSZ, _REG }, { "movb", _DSZ, _I8 },
{ "movb", _SS, _REG }, { "movb", _SS, _I8 }, { "movw", _SP, _REG }, { "movw", _SP, _I16 },
{ "movb", _F, _REG }, { "movb", _F, _I8 }, { "unDA?", 0, 0 }, { "unDb?", 0, 0 },
{ "movb", _DS, _REG }, { "movb", _DS, _I8 }, { "movw", _LAR, _REG }, { "movw?", _LAR, _I16 },
/* 0xe0 */
{ "unE0?", _I8, 0 }, { "unE1?", _I8, 0 }, { "in", _REG, _KI }, { "movb", _REG, _DSZ },
{ "movb", _REG, _F }, { "movb", _REG, _TIM }, { "unE6?", _I8, 0 }, { "unE7?", _I8, 0 },
{ "movw", _REG, _LAR }, { "movw?", _REG, _LAR }, { "movw", _REG, _PC }, { "movw", _REG, _SP },
{ "unEC?", 0, 0 }, { "movb", _REG, _DS }, { "movb", _REG, _CS }, { "movb", _REG, _SS },
{ "unF0?", _I8, 0 }, { "unF1?", _I8, 0 }, { "unF2?", _I8, 0 }, { "unF3?", _I8, 0 },
{ "unF4?", _I8, 0 }, { "unF5?", _I8, 0 }, { "unF6?", _I8, 0 }, { "unF7?", _I8, 0 },
{ "unF8?", 0, 0 }, { "unF9?", 0, 0 }, { "unFA?", 0, 0 }, { "unFb?", 0, 0 },
{ "unFC?", 0, 0 }, { "unFD?", 0, 0 }, { "unFE?", 0, 0 }, { "nop", 0, 0 }
};
CPU_DISASSEMBLE( hcd62121 )
{
UINT8 op, op1=0, op2=0;
int pos = 0;
const hcd62121_dasm *inst;
op = oprom[pos++];
inst = &hcd62121_ops[op];
buffer += sprintf(buffer,"%-8s", inst->str);
switch( inst->arg1 )
{
case _REGREG:
op1 = oprom[pos++];
op2 = oprom[pos++];
if ( op1 & 0x80 )
{
buffer += sprintf( buffer, "r%02x,0x%02x", op1 & 0x7f, op2 );
}
else
{
if ( op2 & 0x80 )
buffer += sprintf( buffer, "r%02x,r%02x", op1 & 0x7f, op2 & 0x7f );
else
buffer += sprintf( buffer, "r%02x,r%02x", op2 & 0x7f, op1 & 0x7f );
}
break;
case _REG:
buffer += sprintf( buffer, "r%02x", oprom[pos++] & 0x7f );
break;
case _IRGREG:
/* bit 6 = direction. 0 - regular, 1 - reverse */
op1 = oprom[pos++];
op2 = oprom[pos++];
if ( op1 & 0x80 )
{
buffer += sprintf( buffer, "(r%02x),0x%02x", 0x40 | ( op1 & 0x3f ), op2 );
}
else
{
if ( op2 & 0x80 )
buffer += sprintf( buffer, "(r%02x%s),r%02x", 0x40 | ( op1 & 0x3f ), (op1 & 0x40) ? ".r" : "", op2 & 0x7f );
else
buffer += sprintf( buffer, "r%02x,(r%02x%s)", op2 & 0x7f, 0x40 | ( op1 & 0x3f ), (op1 & 0x40) ? ".r" : "" );
}
break;
case _IRG:
/* bit 6 = direction. 0 - regular, 1 - reverse */
op1 = oprom[pos++];
buffer += sprintf( buffer, "(r%02x%s)", 0x40 | ( op1 & 0x3f ), (op1 & 0x40) ? ".r" : "" );
break;
case _F:
buffer += sprintf( buffer, "F" );
break;
case _CS:
buffer += sprintf( buffer, "CS" );
break;
case _DS:
buffer += sprintf( buffer, "DS" );
break;
case _SS:
buffer += sprintf( buffer, "SS" );
break;
case _PC:
buffer += sprintf( buffer, "PC" );
break;
case _SP:
buffer += sprintf( buffer, "SP" );
break;
case _I8:
buffer += sprintf( buffer, "0x%02x", oprom[pos++] );
break;
case _I16:
case _A16:
buffer += sprintf( buffer, "0x%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
break;
case _I64:
buffer += sprintf( buffer, "0x%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
break;
case _I80:
buffer += sprintf( buffer, "0x%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
break;
case _A24:
buffer += sprintf( buffer, "0x%02x:", oprom[pos++] );
buffer += sprintf( buffer, "0x%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
break;
case _ILR:
op1 = oprom[pos++];
op2 = oprom[pos++];
if ( op1 & 0x80 )
{
/* (lar),reg */
buffer += sprintf( buffer, "(%slar%s),r%02x", (op1 & 0x20) ? ( (op1 & 0x40) ? "--" : "++" ) : "", (op1 & 0x20) ? "" : ( (op1 & 0x40) ? "--" : "++" ), op2 & 0x7f );
}
else
{
/* reg,(lar) */
buffer += sprintf( buffer, "r%02x,(%slar%s)", op2 & 0x7f, (op1 & 0x20) ? ( (op1 & 0x40) ? "--" : "++" ) : "", (op1 & 0x20) ? "" : ( (op1 & 0x40) ? "--" : "++" ) );
}
break;
case _LAR:
buffer += sprintf( buffer, "lar" );
break;
case _DSZ:
buffer += sprintf( buffer, "dsize" );
break;
case _TIM:
buffer += sprintf( buffer, "TIM?" );
break;
case _KLO:
buffer += sprintf( buffer, "KOL" );
break;
case _KHI:
buffer += sprintf( buffer, "KOH" );
break;
default:
break;
}
switch( inst->arg2 )
{
case _REG:
buffer += sprintf( buffer, ",r%02x", oprom[pos++] & 0x7f );
break;
case _F:
buffer += sprintf( buffer, ",F" );
break;
case _CS:
buffer += sprintf( buffer, ",CS" );
break;
case _DS:
buffer += sprintf( buffer, ",DS" );
break;
case _SS:
buffer += sprintf( buffer, ",SS" );
break;
case _PC:
buffer += sprintf( buffer, ",PC" );
break;
case _SP:
buffer += sprintf( buffer, ",SP" );
break;
case _I8:
buffer += sprintf( buffer, ",0x%02x", oprom[pos++] );
break;
case _I16:
case _A16:
buffer += sprintf( buffer, ",0x%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
break;
case _I64:
buffer += sprintf( buffer, ",0x%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
break;
case _I80:
buffer += sprintf( buffer, ",0x%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
break;
case _A24:
buffer += sprintf( buffer, ",0x%02x:", oprom[pos++] );
buffer += sprintf( buffer, "0x%02x", oprom[pos++] );
buffer += sprintf( buffer, "%02x", oprom[pos++] );
break;
case _ILR:
/* Implemented by _ILR section for arg1 */
break;
case _LAR:
buffer += sprintf( buffer, ",lar" );
break;
case _DSZ:
buffer += sprintf( buffer, ",dsize" );
break;
case _TIM:
buffer += sprintf( buffer, ",TIM?" );
break;
case _KI:
buffer += sprintf( buffer, ",KI" );
break;
case _4:
buffer += sprintf( buffer, ",4" );
break;
default:
break;
}
return pos | DASMFLAG_SUPPORTED;
}