diff --git a/src/devices/cpu/rii/riidasm.cpp b/src/devices/cpu/rii/riidasm.cpp
index 6cc0d85a384..ab27b3fa291 100644
--- a/src/devices/cpu/rii/riidasm.cpp
+++ b/src/devices/cpu/rii/riidasm.cpp
@@ -4,7 +4,6 @@
 
     ELAN Microelectronics RISC II (RII) Series disassembler
 
-
 ***************************************************************************/
 
 #include "emu.h"
@@ -61,6 +60,11 @@ void riscii_disassembler::format_immediate(std::ostream &stream, u8 data) const
 	util::stream_format(stream, "%02Xh", data);
 }
 
+void riscii_disassembler::format_address(std::ostream &stream, u32 dst) const
+{
+	util::stream_format(stream, "%05Xh", dst);
+}
+
 offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const riscii_disassembler::data_buffer &opcodes, const riscii_disassembler::data_buffer &params)
 {
 	u16 opcode = opcodes.r16(pc);
@@ -70,8 +74,8 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 	{
 		if (BIT(opcode, 14))
 		{
-			u32 dst = (pc & 0x3e000) | (opcode & 0x1fff);
-			util::stream_format(stream, "%-8s%05X", BIT(opcode, 13) ? "SCALL" : "SJMP", dst);
+			util::stream_format(stream, "%-8s", BIT(opcode, 13) ? "SCALL" : "SJMP");
+			format_address(stream, (pc & 0x3e000) | (opcode & 0x1fff));
 			if (BIT(opcode, 13))
 				words |= STEP_OVER;
 		}
@@ -105,18 +109,18 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 			stream << "SLEP";
 		else if ((opcode & 0x00f0) == 0x0020)
 		{
-			u32 dst = u32(opcode & 0x000f) << 16 | opcodes.r16(pc + 1);
-			util::stream_format(stream, "%-8s%05X", "LJMP", dst);
+			util::stream_format(stream, "%-8s", "LJMP");
+			format_address(stream, u32(opcode & 0x000f) << 16 | opcodes.r16(pc + 1));
 			words = 2;
 		}
 		else if ((opcode & 0x00f0) == 0x0030)
 		{
-			u32 dst = u32(opcode & 0x000f) << 16 | opcodes.r16(pc + 1);
-			util::stream_format(stream, "%-8s%05X", "LCALL", dst);
+			util::stream_format(stream, "%-8s", "LCALL");
+			format_address(stream, u32(opcode & 0x000f) << 16 | opcodes.r16(pc + 1));
 			words = 2 | STEP_OVER;
 		}
 		else
-			stream << "???";
+			util::stream_format(stream, "%-8s%04Xh", "DW", opcode);
 		break;
 
 	case 0x0200:
@@ -333,7 +337,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 			break;
 
 		default:
-			stream << "???";
+			util::stream_format(stream, "%-8s%04Xh", "DW", opcode);
 			break;
 		}
 		break;
@@ -362,7 +366,8 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 	case 0x3400: case 0x3500: case 0x3600: case 0x3700:
 	case 0x3800: case 0x3900: case 0x3a00: case 0x3b00:
 	case 0x3c00: case 0x3d00: case 0x3e00: case 0x3f00:
-		util::stream_format(stream, "%-8s%05X", "S0CALL", opcode & 0x0fff);
+		util::stream_format(stream, "%-8s", "S0CALL");
+		format_address(stream, opcode & 0x0fff);
 		words |= STEP_OVER;
 		break;
 
@@ -404,21 +409,24 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 	case 0x4700:
 		util::stream_format(stream, "%-8sA,", "JGE");
 		format_immediate(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
 	case 0x4800:
 		util::stream_format(stream, "%-8sA,", "JLE");
 		format_immediate(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
 	case 0x4900:
 		util::stream_format(stream, "%-8sA,", "JE");
 		format_immediate(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
@@ -455,49 +463,56 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 	case 0x5000:
 		util::stream_format(stream, "%-8sA,", "JDNZ");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
 	case 0x5100:
 		util::stream_format(stream, "%-8s", "JDNZ");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
 	case 0x5200:
 		util::stream_format(stream, "%-8sA,", "JINZ");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
 	case 0x5300:
 		util::stream_format(stream, "%-8s", "JINZ");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
 	case 0x5500:
 		util::stream_format(stream, "%-8sA,", "JGE");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
 	case 0x5600:
 		util::stream_format(stream, "%-8sA,", "JLE");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
 	case 0x5700:
 		util::stream_format(stream, "%-8sA,", "JE");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%05X", (pc & 0x30000) | opcodes.r16(pc + 1));
+		stream << ",";
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
@@ -505,7 +520,8 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 	case 0x5c00: case 0x5d00: case 0x5e00: case 0x5f00:
 		util::stream_format(stream, "%-8s", "JBC");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%d,%05X", (opcode & 0x0700) >> 8, (pc & 0x30000) | opcodes.r16(pc + 1));
+		util::stream_format(stream, ",%d,", (opcode & 0x0700) >> 8);
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
@@ -513,7 +529,8 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 	case 0x6400: case 0x6500: case 0x6600: case 0x6700:
 		util::stream_format(stream, "%-8s", "JBS");
 		format_register(stream, opcode & 0x00ff);
-		util::stream_format(stream, ",%d,%05X", (opcode & 0x0700) >> 8, (pc & 0x30000) | opcodes.r16(pc + 1));
+		util::stream_format(stream, ",%d,", (opcode & 0x0700) >> 8);
+		format_address(stream, (pc & 0x30000) | opcodes.r16(pc + 1));
 		words = 2;
 		break;
 
@@ -539,7 +556,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r
 		break;
 
 	default:
-		stream << "???";
+		util::stream_format(stream, "%-8s%04Xh", "DW", opcode);
 		break;
 
 	}
diff --git a/src/devices/cpu/rii/riidasm.h b/src/devices/cpu/rii/riidasm.h
index eba4b9a7ab9..7c2ffb80bff 100644
--- a/src/devices/cpu/rii/riidasm.h
+++ b/src/devices/cpu/rii/riidasm.h
@@ -25,6 +25,7 @@ private:
 	// internal helpers
 	void format_register(std::ostream &stream, u8 reg) const;
 	void format_immediate(std::ostream &stream, u8 data) const;
+	void format_address(std::ostream &stream, u32 dst) const;
 
 	// register names
 	const char *const *m_regs;
diff --git a/src/devices/cpu/rii/riscii.cpp b/src/devices/cpu/rii/riscii.cpp
index cf2101295a3..ea1b95594ab 100644
--- a/src/devices/cpu/rii/riscii.cpp
+++ b/src/devices/cpu/rii/riscii.cpp
@@ -6,7 +6,9 @@
 
     Architecture is very similar to the GI/Microchip PIC series, with
     16-bit opcodes and a banked 8-bit register file with special registers
-    for indirect access. (It has no relation to Berkeley RISC II.)
+    for indirect access. (It has no relation to Berkeley RISC II. Elan's
+    first generation of PIC-like microcontrollers, the EM78 series, has
+    13-bit opcodes.)
 
     Currently this device is just a stub with no actual execution core.