mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
Add support for showing will branch/will fall through comment on SPARC branches under the cursor
Disabled until we can get a hook to refress the instructions under PC when stepping
This commit is contained in:
Vas Crabb
parent
5aa83a011d
commit
d3b553728d
@ -33,7 +33,7 @@ const int mb86901_device::NWINDOWS = 7;
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mb86901_device::mb86901_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: cpu_device(mconfig, MB86901, "Fujitsu MB86901", tag, owner, clock, "mb86901", __FILE__)
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, m_program_config("program", ENDIANNESS_BIG, 32, 32)
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, m_dasm(7)
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, m_dasm(this, 7)
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{
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}
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@ -2944,3 +2944,61 @@ void mb86901_device::execute_run()
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--m_icount;
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}
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}
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//-------------------------------------------------
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// get_reg_r - get integer register value for
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// disassembler
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//-------------------------------------------------
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UINT64 mb86901_device::get_reg_r(unsigned index) const
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{
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return REG(index & 31);
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}
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//-------------------------------------------------
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// get_reg_pc - get program counter value for
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// disassembler
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//-------------------------------------------------
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UINT64 mb86901_device::get_translated_pc() const
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{
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// FIXME: how do we apply translation to the address so it's in the same space the disassembler sees?
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return m_pc;
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}
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//-------------------------------------------------
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// get_icc - get integer condition codes for
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// disassembler
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//-------------------------------------------------
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UINT8 mb86901_device::get_icc() const
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{
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return m_icc;
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}
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//-------------------------------------------------
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// get_icc - get extended integer condition codes
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// for disassembler
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//-------------------------------------------------
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UINT8 mb86901_device::get_xcc() const
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{
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// not present before SPARCv9
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return 0;
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}
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//-------------------------------------------------
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// get_icc - get extended integer condition codes
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// for disassembler
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//-------------------------------------------------
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UINT8 mb86901_device::get_fcc(unsigned index) const
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{
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// only one fcc instance before SPARCv9
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return (m_fsr >> 10) & 3;
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}
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@ -47,7 +47,7 @@
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#define MCFG_SPARC_ADD_ASI_DESC(desc) \
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mb86901_device::add_asi_desc(*device, desc);
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class mb86901_device : public cpu_device
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class mb86901_device : public cpu_device, protected sparc_debug_state
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{
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public:
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mb86901_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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@ -137,6 +137,13 @@ protected:
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UINT32 read_sized_word(UINT8 asi, UINT32 address, int size);
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void write_sized_word(UINT8 asi, UINT32 address, UINT32 data, int size);
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// helpers for the disassembler
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virtual UINT64 get_reg_r(unsigned index) const override;
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virtual UINT64 get_translated_pc() const override;
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virtual UINT8 get_icc() const override;
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virtual UINT8 get_xcc() const override;
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virtual UINT8 get_fcc(unsigned index) const override;
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// general-purpose registers
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UINT32 m_r[120];
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@ -16,6 +16,72 @@ namespace {
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INT32 get_disp16(UINT32 op) { return DISP19; }
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INT32 get_disp19(UINT32 op) { return DISP19; }
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INT32 get_disp22(UINT32 op) { return DISP19; }
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const char *bicc_comment(const sparc_debug_state *state, bool use_cc, offs_t pc, UINT32 op)
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{
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if (!state || (state->get_translated_pc() != pc)) return nullptr;
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auto const cc((use_cc && (BRCC & 0x2)) ? state->get_xcc() : state->get_icc());
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switch (COND)
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{
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case 0x0: return "will fall through";
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case 0x1: return (cc & 0x4) ? "will branch" : "will fall through";
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case 0x2: return ((cc & 0x04) | ((cc ^ (cc >> 2)) & 0x2)) ? "will branch" : "will fall through";
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case 0x3: return ((cc ^ (cc >> 2)) & 0x2) ? "will branch" : "will fall through";
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case 0x4: return (cc & 0x5) ? "will branch" : "will fall through";
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case 0x5: return (cc & 0x1) ? "will branch" : "will fall through";
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case 0x6: return (cc & 0x8) ? "will branch" : "will fall through";
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case 0x7: return (cc & 0x2) ? "will branch" : "will fall through";
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case 0x8: return "will branch";
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case 0x9: return (cc & 0x4) ? "will fall through" : "will branch";
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case 0xa: return ((cc & 0x04) | ((cc ^ (cc >> 2)) & 0x2)) ? "will fall through" : "will branch";
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case 0xb: return ((cc ^ (cc >> 2)) & 0x2) ? "will fall through" : "will branch";
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case 0xc: return (cc & 0x5) ? "will fall through" : "will branch";
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case 0xd: return (cc & 0x1) ? "will fall through" : "will branch";
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case 0xe: return (cc & 0x8) ? "will fall through" : "will branch";
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case 0xf: return (cc & 0x2) ? "will fall through" : "will branch";
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}
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return nullptr;
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}
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const char *bfcc_comment(const sparc_debug_state *state, bool use_cc, offs_t pc, UINT32 op)
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{
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if (!state || (state->get_translated_pc() != pc)) return nullptr;
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auto const fcc(state->get_fcc(use_cc ? BRCC : 0));
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switch (COND)
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{
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case 0x0: return "will fall through";
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case 0x1: return ((fcc == 1) || (fcc == 2) || (fcc == 3)) ? "will branch" : "will fall through";
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case 0x2: return ((fcc == 1) || (fcc == 2)) ? "will branch" : "will fall through";
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case 0x3: return ((fcc == 1) || (fcc == 3)) ? "will branch" : "will fall through";
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case 0x4: return (fcc == 1) ? "will branch" : "will fall through";
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case 0x5: return ((fcc == 2) || (fcc == 3)) ? "will branch" : "will fall through";
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case 0x6: return (fcc == 2) ? "will branch" : "will fall through";
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case 0x7: return (fcc == 3) ? "will branch" : "will fall through";
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case 0x8: return "will branch";
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case 0x9: return (fcc == 0) ? "will branch" : "will fall through";
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case 0xa: return ((fcc == 0) || (fcc == 3)) ? "will branch" : "will fall through";
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case 0xb: return ((fcc == 0) || (fcc == 2)) ? "will branch" : "will fall through";
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case 0xc: return ((fcc == 0) || (fcc == 2) || (fcc == 3)) ? "will branch" : "will fall through";
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case 0xd: return ((fcc == 0) || (fcc == 1)) ? "will branch" : "will fall through";
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case 0xe: return ((fcc == 0) || (fcc == 1) || (fcc == 3)) ? "will branch" : "will fall through";
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case 0xf: return ((fcc == 0) || (fcc == 1) || (fcc == 2)) ? "will branch" : "will fall through";
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}
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return nullptr;
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}
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const char *bpr_comment(const sparc_debug_state *state, bool use_cc, offs_t pc, UINT32 op)
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{
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if (!state || (state->get_translated_pc() != pc)) return nullptr;
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const INT64 reg(state->get_reg_r(RS1));
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switch (COND)
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{
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case 1: return (reg == 0) ? "will branch" : "will fall through";
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case 2: return (reg <= 0) ? "will branch" : "will fall through";
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case 3: return (reg < 0) ? "will branch" : "will fall through";
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case 5: return (reg != 0) ? "will branch" : "will fall through";
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case 6: return (reg > 0) ? "will branch" : "will fall through";
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case 7: return (reg >= 0) ? "will branch" : "will fall through";
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}
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return nullptr;
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}
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}
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const char * const sparc_disassembler::REG_NAMES[32] = {
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@ -26,7 +92,7 @@ const char * const sparc_disassembler::REG_NAMES[32] = {
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};
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const sparc_disassembler::branch_desc sparc_disassembler::EMPTY_BRANCH_DESC = {
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nullptr, 0, false, false,
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nullptr, nullptr, 0, false, false,
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{ nullptr, nullptr, nullptr, nullptr },
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{
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nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr,
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@ -35,7 +101,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::EMPTY_BRANCH_DESC = {
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};
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const sparc_disassembler::branch_desc sparc_disassembler::BPCC_DESC = {
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&get_disp19, 6, true, true,
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&get_disp19, &bicc_comment, 6, true, true,
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{ "%icc", nullptr, "%xcc", nullptr },
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{
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"bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs",
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@ -44,7 +110,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::BPCC_DESC = {
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};
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const sparc_disassembler::branch_desc sparc_disassembler::BICC_DESC = {
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&get_disp22, 6, false, false,
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&get_disp22, &bicc_comment, 6, false, false,
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{ nullptr, nullptr, nullptr, nullptr },
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{
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"bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs",
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@ -53,7 +119,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::BICC_DESC = {
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};
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const sparc_disassembler::branch_desc sparc_disassembler::BPR_DESC = {
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&get_disp16, 5, true, false,
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&get_disp16, &bpr_comment, 5, true, false,
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{ nullptr, nullptr, nullptr, nullptr },
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{
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nullptr, "brz", "brlez", "brlz", nullptr, "brnz", "brgz", "brgez",
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@ -62,7 +128,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::BPR_DESC = {
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};
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const sparc_disassembler::branch_desc sparc_disassembler::FBPFCC_DESC = {
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&get_disp19, 6, true, true,
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&get_disp19, &bfcc_comment, 6, true, true,
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{ "%fcc0", "%fcc1", "%fcc2", "%fcc3" },
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{
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"fbn", "fbne", "fblg", "fbul", "fbl", "fbug", "fbg", "fbu",
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@ -71,7 +137,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::FBPFCC_DESC = {
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};
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const sparc_disassembler::branch_desc sparc_disassembler::FBFCC_DESC = {
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&get_disp22, 6, false, false,
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&get_disp22, &bfcc_comment, 6, false, false,
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{ nullptr, nullptr, nullptr, nullptr },
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{
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"fbn", "fbne", "fblg", "fbul", "fbl", "fbug", "fbg", "fbu",
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@ -80,7 +146,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::FBFCC_DESC = {
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};
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const sparc_disassembler::branch_desc sparc_disassembler::CBCCC_DESC = {
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&get_disp22, 6, false, false,
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&get_disp22, nullptr, 6, false, false,
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{ nullptr, nullptr, nullptr, nullptr },
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{
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"cbn", "cb123", "cb12", "cb13", "cb1", "cb23", "cb2", "cb3",
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@ -551,13 +617,14 @@ inline void sparc_disassembler::print(char *&output, const char *fmt, ...)
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}
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sparc_disassembler::sparc_disassembler(unsigned version)
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: sparc_disassembler(version, vis_none)
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sparc_disassembler::sparc_disassembler(const sparc_debug_state *state, unsigned version)
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: sparc_disassembler(state, version, vis_none)
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{
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}
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sparc_disassembler::sparc_disassembler(unsigned version, vis_level vis)
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: m_version(version)
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sparc_disassembler::sparc_disassembler(const sparc_debug_state *state, unsigned version, vis_level vis)
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: m_state(state)
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, m_version(version)
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, m_vis_level(vis)
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, m_op_field_width(9)
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, m_branch_desc{
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@ -986,12 +1053,14 @@ offs_t sparc_disassembler::dasm_branch(char *buf, offs_t pc, UINT32 op) const
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const char * const mnemonic(desc.mnemonic[COND]);
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if (!mnemonic || (desc.use_cc && !desc.reg_cc[BRCC])) return dasm_invalid(buf, pc, op);
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print(ptr, "%s%s%s", mnemonic, ANNUL ? ",a" : "", (m_branch_desc[OP2].use_pred && !PRED) ? ",pn" : "");
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print(ptr, "%s%s%s", mnemonic, ANNUL ? ",a" : "", (desc.use_pred && !PRED) ? ",pn" : "");
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pad_op_field(buf, ptr);
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if (desc.use_cc) print(ptr, "%s,", desc.reg_cc[BRCC]);
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if (OP2 == 3) print(ptr, "%s,", REG_NAMES[RS1]);
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const INT32 disp(desc.get_disp(op));
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print(ptr, "%%pc%c0x%0*x ! 0x%08x", (disp < 0) ? '-' : '+', desc.disp_width, std::abs(disp), pc + disp);
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//const char * const comment(desc.get_comment ? desc.get_comment(m_state, desc.use_cc, pc, op) : nullptr);
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//if (comment) print(ptr, " - %s", comment);
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return 4 | DASMFLAG_SUPPORTED;
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}
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@ -12,6 +12,20 @@
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#include <map>
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class sparc_debug_state
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{
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public:
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virtual UINT64 get_reg_r(unsigned index) const = 0;
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virtual UINT64 get_translated_pc() const = 0;
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virtual UINT8 get_icc() const = 0;
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virtual UINT8 get_xcc() const = 0;
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virtual UINT8 get_fcc(unsigned index) const = 0; // ?><=
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protected:
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~sparc_debug_state() { }
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};
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class sparc_disassembler
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{
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public:
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@ -44,8 +58,8 @@ public:
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};
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typedef std::map<UINT8, prftch_desc> prftch_desc_map;
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sparc_disassembler(unsigned version);
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sparc_disassembler(unsigned version, vis_level vis);
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sparc_disassembler(const sparc_debug_state *state, unsigned version);
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sparc_disassembler(const sparc_debug_state *state, unsigned version, vis_level vis);
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template <typename T> void add_state_reg_desc(const T &desc)
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{
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@ -98,6 +112,7 @@ private:
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struct branch_desc
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{
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INT32 (*get_disp)(UINT32 op);
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const char * (*get_comment)(const sparc_debug_state *state, bool use_cc, offs_t pc, UINT32 op);
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int disp_width;
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bool use_pred, use_cc;
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const char *reg_cc[4];
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@ -223,18 +238,19 @@ private:
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static const vis_op_desc_map::value_type VIS3_OP_DESC[];
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static const vis_op_desc_map::value_type VIS3B_OP_DESC[];
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unsigned m_version;
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vis_level m_vis_level;
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int m_op_field_width;
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branch_desc m_branch_desc[8];
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int_op_desc_map m_int_op_desc;
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state_reg_desc_map m_state_reg_desc;
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fpop1_desc_map m_fpop1_desc;
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fpop2_desc_map m_fpop2_desc;
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ldst_desc_map m_ldst_desc;
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asi_desc_map m_asi_desc;
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prftch_desc_map m_prftch_desc;
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vis_op_desc_map m_vis_op_desc;
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const sparc_debug_state *m_state;
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unsigned m_version;
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vis_level m_vis_level;
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int m_op_field_width;
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branch_desc m_branch_desc[8];
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int_op_desc_map m_int_op_desc;
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state_reg_desc_map m_state_reg_desc;
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fpop1_desc_map m_fpop1_desc;
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fpop2_desc_map m_fpop2_desc;
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ldst_desc_map m_ldst_desc;
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asi_desc_map m_asi_desc;
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prftch_desc_map m_prftch_desc;
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vis_op_desc_map m_vis_op_desc;
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};
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#endif // MAME_DEVICES_CPU_SPARC_SPARC_DASM_H
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@ -212,14 +212,14 @@ CPU_DISASSEMBLE( z8 );
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CPU_DISASSEMBLE( z80 );
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CPU_DISASSEMBLE( z8000 );
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CPU_DISASSEMBLE( sparcv7 ) { static sparc_disassembler dasm(7); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE(sparcv8) { static sparc_disassembler dasm(8); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE(sparcv9) { static sparc_disassembler dasm(9); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE(sparcv9vis1) { static sparc_disassembler dasm(9, sparc_disassembler::vis_1); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE(sparcv9vis2) { static sparc_disassembler dasm(9, sparc_disassembler::vis_2); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE(sparcv9vis2p) { static sparc_disassembler dasm(9, sparc_disassembler::vis_2p); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE(sparcv9vis3) { static sparc_disassembler dasm(9, sparc_disassembler::vis_3); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE(sparcv9vis3b) { static sparc_disassembler dasm(9, sparc_disassembler::vis_3b); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE( sparcv7 ) { static sparc_disassembler dasm(nullptr, 7); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE( sparcv8 ) { static sparc_disassembler dasm(nullptr, 8); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE( sparcv9 ) { static sparc_disassembler dasm(nullptr, 9); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE( sparcv9vis1 ) { static sparc_disassembler dasm(nullptr, 9, sparc_disassembler::vis_1); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE( sparcv9vis2 ) { static sparc_disassembler dasm(nullptr, 9, sparc_disassembler::vis_2); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE( sparcv9vis2p ) { static sparc_disassembler dasm(nullptr, 9, sparc_disassembler::vis_2p); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE( sparcv9vis3 ) { static sparc_disassembler dasm(nullptr, 9, sparc_disassembler::vis_3); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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CPU_DISASSEMBLE( sparcv9vis3b ) { static sparc_disassembler dasm(nullptr, 9, sparc_disassembler::vis_3b); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
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|
||||
static const dasm_table_entry dasm_table[] =
|
||||
|
||||
Loading…
Reference in New Issue
Block a user