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h8500: Add mode control and EPROM variant types

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This commit is contained in:
AJR 2021-06-20 12:22:53 -04:00
parent 976e707ffe
commit d40706395b
11 changed files with 84 additions and 16 deletions
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3
src/devices/cpu/h8500/h8500.cpp
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@ -12,10 +12,11 @@
#include "h8500.h"
#include "h8500dasm.h"
h8500_device::h8500_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int addrbits, int buswidth, int ramsize, address_map_constructor map)
h8500_device::h8500_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int addrbits, int buswidth, int ramsize, int defmode, address_map_constructor map)
: cpu_device(mconfig, type, tag, owner, clock)
, m_program_config("program", ENDIANNESS_BIG, buswidth, addrbits, 0, map)
, m_ram_config("internal RAM", ENDIANNESS_BIG, 16, ramsize, 0, address_map_constructor(FUNC(h8500_device::ram_map), this))
, m_mode_control(defmode)
, m_pc(0)
, m_ppc(0)
, m_sr(0)

10
src/devices/cpu/h8500/h8500.h
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@ -18,8 +18,10 @@ public:
H8500_R4, H8500_R5, H8500_FP, H8500_SP
};
void set_mode(u8 mode) { assert(!configured()); m_mode_control = mode; }
protected:
h8500_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int addrbits, int buswidth, int ramsize, address_map_constructor map);
h8500_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int addrbits, int buswidth, int ramsize, int defmode, address_map_constructor map);
// device-level overrides
virtual void device_config_complete() override;
@ -40,7 +42,8 @@ protected:
// device_state_interface overrides
virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
virtual bool h8_maximum_mode() const noexcept { return true; }
u8 mode_control() const { return m_mode_control; }
virtual bool h8_maximum_mode() const noexcept { return m_mode_control == 3 || m_mode_control == 4; } // all except H8/570
private:
void ram_map(address_map &map);
@ -52,6 +55,9 @@ private:
address_space *m_program;
memory_access<11, 1, 0, ENDIANNESS_BIG>::cache m_ram_cache;
// misc. configuration
u8 m_mode_control;
// internal registers
u16 m_pc;
u16 m_ppc;

2
src/devices/cpu/h8500/h8510.cpp
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@ -12,7 +12,7 @@
DEFINE_DEVICE_TYPE(HD6415108, hd6415108_device, "hd6415108", "Hitachi HD6415108 (H8/510)")
h8510_device::h8510_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
: h8500_device(mconfig, type, tag, owner, clock, 24, 16, 0, address_map_constructor(FUNC(h8510_device::internal_map), this))
: h8500_device(mconfig, type, tag, owner, clock, 24, 16, 0, 4, address_map_constructor(FUNC(h8510_device::internal_map), this))
{
}

11
src/devices/cpu/h8500/h8520.cpp
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@ -10,9 +10,10 @@
#include "h8520.h"
DEFINE_DEVICE_TYPE(HD6435208, hd6435208_device, "hd6435208", "Hitachi HD6435208 (H8/520)")
DEFINE_DEVICE_TYPE(HD6475208, hd6475208_device, "hd6475208", "Hitachi HD6475208 (H8/520)")
h8520_device::h8520_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
: h8500_device(mconfig, type, tag, owner, clock, 20, 8, 9, address_map_constructor(FUNC(h8520_device::internal_map), this))
: h8500_device(mconfig, type, tag, owner, clock, 20, 8, 9, 4, address_map_constructor(FUNC(h8520_device::internal_map), this))
{
}
@ -21,9 +22,15 @@ hd6435208_device::hd6435208_device(const machine_config &mconfig, const char *ta
{
}
hd6475208_device::hd6475208_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: h8520_device(mconfig, HD6475208, tag, owner, clock)
{
}
void h8520_device::internal_map(address_map &map)
{
map(0x0000, 0x3fff).rom().region(DEVICE_SELF, 0); // modes 2, 4, 7
if (mode_control() == 2 || mode_control() == 4 || mode_control() == 7)
map(0x0000, 0x3fff).rom().region(DEVICE_SELF, 0);
#if 0
map(0xff80, 0xff80).w(FUNC(h8520_device::p1ddr_w));
map(0xff81, 0xff81).w(FUNC(h8520_device::p2ddr_w));

8
src/devices/cpu/h8500/h8520.h
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@ -24,6 +24,14 @@ public:
hd6435208_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
};
class hd6475208_device : public h8520_device
{
public:
// device type constructor
hd6475208_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
};
DECLARE_DEVICE_TYPE(HD6435208, hd6435208_device)
DECLARE_DEVICE_TYPE(HD6475208, hd6475208_device)
#endif // MAME_CPU_H8500_H8520_H

11
src/devices/cpu/h8500/h8532.cpp
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@ -10,9 +10,10 @@
#include "h8532.h"
DEFINE_DEVICE_TYPE(HD6435328, hd6435328_device, "hd6435328", "Hitachi HD6435328 (H8/532)")
DEFINE_DEVICE_TYPE(HD6475328, hd6475328_device, "hd6475328", "Hitachi HD6475328 (H8/532)")
h8532_device::h8532_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
: h8500_device(mconfig, type, tag, owner, clock, 20, 8, 10, address_map_constructor(FUNC(h8532_device::internal_map), this))
: h8500_device(mconfig, type, tag, owner, clock, 20, 8, 10, 4, address_map_constructor(FUNC(h8532_device::internal_map), this))
{
}
@ -21,9 +22,15 @@ hd6435328_device::hd6435328_device(const machine_config &mconfig, const char *ta
{
}
hd6475328_device::hd6475328_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: h8532_device(mconfig, HD6475328, tag, owner, clock)
{
}
void h8532_device::internal_map(address_map &map)
{
map(0x0000, 0x7fff).rom().region(DEVICE_SELF, 0); // modes 2, 4, 7
if (mode_control() == 2 || mode_control() == 4 || mode_control() == 7)
map(0x0000, 0x7fff).rom().region(DEVICE_SELF, 0);
#if 0
map(0xff80, 0xff80).w(FUNC(h8532_device::p1ddr_w));
map(0xff81, 0xff81).w(FUNC(h8532_device::p2ddr_w));

8
src/devices/cpu/h8500/h8532.h
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@ -24,6 +24,14 @@ public:
hd6435328_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
};
class hd6475328_device : public h8532_device
{
public:
// device type constructor
hd6475328_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
};
DECLARE_DEVICE_TYPE(HD6435328, hd6435328_device)
DECLARE_DEVICE_TYPE(HD6475328, hd6475328_device)
#endif // MAME_CPU_H8500_H8532_H

23
src/devices/cpu/h8500/h8534.cpp
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@ -9,11 +9,13 @@
#include "emu.h"
#include "h8534.h"
DEFINE_DEVICE_TYPE(HD6435348, hd6435348_device, "hd6435348", "Hitachi HD6435348 (H8/534)")
DEFINE_DEVICE_TYPE(HD6475348, hd6475348_device, "hd6475348", "Hitachi HD6475348 (H8/534)")
DEFINE_DEVICE_TYPE(HD6435368, hd6435368_device, "hd6435368", "Hitachi HD6435368 (H8/536)")
DEFINE_DEVICE_TYPE(HD6475368, hd6475368_device, "hd6475368", "Hitachi HD6475368 (H8/536)")
h8534_device::h8534_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor map)
: h8500_device(mconfig, type, tag, owner, clock, 20, 8, 11, map)
: h8500_device(mconfig, type, tag, owner, clock, 20, 8, 11, 4, map)
{
}
@ -22,6 +24,11 @@ h8534_device::h8534_device(const machine_config &mconfig, device_type type, cons
{
}
hd6435348_device::hd6435348_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: h8534_device(mconfig, HD6435348, tag, owner, clock)
{
}
hd6475348_device::hd6475348_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: h8534_device(mconfig, HD6475348, tag, owner, clock)
{
@ -37,16 +44,24 @@ hd6435368_device::hd6435368_device(const machine_config &mconfig, const char *ta
{
}
hd6475368_device::hd6475368_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: h8536_device(mconfig, HD6475368, tag, owner, clock)
{
}
void h8534_device::internal_map(address_map &map)
{
map(0x0000, 0x7fff).rom().region(DEVICE_SELF, 0); // modes 2, 4, 7
if (mode_control() == 2 || mode_control() == 4 || mode_control() == 7)
map(0x0000, 0x7fff).rom().region(DEVICE_SELF, 0);
register_field_map(map);
}
void h8536_device::internal_map(address_map &map)
{
//map(0x0000, 0xee7f).rom().region(DEVICE_SELF, 0); // mode 2?
//map(0x0000, 0xf67f).rom().region(DEVICE_SELF, 0); // modes 4, 7
if (mode_control() == 2)
map(0x0000, 0xee7f).rom().region(DEVICE_SELF, 0);
else if (mode_control() == 4 || mode_control() == 7)
map(0x0000, 0xf67f).rom().region(DEVICE_SELF, 0);
register_field_map(map);
}

19
src/devices/cpu/h8500/h8534.h
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@ -11,9 +11,8 @@
class h8534_device : public h8500_device
{
protected:
// delegating constructor
// delegating constructors
h8534_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
h8534_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor map);
void register_field_map(address_map &map);
@ -22,6 +21,13 @@ private:
void internal_map(address_map &map);
};
class hd6435348_device : public h8534_device
{
public:
// device type constructor
hd6435348_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
};
class hd6475348_device : public h8534_device
{
public:
@ -45,7 +51,16 @@ public:
hd6435368_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
};
class hd6475368_device : public h8536_device
{
public:
// device type constructor
hd6475368_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
};
DECLARE_DEVICE_TYPE(HD6435348, hd6435348_device)
DECLARE_DEVICE_TYPE(HD6475348, hd6475348_device)
DECLARE_DEVICE_TYPE(HD6435368, hd6435368_device)
DECLARE_DEVICE_TYPE(HD6475368, hd6475368_device)
#endif // MAME_CPU_H8500_H8534_H

3
src/mame/drivers/betacam.cpp
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@ -98,7 +98,8 @@ void betacam_state::betacam(machine_config &config)
m_systemcpu->set_addrmap(AS_PROGRAM, &betacam_state::system_mem_map);
m_systemcpu->p2_in_cb().set_ioport("DSW1");
HD6475348(config, m_servocpu, 20_MHz_XTAL); //Actual chip is marked "H8/534 6435348F 10"
HD6435348(config, m_servocpu, 20_MHz_XTAL); //Actual chip is marked "H8/534 6435348F 10"
m_servocpu->set_mode(3);
m_servocpu->set_addrmap(AS_PROGRAM, &betacam_state::servo_mem_map);
//CXD1095(config, "cxdio0");

2
src/mame/drivers/bvm.cpp
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@ -51,7 +51,6 @@ private:
void bvm_state::mem_map(address_map &map)
{
// internal ROM not used here?
map(0x00000, 0x0f67f).rw("flash", FUNC(intelfsh8_device::read), FUNC(intelfsh8_device::write));
map(0x10000, 0x17fff).ram().share("nvram");
map(0x18000, 0x18007).rw("cxdio0", FUNC(cxd1095_device::read), FUNC(cxd1095_device::write));
@ -66,6 +65,7 @@ INPUT_PORTS_END
void bvm_state::bvm(machine_config &config)
{
HD6435368(config, m_maincpu, 20_MHz_XTAL);
m_maincpu->set_mode(3); // internal ROM not used here?
m_maincpu->set_addrmap(AS_PROGRAM, &bvm_state::mem_map);
CAT28F020(config, "flash");