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https://github.com/holub/mame
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dsp56k: Remove the not required direct update handler [O. Galibert]
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5293b3d468
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@ -108,7 +108,7 @@ const device_type DSP56156 = &device_creator<dsp56k_device>;
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* Internal Memory Maps
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****************************************************************************/
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static ADDRESS_MAP_START( dsp56156_program_map, AS_PROGRAM, 16, dsp56k_device )
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AM_RANGE(0x0000,0x07ff) AM_READWRITE(program_r, program_w) /* 1-5 */
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AM_RANGE(0x0000,0x07ff) AM_RAM AM_SHARE("dsk56k_program_ram") /* 1-5 */
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// AM_RANGE(0x2f00,0x2fff) AM_ROM /* 1-5 PROM reserved memory. Is this the right spot for it? */
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ADDRESS_MAP_END
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@ -122,25 +122,10 @@ dsp56k_device::dsp56k_device(const machine_config &mconfig, const char *tag, dev
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: cpu_device(mconfig, DSP56156, "DSP56156", tag, owner, clock, "dsp56156", __FILE__)
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, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(dsp56156_program_map))
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, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(dsp56156_x_data_map))
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, m_program_ram(*this, "dsk56k_program_ram")
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{
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}
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/***************************************************************************
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Direct Update Handler
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***************************************************************************/
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DIRECT_UPDATE_MEMBER( dsp56k_device::dsp56k_direct_handler )
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{
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if (address <= (0x07ff<<1))
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{
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direct.explicit_configure(0x0000<<1, 0x07ff<<1, (0x07ff<<1) | 1, m_dsp56k_core.program_ram);
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return ~0;
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}
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return address;
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}
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/***************************************************************************
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MEMORY ACCESSORS
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***************************************************************************/
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@ -255,6 +240,7 @@ void dsp56k_device::device_start()
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memset(&m_dsp56k_core, 0, sizeof(m_dsp56k_core));
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m_dsp56k_core.device = this;
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m_dsp56k_core.program_ram = m_program_ram;
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/* Call specific module inits */
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pcu_init(&m_dsp56k_core, this);
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@ -292,16 +278,11 @@ void dsp56k_device::device_start()
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save_item(NAME(m_dsp56k_core.HI.bootstrap_offset));
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save_item(NAME(m_dsp56k_core.peripheral_ram));
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save_item(NAME(m_dsp56k_core.program_ram));
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m_dsp56k_core.program = &space(AS_PROGRAM);
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m_dsp56k_core.direct = &m_dsp56k_core.program->direct();
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m_dsp56k_core.data = &space(AS_DATA);
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/* Setup the direct memory handler for this CPU */
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/* NOTE: Be sure to grab this guy and call him if you ever install another direct_update_hander in a driver! */
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m_dsp56k_core.program->set_direct_update_handler(direct_update_delegate(FUNC(dsp56k_device::dsp56k_direct_handler), this));
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state_add(DSP56K_PC, "PC", m_dsp56k_core.PCU.pc).formatstr("%04X");
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state_add(DSP56K_SR, "SR", m_dsp56k_core.PCU.sr).formatstr("%04X");
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state_add(DSP56K_LC, "LC", m_dsp56k_core.PCU.lc).formatstr("%04X");
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@ -195,7 +195,7 @@ struct dsp56k_core
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address_space *data;
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UINT16 peripheral_ram[0x40];
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UINT16 program_ram[0x800];
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UINT16 *program_ram;
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};
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@ -204,7 +204,6 @@ class dsp56k_device : public cpu_device
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public:
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dsp56k_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
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DECLARE_DIRECT_UPDATE_MEMBER(dsp56k_direct_handler);
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DECLARE_READ16_MEMBER( program_r );
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DECLARE_WRITE16_MEMBER( program_w );
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DECLARE_READ16_MEMBER( peripheral_register_r );
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@ -244,6 +243,7 @@ protected:
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private:
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address_space_config m_program_config;
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address_space_config m_data_config;
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required_shared_ptr<UINT16> m_program_ram;
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dsp56k_core m_dsp56k_core;
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@ -488,16 +488,6 @@ void dsp56k_io_reset(dsp56k_core* cpustate)
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} // namespace DSP56K
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READ16_MEMBER( dsp56k_device::program_r )
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{
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return m_dsp56k_core.program_ram[offset];
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}
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WRITE16_MEMBER( dsp56k_device::program_w )
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{
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m_dsp56k_core.program_ram[offset] = data;
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}
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/* Work */
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READ16_MEMBER( dsp56k_device::peripheral_register_r )
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{
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@ -314,30 +314,6 @@ READ16_MEMBER(polygonet_state::dsp56k_bootload_r)
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return 0x7fff;
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}
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DIRECT_UPDATE_MEMBER(polygonet_state::plygonet_dsp56k_direct_handler)
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{
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/* Call the dsp's update handler first */
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if (!m_dsp56k_update_handler.isnull())
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{
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if (m_dsp56k_update_handler(direct, address) == ~0)
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return ~0;
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}
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/* If the requested region wasn't in there, see if it needs to be caught driver-side */
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if (address >= (0x7000<<1) && address <= (0x7fff<<1))
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{
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direct.explicit_configure(0x7000<<1, 0x7fff<<1, (0xfff<<1) | 1, m_dsp56k_p_mirror);
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return ~0;
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}
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else if (address >= (0x8000<<1) && address <= (0x87ff<<1))
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{
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direct.explicit_configure(0x8000<<1, 0x87ff<<1, (0x7ff<<1) | 1, m_dsp56k_p_8000);
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return ~0;
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}
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return address;
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}
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/* The dsp56k's Port C Data register (0xffe3) :
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Program code (function 4e) configures it as general purpose output I/O pins (ffc1 = 0000 & ffc3 = 0fff).
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@ -756,10 +732,6 @@ DRIVER_INIT_MEMBER(polygonet_state,polygonet)
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memset(m_dsp56k_bank02_ram, 0, sizeof(m_dsp56k_bank02_ram));
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memset(m_dsp56k_shared_ram_16, 0, sizeof(m_dsp56k_shared_ram_16));
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memset(m_dsp56k_bank04_ram, 0, sizeof(m_dsp56k_bank04_ram));
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/* The dsp56k occasionally executes out of mapped memory */
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address_space &space = machine().device<dsp56k_device>("dsp")->space(AS_PROGRAM);
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m_dsp56k_update_handler = space.set_direct_update_handler(direct_update_delegate(FUNC(polygonet_state::plygonet_dsp56k_direct_handler), this));
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}
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@ -48,8 +48,6 @@ public:
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UINT8 m_sys0;
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UINT8 m_sys1;
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direct_update_delegate m_dsp56k_update_handler;
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/* TTL text plane stuff */
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int m_ttl_gfx_index;
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tilemap_t *m_ttl_tilemap;
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@ -95,7 +93,6 @@ public:
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DECLARE_WRITE32_MEMBER(polygonet_ttl_ram_w);
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DECLARE_READ32_MEMBER(polygonet_roz_ram_r);
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DECLARE_WRITE32_MEMBER(polygonet_roz_ram_w);
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DIRECT_UPDATE_MEMBER(plygonet_dsp56k_direct_handler);
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DECLARE_DRIVER_INIT(polygonet);
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TILE_GET_INFO_MEMBER(ttl_get_tile_info);
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TILE_GET_INFO_MEMBER(roz_get_tile_info);
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