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https://github.com/holub/mame
synced 2025-04-26 18:23:08 +03:00
Added video emulation
This commit is contained in:
Angelo Salese
parent
1cf5de7016
commit
d42b8d7529
@ -71,7 +71,7 @@ public:
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required_shared_ptr<UINT8> m_video_ram;
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UINT8 *m_ram_base;
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UINT8 *m_rom_base;
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UINT8 *m_char_rom;
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UINT8 *m_char_ram;
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UINT16 m_pcg_addr;
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UINT16 m_pcg_internal_addr;
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UINT8 m_key_mux;
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@ -117,7 +117,7 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
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for( yi = 0; yi < lr; yi++)
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{
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tile_data = state->m_char_rom[(tile*8+yi) & 0x7ff];
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tile_data = state->m_char_ram[(tile*8+yi) & 0x7ff];
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if(cursor_on && cursor_addr == addr+x && device->machine().primary_screen->frame_number() & 0x10)
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tile_data^=0xff;
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@ -163,7 +163,7 @@ WRITE8_MEMBER( a5105_state::pcg_addr_w )
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WRITE8_MEMBER( a5105_state::pcg_val_w )
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{
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m_char_rom[m_pcg_addr | m_pcg_internal_addr] = data;
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m_char_ram[m_pcg_addr | m_pcg_internal_addr] = data;
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machine().gfx[0]->mark_dirty(m_pcg_addr >> 3);
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@ -528,7 +528,7 @@ void a5105_state::palette_init()
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void a5105_state::video_start()
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{
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// find memory regions
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m_char_rom = memregion("pcg")->base();
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m_char_ram = memregion("pcg")->base();
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}
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static UPD7220_INTERFACE( hgdc_intf )
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@ -1,6 +1,8 @@
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/***************************************************************************
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Template for skeleton drivers
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MZ-3500 (c) 198? Sharp
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preliminary driver by Angelo Salese
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***************************************************************************/
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@ -8,6 +10,7 @@ Template for skeleton drivers
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#include "emu.h"
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#include "cpu/z80/z80.h"
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//#include "sound/ay8910.h"
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#include "video/upd7220.h"
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#define MAIN_CLOCK XTAL_8MHz
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@ -17,18 +20,26 @@ public:
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mz3500_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_master(*this, "master"),
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m_slave(*this, "slave")
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m_slave(*this, "slave"),
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m_hgdc1(*this, "upd7220_chr"),
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m_hgdc2(*this, "upd7220_gfx"),
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m_video_ram(*this, "video_ram")
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{ }
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// devices
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required_device<cpu_device> m_master;
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required_device<cpu_device> m_slave;
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required_device<upd7220_device> m_hgdc1;
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required_device<upd7220_device> m_hgdc2;
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required_shared_ptr<UINT8> m_video_ram;
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UINT8 *m_ipl_rom;
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UINT8 *m_basic_rom;
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UINT8 *m_work_ram;
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UINT8 *m_shared_ram;
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UINT8 *m_char_rom;
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UINT8 m_ma,m_mo,m_ms,m_me2,m_me1;
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UINT8 m_crtc[0x10];
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DECLARE_READ8_MEMBER(mz3500_master_mem_r);
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DECLARE_WRITE8_MEMBER(mz3500_master_mem_w);
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@ -40,9 +51,10 @@ public:
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DECLARE_WRITE8_MEMBER(mz3500_shared_ram_w);
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DECLARE_READ8_MEMBER(mz3500_io_r);
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DECLARE_WRITE8_MEMBER(mz3500_io_w);
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DECLARE_WRITE8_MEMBER(mz3500_crtc_w);
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// screen updates
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UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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protected:
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// driver_device overrides
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@ -57,11 +69,138 @@ void mz3500_state::video_start()
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{
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}
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UINT32 mz3500_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
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/*
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CRTC regs
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[0]
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---- -x-- "Choice of whether attribute or cursor be put on the frame that displayed on CRT2" (whatever that means ...)
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---- --x- CRT2 output
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---- ---x CRT1 output
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[1]
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---- -GRB CRT1 color output
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[2]
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---- -GRB CRT2 color output
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[3]
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---- -GRB background color output
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[4]
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---- --x- border color mode in effect
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---- ---x color mode
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[5]
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---- --x- width setting (0: 40 chars, 1: 80 chars)
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---- ---x data size for graphics RAM (0: 8 bits, 1: 16 bits)
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[6]
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---- -x-- "Connection of graphic GDC"
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---- --x- "Connection of the 96K bytes VRAM"
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---- ---x "Connection of a 400 raster CRT"
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[7]
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---- ---x 0: 25 lines, 1: 20 lines display
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[d]
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(mirror of [5]?)
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*/
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static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
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{
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// ...
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}
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static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
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{
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mz3500_state *state = device->machine().driver_data<mz3500_state>();
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const rgb_t *palette = palette_entry_list_raw(bitmap.palette());
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int x;
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int xi,yi;
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int tile;
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int attr;
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UINT8 tile_data;
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UINT8 width80;
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UINT8 char_size;
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UINT8 hires;
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// popmessage("%02x",state->m_crtc[6]);
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width80 = (state->m_crtc[5] & 2) >> 1;
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hires = (state->m_crtc[6] & 1);
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char_size = (hires) ? 16 : 8;
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for( x = 0; x < pitch; x++ )
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{
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tile = (state->m_video_ram[((addr+x)*2) & 0x1fff] & 0xff);
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attr = (state->m_video_ram[((addr+x)*2+1) & 0x3ffff] & 0x0f);
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//if(hires)
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// tile <<= 1;
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for( yi = 0; yi < lr; yi++)
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{
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tile_data = state->m_char_rom[((tile*16+yi) & 0xfff) | (hires*0x1000)];
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for( xi = 0; xi < 8; xi++)
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{
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int res_x,res_y;
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int pen;
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/* TODO: color attribute needs double check */
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if(yi >= char_size)
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pen = -1;
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else
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{
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if(state->m_crtc[4] & 1)
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pen = (tile_data >> (7-xi)) & 1 ? (attr >> 1) : -1;
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else
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pen = (tile_data >> (7-xi)) & 1 ? 7 : -1;
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}
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res_x = x * 8 + xi;
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res_y = y * lr + yi;
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if(pen != -1)
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{
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if(!width80)
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{
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bitmap.pix32(res_y, res_x*2+0) = palette[pen];
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bitmap.pix32(res_y, res_x*2+1) = palette[pen];
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}
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else
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bitmap.pix32(res_y, res_x) = palette[pen];
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}
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}
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}
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}
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}
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UINT32 mz3500_state::screen_update( screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect )
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{
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bitmap.fill(machine().pens[(m_crtc[4] & 2) ? m_crtc[3] & 7 : 0], cliprect);
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/* graphics */
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m_hgdc2->screen_update(screen, bitmap, cliprect);
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m_hgdc1->screen_update(screen, bitmap, cliprect);
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return 0;
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}
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static UPD7220_INTERFACE( hgdc_1_intf )
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{
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"screen",
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NULL,
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hgdc_draw_text,
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DEVCB_NULL,
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DEVCB_DEVICE_LINE_MEMBER("upd7220_gfx", upd7220_device, ext_sync_w),
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DEVCB_NULL
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};
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static UPD7220_INTERFACE( hgdc_2_intf )
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{
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"screen",
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hgdc_display_pixels,
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NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL
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};
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READ8_MEMBER(mz3500_state::mz3500_ipl_r)
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{
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return m_ipl_rom[offset];
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@ -262,6 +401,19 @@ WRITE8_MEMBER(mz3500_state::mz3500_io_w)
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}
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}
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WRITE8_MEMBER(mz3500_state::mz3500_crtc_w)
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{
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if(offset & 8)
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{
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if(offset == 0xd)
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m_crtc[offset & 7] = data;
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else
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printf("CRTC register access %02x\n",offset); // probably just a mirror, but who knows ...
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}
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else
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m_crtc[offset] = data;
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}
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static ADDRESS_MAP_START( mz3500_master_map, AS_PROGRAM, 8, mz3500_state )
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AM_RANGE(0x0000, 0xffff) AM_READWRITE(mz3500_master_mem_r,mz3500_master_mem_w)
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ADDRESS_MAP_END
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@ -273,6 +425,7 @@ static ADDRESS_MAP_START( mz3500_master_io, AS_IO, 8, mz3500_state )
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// AM_RANGE(0xec, 0xef) irq signal from slave to master CPU
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// AM_RANGE(0xf4, 0xf7) MFD upd765
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// AM_RANGE(0xf8, 0xfb) MFD I/O port
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AM_RANGE(0xf8, 0xf8) AM_READNOP // TODO
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AM_RANGE(0xfc, 0xff) AM_READWRITE(mz3500_io_r,mz3500_io_w) // memory mapper
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ADDRESS_MAP_END
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@ -289,9 +442,9 @@ static ADDRESS_MAP_START( mz3500_slave_io, AS_IO, 8, mz3500_state )
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// AM_RANGE(0x20, 0x2f) pit8253
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// AM_RANGE(0x30, 0x3f) i8255
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// AM_RANGE(0x40, 0x4f) 8-bit input port
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// AM_RANGE(0x50, 0x5f) CRTC
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// AM_RANGE(0x60, 0x6f) upd7220 gfx
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// AM_RANGE(0x70, 0x7f) upd7220 chr
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AM_RANGE(0x50, 0x5f) AM_RAM_WRITE(mz3500_crtc_w)
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AM_RANGE(0x60, 0x61) AM_DEVREADWRITE("upd7220_gfx", upd7220_device, read, write)
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AM_RANGE(0x70, 0x71) AM_DEVREADWRITE("upd7220_chr", upd7220_device, read, write)
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ADDRESS_MAP_END
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static INPUT_PORTS_START( mz3500 )
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@ -350,19 +503,33 @@ static INPUT_PORTS_START( mz3500 )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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INPUT_PORTS_END
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static const gfx_layout charlayout =
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static const gfx_layout charlayout_8x8 =
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{
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8,8,
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RGN_FRAC(1,1),
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0x100,
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1,
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{ RGN_FRAC(0,1) },
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{ 0, 1, 2, 3, 4, 5, 6, 7 },
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{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
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8*8
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8*16
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};
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static const gfx_layout charlayout_8x16 =
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{
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8,16,
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0x100,
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1,
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{ RGN_FRAC(0,1) },
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{ 0, 1, 2, 3, 4, 5, 6, 7 },
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{ STEP16(0,8) },
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8*16
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};
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static GFXDECODE_START( mz3500 )
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GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 )
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GFXDECODE_ENTRY( "gfx1", 0x0000, charlayout_8x8, 0, 1 )
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GFXDECODE_ENTRY( "gfx1", 0x0008, charlayout_8x8, 0, 1 )
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GFXDECODE_ENTRY( "gfx1", 0x1000, charlayout_8x16, 0, 1 )
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GFXDECODE_END
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@ -370,6 +537,7 @@ void mz3500_state::machine_start()
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{
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m_ipl_rom = memregion("ipl")->base();
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m_basic_rom = memregion("basic")->base();
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m_char_rom = memregion("gfx1")->base();
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m_work_ram = auto_alloc_array_clear(machine(), UINT8, 0x40000);
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m_shared_ram = auto_alloc_array_clear(machine(), UINT8, 0x800);
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}
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@ -382,14 +550,29 @@ void mz3500_state::machine_reset()
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m_mo = 0;
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m_me1 = 0;
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m_me2 = 0;
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m_slave->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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//m_slave->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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}
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void mz3500_state::palette_init()
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{
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int i;
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for(i=0;i<8;i++)
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palette_set_color_rgb(machine(), i,pal1bit((i >> 1) & 1),pal1bit(i >> 2),pal1bit((i >> 0) & 1));
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}
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static ADDRESS_MAP_START( upd7220_1_map, AS_0, 8, mz3500_state )
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ADDRESS_MAP_GLOBAL_MASK(0x1fff)
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AM_RANGE(0x00000, 0x1fff) AM_RAM AM_SHARE("video_ram")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( upd7220_2_map, AS_0, 8, mz3500_state )
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AM_RANGE(0x00000, 0x3ffff) AM_RAM // AM_SHARE("video_ram_2")
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ADDRESS_MAP_END
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/* TODO: clocks */
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static MACHINE_CONFIG_START( mz3500, mz3500_state )
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/* basic machine hardware */
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@ -401,6 +584,9 @@ static MACHINE_CONFIG_START( mz3500, mz3500_state )
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MCFG_CPU_PROGRAM_MAP(mz3500_slave_map)
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MCFG_CPU_IO_MAP(mz3500_slave_io)
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MCFG_UPD7220_ADD("upd7220_chr", MAIN_CLOCK/5, hgdc_1_intf, upd7220_1_map)
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MCFG_UPD7220_ADD("upd7220_gfx", MAIN_CLOCK/5, hgdc_2_intf, upd7220_2_map)
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/* video hardware */
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_REFRESH_RATE(60)
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