From d455c6267e4d1a00fd4d9e429ed19e86738c871e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Banaan=20Ananas?= Date: Sun, 29 Jul 2012 23:44:37 +0000 Subject: [PATCH] that trick doesn't work with ADD (SUB is left-to-right, ADD is equal both ways) --- src/emu/cpu/tms32031/32031ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/emu/cpu/tms32031/32031ops.c b/src/emu/cpu/tms32031/32031ops.c index 917ae407519..67ff2d240ce 100644 --- a/src/emu/cpu/tms32031/32031ops.c +++ b/src/emu/cpu/tms32031/32031ops.c @@ -83,7 +83,7 @@ #define OR_V_SUB(a,b,r) do { UINT32 temp = ((((a) ^ (b)) & ((a) ^ (r))) >> 30) & VFLAG; IREG(TMR_ST) |= temp | (temp << 4); } while (0) #define OR_V_ADD(a,b,r) do { UINT32 temp = ((~((a) ^ (b)) & ((a) ^ (r))) >> 30) & VFLAG; IREG(TMR_ST) |= temp | (temp << 4); } while (0) #define OR_C_SUB(a,b,r) do { IREG(TMR_ST) |= ((UINT32)(b) > (UINT32)(a)); } while (0) -#define OR_C_ADD(a,b,r) do { IREG(TMR_ST) |= ((UINT32)(~(a)) < (UINT32)(b)); } while (0) +#define OR_C_ADD(a,b,r) do { IREG(TMR_ST) |= ((UINT32)(a) > (UINT32)(r)); } while (0) #define OR_NZCV_SUB(a,b,r) do { OR_V_SUB(a,b,r); OR_C_SUB(a,b,r); OR_NZ(r); } while (0) #define OR_NZCV_ADD(a,b,r) do { OR_V_ADD(a,b,r); OR_C_ADD(a,b,r); OR_NZ(r); } while (0)