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cubeqcpu.cpp : Updates

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Simplify handlers, Use correct/shorter type values, Fix spacings
This commit is contained in:
cam900 2019-05-03 15:09:13 +09:00
parent 9a57fb3d79
commit d45da88a8d
3 changed files with 296 additions and 296 deletions
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396
src/devices/cpu/cubeqcpu/cubeqcpu.cpp
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@ -76,7 +76,7 @@ DEFINE_DEVICE_TYPE(CQUESTROT, cquestrot_cpu_device, "cquestrot", "Cube Quest Rot
DEFINE_DEVICE_TYPE(CQUESTLIN, cquestlin_cpu_device, "cquestlin", "Cube Quest Line CPU") DEFINE_DEVICE_TYPE(CQUESTLIN, cquestlin_cpu_device, "cquestlin", "Cube Quest Line CPU")
cquestsnd_cpu_device::cquestsnd_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) cquestsnd_cpu_device::cquestsnd_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: cpu_device(mconfig, CQUESTSND, tag, owner, clock) : cpu_device(mconfig, CQUESTSND, tag, owner, clock)
, m_program_config("program", ENDIANNESS_BIG, 64, 8, -3) , m_program_config("program", ENDIANNESS_BIG, 64, 8, -3)
, m_dac_w(*this) , m_dac_w(*this)
@ -98,7 +98,7 @@ std::unique_ptr<util::disasm_interface> cquestsnd_cpu_device::create_disassemble
} }
cquestrot_cpu_device::cquestrot_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) cquestrot_cpu_device::cquestrot_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: cpu_device(mconfig, CQUESTROT, tag, owner, clock) : cpu_device(mconfig, CQUESTROT, tag, owner, clock)
, m_program_config("program", ENDIANNESS_BIG, 64, 9, -3) , m_program_config("program", ENDIANNESS_BIG, 64, 9, -3)
, m_linedata_w(*this) , m_linedata_w(*this)
@ -106,7 +106,7 @@ cquestrot_cpu_device::cquestrot_cpu_device(const machine_config &mconfig, const
} }
READ16_MEMBER( cquestrot_cpu_device::linedata_r ) u16 cquestrot_cpu_device::linedata_r()
{ {
return m_linedata; return m_linedata;
} }
@ -118,7 +118,7 @@ std::unique_ptr<util::disasm_interface> cquestrot_cpu_device::create_disassemble
} }
cquestlin_cpu_device::cquestlin_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) cquestlin_cpu_device::cquestlin_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: cpu_device(mconfig, CQUESTLIN, tag, owner, clock) : cpu_device(mconfig, CQUESTLIN, tag, owner, clock)
, m_program_config("program", ENDIANNESS_BIG, 64, 8, -3) , m_program_config("program", ENDIANNESS_BIG, 64, 8, -3)
, m_linedata_r(*this) , m_linedata_r(*this)
@ -140,7 +140,7 @@ std::unique_ptr<util::disasm_interface> cquestlin_cpu_device::create_disassemble
} }
WRITE16_MEMBER( cquestlin_cpu_device::linedata_w ) void cquestlin_cpu_device::linedata_w(offs_t offset, u16 data)
{ {
m_sram[offset] = data; m_sram[offset] = data;
} }
@ -150,23 +150,23 @@ WRITE16_MEMBER( cquestlin_cpu_device::linedata_w )
MEMORY ACCESSORS FOR 68000 MEMORY ACCESSORS FOR 68000
***************************************************************************/ ***************************************************************************/
WRITE16_MEMBER( cquestsnd_cpu_device::sndram_w ) void cquestsnd_cpu_device::sndram_w(offs_t offset, u16 data, u16 mem_mask)
{ {
COMBINE_DATA(&m_sram[offset]); COMBINE_DATA(&m_sram[offset]);
} }
READ16_MEMBER( cquestsnd_cpu_device::sndram_r ) u16 cquestsnd_cpu_device::sndram_r(offs_t offset)
{ {
return m_sram[offset]; return m_sram[offset];
} }
WRITE16_MEMBER( cquestrot_cpu_device::rotram_w ) void cquestrot_cpu_device::rotram_w(offs_t offset, u16 data, u16 mem_mask)
{ {
COMBINE_DATA(&m_dram[offset]); COMBINE_DATA(&m_dram[offset]);
} }
READ16_MEMBER( cquestrot_cpu_device::rotram_r ) u16 cquestrot_cpu_device::rotram_r(offs_t offset)
{ {
return m_dram[offset]; return m_dram[offset];
} }
@ -180,7 +180,7 @@ void cquestsnd_cpu_device::device_start()
{ {
m_dac_w.resolve_safe(); m_dac_w.resolve_safe();
assert(m_sound_region_tag != nullptr); assert(m_sound_region_tag != nullptr);
m_sound_data = (uint16_t*)machine().root_device().memregion(m_sound_region_tag)->base(); m_sound_data = (u16*)machine().root_device().memregion(m_sound_region_tag)->base();
m_program = &space(AS_PROGRAM); m_program = &space(AS_PROGRAM);
m_cache = m_program->cache<3, -3, ENDIANNESS_BIG>(); m_cache = m_program->cache<3, -3, ENDIANNESS_BIG>();
@ -218,27 +218,27 @@ void cquestsnd_cpu_device::device_start()
save_item(NAME(m_prev_ipram)); save_item(NAME(m_prev_ipram));
save_item(NAME(m_prev_ipwrt)); save_item(NAME(m_prev_ipwrt));
state_add( CQUESTSND_PC, "PC", m_pc).formatstr("%02X"); state_add(CQUESTSND_PC, "PC", m_pc).formatstr("%02X");
state_add( CQUESTSND_Q, "Q", m_q).formatstr("%04X"); state_add(CQUESTSND_Q, "Q", m_q).formatstr("%04X");
state_add( CQUESTSND_RTNLATCH, "RTN", m_rtnlatch).formatstr("%02X"); state_add(CQUESTSND_RTNLATCH, "RTN", m_rtnlatch).formatstr("%02X");
state_add( CQUESTSND_ADRCNTR, "CNT", m_adrcntr).formatstr("%02X"); state_add(CQUESTSND_ADRCNTR, "CNT", m_adrcntr).formatstr("%02X");
state_add( CQUESTSND_DINLATCH, "DINX", m_dinlatch).formatstr("%04X"); state_add(CQUESTSND_DINLATCH, "DINX", m_dinlatch).formatstr("%04X");
state_add( CQUESTSND_RAM0, "RAM[0]", m_ram[0x0]).formatstr("%04X"); state_add(CQUESTSND_RAM0, "RAM[0]", m_ram[0x0]).formatstr("%04X");
state_add( CQUESTSND_RAM1, "RAM[1]", m_ram[0x1]).formatstr("%04X"); state_add(CQUESTSND_RAM1, "RAM[1]", m_ram[0x1]).formatstr("%04X");
state_add( CQUESTSND_RAM2, "RAM[2]", m_ram[0x2]).formatstr("%04X"); state_add(CQUESTSND_RAM2, "RAM[2]", m_ram[0x2]).formatstr("%04X");
state_add( CQUESTSND_RAM3, "RAM[3]", m_ram[0x3]).formatstr("%04X"); state_add(CQUESTSND_RAM3, "RAM[3]", m_ram[0x3]).formatstr("%04X");
state_add( CQUESTSND_RAM4, "RAM[4]", m_ram[0x4]).formatstr("%04X"); state_add(CQUESTSND_RAM4, "RAM[4]", m_ram[0x4]).formatstr("%04X");
state_add( CQUESTSND_RAM5, "RAM[5]", m_ram[0x5]).formatstr("%04X"); state_add(CQUESTSND_RAM5, "RAM[5]", m_ram[0x5]).formatstr("%04X");
state_add( CQUESTSND_RAM6, "RAM[6]", m_ram[0x6]).formatstr("%04X"); state_add(CQUESTSND_RAM6, "RAM[6]", m_ram[0x6]).formatstr("%04X");
state_add( CQUESTSND_RAM7, "RAM[7]", m_ram[0x7]).formatstr("%04X"); state_add(CQUESTSND_RAM7, "RAM[7]", m_ram[0x7]).formatstr("%04X");
state_add( CQUESTSND_RAM8, "RAM[8]", m_ram[0x8]).formatstr("%04X"); state_add(CQUESTSND_RAM8, "RAM[8]", m_ram[0x8]).formatstr("%04X");
state_add( CQUESTSND_RAM9, "RAM[9]", m_ram[0x9]).formatstr("%04X"); state_add(CQUESTSND_RAM9, "RAM[9]", m_ram[0x9]).formatstr("%04X");
state_add( CQUESTSND_RAMA, "RAM[A]", m_ram[0xa]).formatstr("%04X"); state_add(CQUESTSND_RAMA, "RAM[A]", m_ram[0xa]).formatstr("%04X");
state_add( CQUESTSND_RAMB, "RAM[B]", m_ram[0xb]).formatstr("%04X"); state_add(CQUESTSND_RAMB, "RAM[B]", m_ram[0xb]).formatstr("%04X");
state_add( CQUESTSND_RAMC, "RAM[C]", m_ram[0xc]).formatstr("%04X"); state_add(CQUESTSND_RAMC, "RAM[C]", m_ram[0xc]).formatstr("%04X");
state_add( CQUESTSND_RAMD, "RAM[D]", m_ram[0xd]).formatstr("%04X"); state_add(CQUESTSND_RAMD, "RAM[D]", m_ram[0xd]).formatstr("%04X");
state_add( CQUESTSND_RAME, "RAM[E]", m_ram[0xe]).formatstr("%04X"); state_add(CQUESTSND_RAME, "RAM[E]", m_ram[0xe]).formatstr("%04X");
state_add( CQUESTSND_RAMF, "RAM[F]", m_ram[0xf]).formatstr("%04X"); state_add(CQUESTSND_RAMF, "RAM[F]", m_ram[0xf]).formatstr("%04X");
state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%02X").noshow(); state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%02X").noshow();
state_add(STATE_GENPCBASE, "CURPC", m_pc).formatstr("%02X").noshow(); state_add(STATE_GENPCBASE, "CURPC", m_pc).formatstr("%02X").noshow();
@ -314,34 +314,34 @@ void cquestrot_cpu_device::device_start()
save_pointer(NAME(m_dram), 16384); save_pointer(NAME(m_dram), 16384);
save_pointer(NAME(m_sram), 2048); save_pointer(NAME(m_sram), 2048);
state_add( CQUESTROT_PC, "PC", m_pc).formatstr("%02X"); state_add(CQUESTROT_PC, "PC", m_pc).formatstr("%02X");
state_add( CQUESTROT_Q, "Q", m_q).formatstr("%04X"); state_add(CQUESTROT_Q, "Q", m_q).formatstr("%04X");
state_add( CQUESTROT_RAM0, "RAM[0]", m_ram[0x0]).formatstr("%04X"); state_add(CQUESTROT_RAM0, "RAM[0]", m_ram[0x0]).formatstr("%04X");
state_add( CQUESTROT_RAM1, "RAM[1]", m_ram[0x1]).formatstr("%04X"); state_add(CQUESTROT_RAM1, "RAM[1]", m_ram[0x1]).formatstr("%04X");
state_add( CQUESTROT_RAM2, "RAM[2]", m_ram[0x2]).formatstr("%04X"); state_add(CQUESTROT_RAM2, "RAM[2]", m_ram[0x2]).formatstr("%04X");
state_add( CQUESTROT_RAM3, "RAM[3]", m_ram[0x3]).formatstr("%04X"); state_add(CQUESTROT_RAM3, "RAM[3]", m_ram[0x3]).formatstr("%04X");
state_add( CQUESTROT_RAM4, "RAM[4]", m_ram[0x4]).formatstr("%04X"); state_add(CQUESTROT_RAM4, "RAM[4]", m_ram[0x4]).formatstr("%04X");
state_add( CQUESTROT_RAM5, "RAM[5]", m_ram[0x5]).formatstr("%04X"); state_add(CQUESTROT_RAM5, "RAM[5]", m_ram[0x5]).formatstr("%04X");
state_add( CQUESTROT_RAM6, "RAM[6]", m_ram[0x6]).formatstr("%04X"); state_add(CQUESTROT_RAM6, "RAM[6]", m_ram[0x6]).formatstr("%04X");
state_add( CQUESTROT_RAM7, "RAM[7]", m_ram[0x7]).formatstr("%04X"); state_add(CQUESTROT_RAM7, "RAM[7]", m_ram[0x7]).formatstr("%04X");
state_add( CQUESTROT_RAM8, "RAM[8]", m_ram[0x8]).formatstr("%04X"); state_add(CQUESTROT_RAM8, "RAM[8]", m_ram[0x8]).formatstr("%04X");
state_add( CQUESTROT_RAM9, "RAM[9]", m_ram[0x9]).formatstr("%04X"); state_add(CQUESTROT_RAM9, "RAM[9]", m_ram[0x9]).formatstr("%04X");
state_add( CQUESTROT_RAMA, "RAM[A]", m_ram[0xa]).formatstr("%04X"); state_add(CQUESTROT_RAMA, "RAM[A]", m_ram[0xa]).formatstr("%04X");
state_add( CQUESTROT_RAMB, "RAM[B]", m_ram[0xb]).formatstr("%04X"); state_add(CQUESTROT_RAMB, "RAM[B]", m_ram[0xb]).formatstr("%04X");
state_add( CQUESTROT_RAMC, "RAM[C]", m_ram[0xc]).formatstr("%04X"); state_add(CQUESTROT_RAMC, "RAM[C]", m_ram[0xc]).formatstr("%04X");
state_add( CQUESTROT_RAMD, "RAM[D]", m_ram[0xd]).formatstr("%04X"); state_add(CQUESTROT_RAMD, "RAM[D]", m_ram[0xd]).formatstr("%04X");
state_add( CQUESTROT_RAME, "RAM[E]", m_ram[0xe]).formatstr("%04X"); state_add(CQUESTROT_RAME, "RAM[E]", m_ram[0xe]).formatstr("%04X");
state_add( CQUESTROT_RAMF, "RAM[F]", m_ram[0xf]).formatstr("%04X"); state_add(CQUESTROT_RAMF, "RAM[F]", m_ram[0xf]).formatstr("%04X");
state_add( CQUESTROT_SEQCNT, "SEQCNT", m_seqcnt).formatstr("%01X"); state_add(CQUESTROT_SEQCNT, "SEQCNT", m_seqcnt).formatstr("%01X");
state_add( CQUESTROT_DYNADDR, "DYNADDR", m_dynaddr).formatstr("%04X"); state_add(CQUESTROT_DYNADDR, "DYNADDR", m_dynaddr).formatstr("%04X");
state_add( CQUESTROT_DYNDATA, "DYNDATA", m_dyndata).formatstr("%04X"); state_add(CQUESTROT_DYNDATA, "DYNDATA", m_dyndata).formatstr("%04X");
state_add( CQUESTROT_YRLATCH, "YRLATCH", m_yrlatch).formatstr("%04X"); state_add(CQUESTROT_YRLATCH, "YRLATCH", m_yrlatch).formatstr("%04X");
state_add( CQUESTROT_YDLATCH, "YDLATCH", m_ydlatch).formatstr("%04X"); state_add(CQUESTROT_YDLATCH, "YDLATCH", m_ydlatch).formatstr("%04X");
state_add( CQUESTROT_DINLATCH, "DINLATCH", m_dinlatch).formatstr("%04X"); state_add(CQUESTROT_DINLATCH, "DINLATCH", m_dinlatch).formatstr("%04X");
state_add( CQUESTROT_DSRCLATCH, "DSRCLATCH", m_dsrclatch).formatstr("%04X"); state_add(CQUESTROT_DSRCLATCH, "DSRCLATCH", m_dsrclatch).formatstr("%04X");
state_add( CQUESTROT_RSRCLATCH, "RSRCLATCH", m_rsrclatch).formatstr("%04X"); state_add(CQUESTROT_RSRCLATCH, "RSRCLATCH", m_rsrclatch).formatstr("%04X");
state_add( CQUESTROT_LDADDR, "LDADDR", m_lineaddr).formatstr("%04X"); state_add(CQUESTROT_LDADDR, "LDADDR", m_lineaddr).formatstr("%04X");
state_add( CQUESTROT_LDDATA, "LDDATA", m_linedata).formatstr("%04X"); state_add(CQUESTROT_LDDATA, "LDDATA", m_linedata).formatstr("%04X");
state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%02X").noshow(); state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%02X").noshow();
state_add(STATE_GENPCBASE, "CURPC", m_pc).formatstr("%02X").noshow(); state_add(STATE_GENPCBASE, "CURPC", m_pc).formatstr("%02X").noshow();
@ -448,33 +448,33 @@ void cquestlin_cpu_device::device_start()
save_pointer(NAME(m_e_stack), 32768); save_pointer(NAME(m_e_stack), 32768);
save_pointer(NAME(m_o_stack), 32768); save_pointer(NAME(m_o_stack), 32768);
state_add( CQUESTLIN_FGPC, "FPC", m_pc[FOREGROUND]).formatstr("%02X"); state_add(CQUESTLIN_FGPC, "FPC", m_pc[FOREGROUND]).formatstr("%02X");
state_add( CQUESTLIN_BGPC, "BPC", m_pc[BACKGROUND]).formatstr("%02X"); state_add(CQUESTLIN_BGPC, "BPC", m_pc[BACKGROUND]).formatstr("%02X");
state_add( CQUESTLIN_Q, "Q", m_q).formatstr("%04X"); state_add(CQUESTLIN_Q, "Q", m_q).formatstr("%04X");
state_add( CQUESTLIN_RAM0, "RAM[0]", m_ram[0x0]).formatstr("%04X"); state_add(CQUESTLIN_RAM0, "RAM[0]", m_ram[0x0]).formatstr("%04X");
state_add( CQUESTLIN_RAM1, "RAM[1]", m_ram[0x1]).formatstr("%04X"); state_add(CQUESTLIN_RAM1, "RAM[1]", m_ram[0x1]).formatstr("%04X");
state_add( CQUESTLIN_RAM2, "RAM[2]", m_ram[0x2]).formatstr("%04X"); state_add(CQUESTLIN_RAM2, "RAM[2]", m_ram[0x2]).formatstr("%04X");
state_add( CQUESTLIN_RAM3, "RAM[3]", m_ram[0x3]).formatstr("%04X"); state_add(CQUESTLIN_RAM3, "RAM[3]", m_ram[0x3]).formatstr("%04X");
state_add( CQUESTLIN_RAM4, "RAM[4]", m_ram[0x4]).formatstr("%04X"); state_add(CQUESTLIN_RAM4, "RAM[4]", m_ram[0x4]).formatstr("%04X");
state_add( CQUESTLIN_RAM5, "RAM[5]", m_ram[0x5]).formatstr("%04X"); state_add(CQUESTLIN_RAM5, "RAM[5]", m_ram[0x5]).formatstr("%04X");
state_add( CQUESTLIN_RAM6, "RAM[6]", m_ram[0x6]).formatstr("%04X"); state_add(CQUESTLIN_RAM6, "RAM[6]", m_ram[0x6]).formatstr("%04X");
state_add( CQUESTLIN_RAM7, "RAM[7]", m_ram[0x7]).formatstr("%04X"); state_add(CQUESTLIN_RAM7, "RAM[7]", m_ram[0x7]).formatstr("%04X");
state_add( CQUESTLIN_RAM8, "RAM[8]", m_ram[0x8]).formatstr("%04X"); state_add(CQUESTLIN_RAM8, "RAM[8]", m_ram[0x8]).formatstr("%04X");
state_add( CQUESTLIN_RAM9, "RAM[9]", m_ram[0x9]).formatstr("%04X"); state_add(CQUESTLIN_RAM9, "RAM[9]", m_ram[0x9]).formatstr("%04X");
state_add( CQUESTLIN_RAMA, "RAM[A]", m_ram[0xa]).formatstr("%04X"); state_add(CQUESTLIN_RAMA, "RAM[A]", m_ram[0xa]).formatstr("%04X");
state_add( CQUESTLIN_RAMB, "RAM[B]", m_ram[0xb]).formatstr("%04X"); state_add(CQUESTLIN_RAMB, "RAM[B]", m_ram[0xb]).formatstr("%04X");
state_add( CQUESTLIN_RAMC, "RAM[C]", m_ram[0xc]).formatstr("%04X"); state_add(CQUESTLIN_RAMC, "RAM[C]", m_ram[0xc]).formatstr("%04X");
state_add( CQUESTLIN_RAMD, "RAM[D]", m_ram[0xd]).formatstr("%04X"); state_add(CQUESTLIN_RAMD, "RAM[D]", m_ram[0xd]).formatstr("%04X");
state_add( CQUESTLIN_RAME, "RAM[E]", m_ram[0xe]).formatstr("%04X"); state_add(CQUESTLIN_RAME, "RAM[E]", m_ram[0xe]).formatstr("%04X");
state_add( CQUESTLIN_RAMF, "RAM[F]", m_ram[0xf]).formatstr("%04X"); state_add(CQUESTLIN_RAMF, "RAM[F]", m_ram[0xf]).formatstr("%04X");
state_add( CQUESTLIN_FADLATCH, "FADDR", m_fadlatch).formatstr("%04X"); state_add(CQUESTLIN_FADLATCH, "FADDR", m_fadlatch).formatstr("%04X");
state_add( CQUESTLIN_BADLATCH, "BADDR", m_badlatch).formatstr("%04X"); state_add(CQUESTLIN_BADLATCH, "BADDR", m_badlatch).formatstr("%04X");
state_add( CQUESTLIN_SREG, "SREG", m_sreg).formatstr("%04X"); state_add(CQUESTLIN_SREG, "SREG", m_sreg).formatstr("%04X");
state_add( CQUESTLIN_XCNT, "XCNT", m_xcnt).formatstr("%03X"); state_add(CQUESTLIN_XCNT, "XCNT", m_xcnt).formatstr("%03X");
state_add( CQUESTLIN_YCNT, "YCNT", m_ycnt).formatstr("%03X"); state_add(CQUESTLIN_YCNT, "YCNT", m_ycnt).formatstr("%03X");
state_add( CQUESTLIN_CLATCH, "CLATCH", m_clatch).formatstr("%04X"); state_add(CQUESTLIN_CLATCH, "CLATCH", m_clatch).formatstr("%04X");
state_add( CQUESTLIN_ZLATCH, "ZLATCH", m_zlatch).formatstr("%04X"); state_add(CQUESTLIN_ZLATCH, "ZLATCH", m_zlatch).formatstr("%04X");
state_add(STATE_GENPC, "GENPC", m_curpc).formatstr("%02X").noshow(); state_add(STATE_GENPC, "GENPC", m_curpc).formatstr("%02X").noshow();
state_add(STATE_GENPCBASE, "CURPC", m_curpc).formatstr("%02X").noshow(); state_add(STATE_GENPCBASE, "CURPC", m_curpc).formatstr("%02X").noshow();
@ -501,7 +501,7 @@ void cquestlin_cpu_device::state_string_export(const device_state_entry &entry,
m_cflag ? 'C' : '.', m_cflag ? 'C' : '.',
m_vflag ? 'V' : '.', m_vflag ? 'V' : '.',
m_f ? '.' : 'Z', m_f ? '.' : 'Z',
( m_clkcnt & 3 ) ? 'B' : 'F'); (m_clkcnt & 3) ? 'B' : 'F');
break; break;
} }
} }
@ -521,19 +521,19 @@ enum snd_latch_type
ADLATCH = 2 ADLATCH = 2
}; };
int cquestsnd_cpu_device::do_sndjmp(int jmp) bool cquestsnd_cpu_device::do_sndjmp(u8 jmp)
{ {
switch (jmp) switch (jmp)
{ {
/* JUMP */ case 0: return 1; /* JUMP */ case 0: return true;
/* MSB */ case 2: return m_f & 0x8000 ? 0 : 1; /* MSB */ case 2: return m_f & 0x8000 ? false : true;
/* !MSB */ case 3: return m_f & 0x8000 ? 1 : 0; /* !MSB */ case 3: return m_f & 0x8000 ? true : false;
/* ZERO */ case 5: return m_f == 0 ? 0 : 1; /* ZERO */ case 5: return m_f == 0 ? false : true;
/* OVR */ case 6: return m_vflag ? 0 : 1; /* OVR */ case 6: return m_vflag ? false : true;
/* LOOP */ case 7: return m_adrcntr & 0x80 ? 0: 1; /* LOOP */ case 7: return m_adrcntr & 0x80 ? false: true;
} }
return 0; return false;
} }
void cquestsnd_cpu_device::execute_run() void cquestsnd_cpu_device::execute_run()
@ -542,26 +542,26 @@ void cquestsnd_cpu_device::execute_run()
do do
{ {
/* Decode the instruction */ /* Decode the instruction */
uint64_t inst = m_cache->read_qword(SND_PC); u64 inst = m_cache->read_qword(SND_PC);
uint32_t inslow = inst & 0xffffffff; u32 inslow = inst & 0xffffffff;
uint32_t inshig = inst >> 32; u32 inshig = inst >> 32;
int t = (inshig >> 24) & 0xff; u8 t = (inshig >> 24) & 0xff;
int b = (inshig >> 20) & 0xf; const u8 b = (inshig >> 20) & 0xf;
int a = (inshig >> 16) & 0xf; const u8 a = (inshig >> 16) & 0xf;
int ci = (inshig >> 15) & 1; const u8 ci = (inshig >> 15) & 1;
int i5_3 = (inshig >> 12) & 7; const u8 i5_3 = (inshig >> 12) & 7;
int _ramen = (inshig >> 11) & 1; const bool _ramen = (inshig >> 11) & 1;
int i2_0 = (inshig >> 8) & 7; const u8 i2_0 = (inshig >> 8) & 7;
int rtnltch = (inshig >> 7) & 1; const bool rtnltch = (inshig >> 7) & 1;
int jmp = (inshig >> 4) & 7; const u8 jmp = (inshig >> 4) & 7;
int inca = (inshig >> 3) & 1; const bool inca = (inshig >> 3) & 1;
int i8_6 = (inshig >> 0) & 7; const u8 i8_6 = (inshig >> 0) & 7;
int _ipram = (inslow >> 31) & 1; const bool _ipram = (inslow >> 31) & 1;
int _ipwrt = (inslow >> 30) & 1; const bool _ipwrt = (inslow >> 30) & 1;
int latch = (inslow >> 28) & 3; const u8 latch = (inslow >> 28) & 3;
int rtn = (inslow >> 27) & 1; const bool rtn = (inslow >> 27) & 1;
int _rin = (inslow >> 26) & 1; const bool _rin = (inslow >> 26) & 1;
debugger_instruction_hook(m_pc); debugger_instruction_hook(m_pc);
@ -571,12 +571,12 @@ void cquestsnd_cpu_device::execute_run()
/* Handle the AM2901 ALU instruction */ /* Handle the AM2901 ALU instruction */
{ {
uint16_t r = 0; u16 r = 0;
uint16_t s = 0; u16 s = 0;
uint32_t res = 0; u32 res = 0;
uint32_t cflag = 0; u32 cflag = 0;
uint32_t vflag = 0; u32 vflag = 0;
/* Determine the ALU sources */ /* Determine the ALU sources */
switch (i2_0) switch (i2_0)
@ -649,7 +649,7 @@ void cquestsnd_cpu_device::execute_run()
break; break;
case RAMQD: case RAMQD:
{ {
uint16_t qin; u16 qin;
m_ram[b] = (_rin ? 0 : 0x8000) | (m_f >> 1); m_ram[b] = (_rin ? 0 : 0x8000) | (m_f >> 1);
m_q >>= 1; m_q >>= 1;
@ -680,7 +680,7 @@ void cquestsnd_cpu_device::execute_run()
/* Now handle any SRAM accesses from the previous cycle */ /* Now handle any SRAM accesses from the previous cycle */
if (!m_prev_ipram) if (!m_prev_ipram)
{ {
uint16_t addr = m_adrlatch | (m_adrcntr & 0x7f); u16 addr = m_adrlatch | (m_adrcntr & 0x7f);
if (!m_prev_ipwrt) if (!m_prev_ipwrt)
m_sram[addr] = m_ramwlatch; m_sram[addr] = m_ramwlatch;
@ -707,7 +707,7 @@ void cquestsnd_cpu_device::execute_run()
} }
/* Check for jump/return */ /* Check for jump/return */
if ( do_sndjmp(jmp) ) if (do_sndjmp(jmp))
m_pc = rtn ? m_rtnlatch : t; m_pc = rtn ? m_rtnlatch : t;
else else
m_pc++; m_pc++;
@ -769,7 +769,7 @@ enum rot_yout
/* The Dynamic RAM latch clocks in a value at the end of this cycle */ /* The Dynamic RAM latch clocks in a value at the end of this cycle */
/* So CPU waits for sync before reading from DRAM */ /* So CPU waits for sync before reading from DRAM */
int cquestrot_cpu_device::do_rotjmp(int jmp) int cquestrot_cpu_device::do_rotjmp(u8 jmp)
{ {
int ret = 0; int ret = 0;
@ -798,28 +798,28 @@ void cquestrot_cpu_device::execute_run()
do do
{ {
/* Decode the instruction */ /* Decode the instruction */
uint64_t inst = m_cache->read_qword(ROT_PC); u64 inst = m_cache->read_qword(ROT_PC);
uint32_t inslow = inst & 0xffffffff; u32 inslow = inst & 0xffffffff;
uint32_t inshig = inst >> 32; u32 inshig = inst >> 32;
int t = (inshig >> 20) & 0xfff; u16 t = (inshig >> 20) & 0xfff;
int jmp = (inshig >> 16) & 0xf; const u8 jmp = (inshig >> 16) & 0xf;
int spf = (inshig >> 12) & 0xf; const u8 spf = (inshig >> 12) & 0xf;
int rsrc = (inshig >> 11) & 0x1; const bool rsrc = (inshig >> 11) & 0x1;
int yout = (inshig >> 8) & 0x7; const u8 yout = (inshig >> 8) & 0x7;
int sel = (inshig >> 6) & 0x3; const u8 sel = (inshig >> 6) & 0x3;
int dsrc = (inshig >> 4) & 0x3; const u8 dsrc = (inshig >> 4) & 0x3;
int b = (inshig >> 0) & 0xf; const u8 b = (inshig >> 0) & 0xf;
int a = (inslow >> 28) & 0xf; const u8 a = (inslow >> 28) & 0xf;
int i8_6 = (inslow >> 24) & 0x7; const u8 i8_6 = (inslow >> 24) & 0x7;
int ci = (inslow >> 23) & 0x1; u8 ci = (inslow >> 23) & 0x1;
int i5_3 = (inslow >> 20) & 0x7; u8 i5_3 = (inslow >> 20) & 0x7;
int _sex = (inslow >> 19) & 0x1; const bool _sex = (inslow >> 19) & 0x1;
int i2_0 = (inslow >> 16) & 0x7; u8 i2_0 = (inslow >> 16) & 0x7;
int dsrclatch; int dsrclatch;
uint16_t data_in = 0xffff; u16 data_in = 0xffff;
debugger_instruction_hook(ROT_PC); debugger_instruction_hook(ROT_PC);
@ -871,12 +871,12 @@ void cquestrot_cpu_device::execute_run()
/* No do the ALU operation */ /* No do the ALU operation */
{ {
uint16_t r = 0; u16 r = 0;
uint16_t s = 0; u16 s = 0;
uint32_t res = 0; u32 res = 0;
uint32_t cflag = 0; u32 cflag = 0;
uint32_t vflag = 0; u32 vflag = 0;
/* First, determine correct I1 bit */ /* First, determine correct I1 bit */
if ((spf == SPF_MULT) && !_BIT(m_q, 0)) if ((spf == SPF_MULT) && !_BIT(m_q, 0))
@ -960,10 +960,10 @@ void cquestrot_cpu_device::execute_run()
break; break;
case RAMQD: case RAMQD:
{ {
uint16_t q0 = m_q & 1; u16 q0 = m_q & 1;
uint16_t r0 = m_f & 1; u16 r0 = m_f & 1;
uint16_t q15 = 0; u16 q15 = 0;
uint16_t r15 = 0; u16 r15 = 0;
/* Determine Q15 and RAM15 */ /* Determine Q15 and RAM15 */
switch (sel) switch (sel)
@ -987,8 +987,8 @@ void cquestrot_cpu_device::execute_run()
} }
case RAMD: case RAMD:
{ {
uint16_t r0 = m_f & 1; u16 r0 = m_f & 1;
uint16_t r15 = 0; u16 r15 = 0;
switch (sel) switch (sel)
{ {
@ -1006,10 +1006,10 @@ void cquestrot_cpu_device::execute_run()
} }
case RAMQU: case RAMQU:
{ {
uint16_t q15 = BIT(m_q, 15); u16 q15 = BIT(m_q, 15);
uint16_t r15 = BIT(m_f, 15); u16 r15 = BIT(m_f, 15);
uint16_t q0 = 0; u16 q0 = 0;
uint16_t r0 = 0; u16 r0 = 0;
switch (sel) switch (sel)
{ {
@ -1031,9 +1031,9 @@ void cquestrot_cpu_device::execute_run()
} }
case RAMU: case RAMU:
{ {
uint16_t q15 = BIT(m_q, 15); u16 q15 = BIT(m_q, 15);
uint16_t r15 = BIT(m_f, 15); u16 r15 = BIT(m_f, 15);
uint16_t r0 = 0; u16 r0 = 0;
switch (sel) switch (sel)
{ {
@ -1051,7 +1051,7 @@ void cquestrot_cpu_device::execute_run()
} }
/* Check for jump */ /* Check for jump */
if ( do_rotjmp(jmp) ) if (do_rotjmp(jmp))
m_pc = t; m_pc = t;
else else
m_pc = (m_pc + 1) & 0xfff; m_pc = (m_pc + 1) & 0xfff;
@ -1059,7 +1059,7 @@ void cquestrot_cpu_device::execute_run()
/* Rising edge; update the sequence counter */ /* Rising edge; update the sequence counter */
if (spf == SPF_SQLTCH) if (spf == SPF_SQLTCH)
m_seqcnt = t & 0xf; m_seqcnt = t & 0xf;
else if ( (spf == SPF_MULT) || (spf == SPF_DIV) ) else if ((spf == SPF_MULT) || (spf == SPF_DIV))
m_seqcnt = (m_seqcnt + 1) & 0xf; m_seqcnt = (m_seqcnt + 1) & 0xf;
/* Rising edge; write data source reg */ /* Rising edge; write data source reg */
@ -1085,7 +1085,7 @@ void cquestrot_cpu_device::execute_run()
case YOUT_Y2LDD: case YOUT_Y2LDD:
{ {
m_linedata = ((t & 0xf) << 12) | (m_y & 0xfff); m_linedata = ((t & 0xf) << 12) | (m_y & 0xfff);
m_linedata_w( m_lineaddr, m_linedata, 0xffff ); m_linedata_w(m_lineaddr, m_linedata);
break; break;
} }
case YOUT_Y2DAD: m_dynaddr = m_y & 0x3fff; break; case YOUT_Y2DAD: m_dynaddr = m_y & 0x3fff; break;
@ -1147,7 +1147,7 @@ enum sreg_bits
SREG_LDX = 7 SREG_LDX = 7
}; };
int cquestlin_cpu_device::do_linjmp(int jmp) int cquestlin_cpu_device::do_linjmp(u8 jmp)
{ {
int ret = 0; int ret = 0;
@ -1177,13 +1177,13 @@ void cquestlin_cpu_device::cubeqcpu_clear_stack()
} }
uint8_t cquestlin_cpu_device::cubeqcpu_get_ptr_ram_val(int i) u8 cquestlin_cpu_device::cubeqcpu_get_ptr_ram_val(int i)
{ {
return m_ptr_ram[((m_field^1) * 256) + i]; return m_ptr_ram[((m_field^1) * 256) + i];
} }
uint32_t* cquestlin_cpu_device::cubeqcpu_get_stack_ram() u32* cquestlin_cpu_device::cubeqcpu_get_stack_ram()
{ {
if (m_field != ODD_FIELD) if (m_field != ODD_FIELD)
return m_o_stack; return m_o_stack;
@ -1196,8 +1196,8 @@ void cquestlin_cpu_device::execute_run()
{ {
#define LINE_PC ((m_pc[prog] & 0x7f) | ((prog == BACKGROUND) ? 0x80 : 0)) #define LINE_PC ((m_pc[prog] & 0x7f) | ((prog == BACKGROUND) ? 0x80 : 0))
uint32_t *stack_ram; u32 *stack_ram;
uint8_t *ptr_ram; u8 *ptr_ram;
/* Check the field and set the stack/pointer RAM pointers appropriately */ /* Check the field and set the stack/pointer RAM pointers appropriately */
if (m_field == ODD_FIELD) if (m_field == ODD_FIELD)
@ -1218,25 +1218,25 @@ void cquestlin_cpu_device::execute_run()
int prog = (m_clkcnt & 3) ? BACKGROUND : FOREGROUND; int prog = (m_clkcnt & 3) ? BACKGROUND : FOREGROUND;
m_curpc = LINE_PC; m_curpc = LINE_PC;
uint64_t inst = m_cache->read_qword(LINE_PC); u64 inst = m_cache->read_qword(LINE_PC);
uint32_t inslow = inst & 0xffffffff; u32 inslow = inst & 0xffffffff;
uint32_t inshig = inst >> 32; u32 inshig = inst >> 32;
int t = (inshig >> 24) & 0xff; u8 t = (inshig >> 24) & 0xff;
int jmp = (inshig >> 20) & 0xf; const u8 jmp = (inshig >> 20) & 0xf;
int latch = (inshig >> 16) & 0x7; const u8 latch = (inshig >> 16) & 0x7;
int op = (inshig >> 15) & 0x1; const bool op = (inshig >> 15) & 0x1;
int spf = (inshig >> 12) & 0x7; const u8 spf = (inshig >> 12) & 0x7;
int b = (inshig >> 8) & 0xf; const u8 b = (inshig >> 8) & 0xf;
int a = (inshig >> 4) & 0xf; u8 a = (inshig >> 4) & 0xf;
int i8_6 = (inshig >> 0) & 0x7; const u8 i8_6 = (inshig >> 0) & 0x7;
int ci = (inslow >> 31) & 0x1; const u8 ci = (inslow >> 31) & 0x1;
int i5_3 = (inslow >> 28) & 0x7; const u8 i5_3 = (inslow >> 28) & 0x7;
int _pbcs = (inslow >> 27) & 0x1; const u8 _pbcs = (inslow >> 27) & 0x1;
int i2_0 = (inslow >> 24) & 0x7; u8 i2_0 = (inslow >> 24) & 0x7;
uint16_t data_in = 0; u16 data_in = 0;
debugger_instruction_hook(m_pc[prog]); debugger_instruction_hook(m_pc[prog]);
@ -1264,16 +1264,16 @@ void cquestlin_cpu_device::execute_run()
if (_BIT(m_fglatch, 4) && (m_ycnt < 256)) if (_BIT(m_fglatch, 4) && (m_ycnt < 256))
{ {
/* 20-bit words */ /* 20-bit words */
uint32_t data; u32 data;
uint16_t h = m_xcnt; u16 h = m_xcnt;
uint8_t v = m_ycnt & 0xff; u8 v = m_ycnt & 0xff;
/* Clamp H between 0 and 319 */ /* Clamp H between 0 and 319 */
if (h >= 320) if (h >= 320)
h = (h & 0x800) ? 0 : 319; h = (h & 0x800) ? 0 : 319;
/* Stack word type depends on STOP/#START bit */ /* Stack word type depends on STOP/#START bit */
if ( _BIT(m_fglatch, 3) ) if (_BIT(m_fglatch, 3))
data = (0 << 19) | (h << 8) | m_zlatch; data = (0 << 19) | (h << 8) | m_zlatch;
else else
data = (1 << 19) | ((m_clatch & 0x100) << 9) | (h << 8) | (m_clatch & 0xff); data = (1 << 19) | ((m_clatch & 0x100) << 9) | (h << 8) | (m_clatch & 0xff);
@ -1299,12 +1299,12 @@ void cquestlin_cpu_device::execute_run()
/* Now do the ALU operation */ /* Now do the ALU operation */
{ {
uint16_t r = 0; u16 r = 0;
uint16_t s = 0; u16 s = 0;
uint16_t res = 0; u16 res = 0;
uint32_t cflag = 0; u32 cflag = 0;
uint32_t vflag = 0; u32 vflag = 0;
/* Determine the ALU sources */ /* Determine the ALU sources */
switch (i2_0) switch (i2_0)
@ -1381,8 +1381,8 @@ void cquestlin_cpu_device::execute_run()
break; break;
case RAMQD: case RAMQD:
{ {
uint16_t r11 = (BIT(m_f, 11) ^ m_vflag) ? 0x800 : 0; u16 r11 = (BIT(m_f, 11) ^ m_vflag) ? 0x800 : 0;
uint16_t q11 = (prog == BACKGROUND) ? 0x800 : 0; u16 q11 = (prog == BACKGROUND) ? 0x800 : 0;
m_ram[b] = r11 | (m_f >> 1); m_ram[b] = r11 | (m_f >> 1);
m_q = q11 | (m_q >> 1); m_q = q11 | (m_q >> 1);
@ -1391,7 +1391,7 @@ void cquestlin_cpu_device::execute_run()
} }
case RAMD: case RAMD:
{ {
uint16_t r11 = (BIT(m_f, 11) ^ m_vflag) ? 0x800 : 0; u16 r11 = (BIT(m_f, 11) ^ m_vflag) ? 0x800 : 0;
m_ram[b] = r11 | (m_f >> 1); m_ram[b] = r11 | (m_f >> 1);
m_y = m_f; m_y = m_f;
@ -1400,7 +1400,7 @@ void cquestlin_cpu_device::execute_run()
case RAMQU: case RAMQU:
{ {
/* Determine shift inputs */ /* Determine shift inputs */
uint16_t r0 = (prog == BACKGROUND); u16 r0 = (prog == BACKGROUND);
/* This should never happen - Q0 will be invalid */ /* This should never happen - Q0 will be invalid */
m_ram[b] = (m_f << 1) | r0; m_ram[b] = (m_f << 1) | r0;
@ -1410,7 +1410,7 @@ void cquestlin_cpu_device::execute_run()
} }
case RAMU: case RAMU:
{ {
uint16_t r0 = (prog == BACKGROUND); u16 r0 = (prog == BACKGROUND);
m_ram[b] = (m_f << 1) | r0; m_ram[b] = (m_f << 1) | r0;
m_y = m_f; m_y = m_f;
@ -1420,7 +1420,7 @@ void cquestlin_cpu_device::execute_run()
} }
/* Adjust program counter */ /* Adjust program counter */
if ( do_linjmp(jmp) ) if (do_linjmp(jmp))
m_pc[prog] = t & 0x7f; m_pc[prog] = t & 0x7f;
else else
m_pc[prog] = (m_pc[prog] + 1) & 0x7f; m_pc[prog] = (m_pc[prog] + 1) & 0x7f;
@ -1481,7 +1481,7 @@ void cquestlin_cpu_device::execute_run()
m_badlatch = m_y & 0xfff; m_badlatch = m_y & 0xfff;
/* What about the SRAM dlatch? */ /* What about the SRAM dlatch? */
if ( !_BIT(m_bglatch, 5) ) if (!_BIT(m_bglatch, 5))
m_sramdlatch = ((t & 0xf) << 12) | (m_y & 0x0fff); m_sramdlatch = ((t & 0xf) << 12) | (m_y & 0x0fff);
/* BG and FG latches */ /* BG and FG latches */

188
src/devices/cpu/cubeqcpu/cubeqcpu.h
View File

@ -20,14 +20,14 @@ class cquestsnd_cpu_device : public cpu_device
{ {
public: public:
// construction/destruction // construction/destruction
cquestsnd_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); cquestsnd_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
// configuration helpers // configuration helpers
auto dac_w() { return m_dac_w.bind(); } auto dac_w() { return m_dac_w.bind(); }
void set_sound_region(const char *tag) { m_sound_region_tag = tag; } void set_sound_region(const char *tag) { m_sound_region_tag = tag; }
DECLARE_WRITE16_MEMBER(sndram_w); void sndram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
DECLARE_READ16_MEMBER(sndram_r); u16 sndram_r(offs_t offset);
protected: protected:
enum enum
@ -60,9 +60,9 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
// device_execute_interface overrides // device_execute_interface overrides
virtual uint32_t execute_min_cycles() const override { return 1; } virtual u32 execute_min_cycles() const override { return 1; }
virtual uint32_t execute_max_cycles() const override { return 1; } virtual u32 execute_max_cycles() const override { return 1; }
virtual uint32_t execute_input_lines() const override { return 0; } virtual u32 execute_input_lines() const override { return 0; }
virtual void execute_run() override; virtual void execute_run() override;
// device_memory_interface overrides // device_memory_interface overrides
@ -75,35 +75,35 @@ private:
address_space_config m_program_config; address_space_config m_program_config;
/* AM2901 internals */ /* AM2901 internals */
uint16_t m_ram[16]; u16 m_ram[16];
uint16_t m_q; u16 m_q;
uint16_t m_f; u16 m_f;
uint16_t m_y; u16 m_y;
uint32_t m_cflag; u32 m_cflag;
uint32_t m_vflag; u32 m_vflag;
uint8_t m_pc; /* 2 x LS161 @ 6E, 6F */ u8 m_pc; /* 2 x LS161 @ 6E, 6F */
uint16_t m_platch; u16 m_platch;
uint8_t m_rtnlatch; /* LS374 @ 5F */ u8 m_rtnlatch; /* LS374 @ 5F */
uint8_t m_adrcntr; /* 2 x LS161 */ u8 m_adrcntr; /* 2 x LS161 */
uint16_t m_adrlatch; u16 m_adrlatch;
uint16_t m_dinlatch; u16 m_dinlatch;
uint16_t m_ramwlatch; u16 m_ramwlatch;
uint16_t m_sram[4096/2]; u16 m_sram[4096/2];
int m_prev_ipram; bool m_prev_ipram;
int m_prev_ipwrt; bool m_prev_ipwrt;
devcb_write16 m_dac_w; devcb_write16 m_dac_w;
const char *m_sound_region_tag; const char *m_sound_region_tag;
uint16_t *m_sound_data; u16 *m_sound_data;
address_space *m_program; address_space *m_program;
memory_access_cache<3, -3, ENDIANNESS_BIG> *m_cache; memory_access_cache<3, -3, ENDIANNESS_BIG> *m_cache;
int m_icount; int m_icount;
int do_sndjmp(int jmp); bool do_sndjmp(u8 jmp);
}; };
@ -111,14 +111,14 @@ class cquestrot_cpu_device : public cpu_device
{ {
public: public:
// construction/destruction // construction/destruction
cquestrot_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); cquestrot_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
// configuration helpers // configuration helpers
auto linedata_w() { return m_linedata_w.bind(); } auto linedata_w() { return m_linedata_w.bind(); }
DECLARE_READ16_MEMBER(linedata_r); u16 linedata_r();
DECLARE_WRITE16_MEMBER(rotram_w); void rotram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
DECLARE_READ16_MEMBER(rotram_r); u16 rotram_r(offs_t offset);
protected: protected:
enum enum
@ -158,9 +158,9 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
// device_execute_interface overrides // device_execute_interface overrides
virtual uint32_t execute_min_cycles() const override { return 1; } virtual u32 execute_min_cycles() const override { return 1; }
virtual uint32_t execute_max_cycles() const override { return 1; } virtual u32 execute_max_cycles() const override { return 1; }
virtual uint32_t execute_input_lines() const override { return 0; } virtual u32 execute_input_lines() const override { return 0; }
virtual void execute_run() override; virtual void execute_run() override;
// device_memory_interface overrides // device_memory_interface overrides
@ -177,45 +177,45 @@ private:
devcb_write16 m_linedata_w; devcb_write16 m_linedata_w;
/* AM2901 internals */ /* AM2901 internals */
uint16_t m_ram[16]; u16 m_ram[16];
uint16_t m_q; u16 m_q;
uint16_t m_f; u16 m_f;
uint16_t m_y; u16 m_y;
uint32_t m_cflag; u32 m_cflag;
uint32_t m_vflag; u32 m_vflag;
uint16_t m_pc; /* 12-bit, but only 9 used */ u16 m_pc; /* 12-bit, but only 9 used */
uint8_t m_seqcnt; /* 4-bit counter */ u8 m_seqcnt; /* 4-bit counter */
uint8_t m_dsrclatch; u8 m_dsrclatch;
uint8_t m_rsrclatch; u8 m_rsrclatch;
uint16_t m_dynaddr; /* LS374 at 2D, 8D */ u16 m_dynaddr; /* LS374 at 2D, 8D */
uint16_t m_dyndata; /* LS374 at 10B, 9B */ u16 m_dyndata; /* LS374 at 10B, 9B */
uint16_t m_yrlatch; /* LS374 at 9D, 10D */ u16 m_yrlatch; /* LS374 at 9D, 10D */
uint16_t m_ydlatch; /* LS374 at 9C, 10C */ u16 m_ydlatch; /* LS374 at 9C, 10C */
uint16_t m_dinlatch; u16 m_dinlatch;
uint8_t m_divreg; /* LS74 at ? */ u8 m_divreg; /* LS74 at ? */
uint16_t m_linedata; u16 m_linedata;
uint16_t m_lineaddr; u16 m_lineaddr;
uint16_t m_dram[16384]; /* Shared with 68000 */ u16 m_dram[16384]; /* Shared with 68000 */
uint16_t m_sram[2048]; /* Private */ u16 m_sram[2048]; /* Private */
uint8_t m_prev_dred; u8 m_prev_dred;
uint8_t m_prev_dwrt; u8 m_prev_dwrt;
uint8_t m_wc; u8 m_wc;
uint8_t m_rc; u8 m_rc;
uint8_t m_clkcnt; u8 m_clkcnt;
address_space *m_program; address_space *m_program;
memory_access_cache<3, -3, ENDIANNESS_BIG> *m_cache; memory_access_cache<3, -3, ENDIANNESS_BIG> *m_cache;
int m_icount; int m_icount;
// For the debugger // For the debugger
uint8_t m_flags; u8 m_flags;
int do_rotjmp(int jmp); int do_rotjmp(u8 jmp);
}; };
@ -223,16 +223,16 @@ class cquestlin_cpu_device : public cpu_device
{ {
public: public:
// construction/destruction // construction/destruction
cquestlin_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); cquestlin_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
// configuration helpers // configuration helpers
auto linedata_r() { return m_linedata_r.bind(); } auto linedata_r() { return m_linedata_r.bind(); }
DECLARE_WRITE16_MEMBER( linedata_w ); void linedata_w(offs_t offset, u16 data);
void cubeqcpu_swap_line_banks(); void cubeqcpu_swap_line_banks();
void cubeqcpu_clear_stack(); void cubeqcpu_clear_stack();
uint8_t cubeqcpu_get_ptr_ram_val(int i); u8 cubeqcpu_get_ptr_ram_val(int i);
uint32_t* cubeqcpu_get_stack_ram(); u32* cubeqcpu_get_stack_ram();
protected: protected:
enum enum
@ -270,9 +270,9 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
// device_execute_interface overrides // device_execute_interface overrides
virtual uint32_t execute_min_cycles() const override { return 1; } virtual u32 execute_min_cycles() const override { return 1; }
virtual uint32_t execute_max_cycles() const override { return 1; } virtual u32 execute_max_cycles() const override { return 1; }
virtual uint32_t execute_input_lines() const override { return 0; } virtual u32 execute_input_lines() const override { return 0; }
virtual void execute_run() override; virtual void execute_run() override;
// device_memory_interface overrides // device_memory_interface overrides
@ -289,51 +289,51 @@ private:
devcb_read16 m_linedata_r; devcb_read16 m_linedata_r;
/* 12-bit AM2901 internals */ /* 12-bit AM2901 internals */
uint16_t m_ram[16]; u16 m_ram[16];
uint16_t m_q; u16 m_q;
uint16_t m_f; u16 m_f;
uint16_t m_y; u16 m_y;
uint32_t m_cflag; u32 m_cflag;
uint32_t m_vflag; u32 m_vflag;
uint8_t m_pc[2]; /* Two program counters; one for FG, other for BG */ u8 m_pc[2]; /* Two program counters; one for FG, other for BG */
uint16_t m_seqcnt; /* 12-bit */ u16 m_seqcnt; /* 12-bit */
uint16_t m_clatch; /* LS374 at 9E and 1-bit FF */ u16 m_clatch; /* LS374 at 9E and 1-bit FF */
uint8_t m_zlatch; /* LS374 at 4H */ u8 m_zlatch; /* LS374 at 4H */
uint16_t m_xcnt; u16 m_xcnt;
uint16_t m_ycnt; u16 m_ycnt;
uint8_t m_sreg; u8 m_sreg;
uint16_t m_fadlatch; u16 m_fadlatch;
uint16_t m_badlatch; u16 m_badlatch;
uint16_t m_sramdlatch; u16 m_sramdlatch;
uint8_t m_fglatch; u8 m_fglatch;
uint8_t m_bglatch; u8 m_bglatch;
uint8_t m_gt0reg; u8 m_gt0reg;
uint8_t m_fdxreg; u8 m_fdxreg;
uint32_t m_field; u32 m_field;
uint32_t m_clkcnt; u32 m_clkcnt;
/* RAM */ /* RAM */
uint16_t m_sram[4096]; /* Shared with rotate CPU */ u16 m_sram[4096]; /* Shared with rotate CPU */
uint8_t m_ptr_ram[1024]; /* Pointer RAM */ u8 m_ptr_ram[1024]; /* Pointer RAM */
uint32_t m_e_stack[32768]; /* Stack DRAM: 32kx20 */ u32 m_e_stack[32768]; /* Stack DRAM: 32kx20 */
uint32_t m_o_stack[32768]; /* Stack DRAM: 32kx20 */ u32 m_o_stack[32768]; /* Stack DRAM: 32kx20 */
address_space *m_program; address_space *m_program;
memory_access_cache<3, -3, ENDIANNESS_BIG> *m_cache; memory_access_cache<3, -3, ENDIANNESS_BIG> *m_cache;
int m_icount; int m_icount;
// For the debugger // For the debugger
uint8_t m_flags; u8 m_flags;
uint16_t m_curpc; u16 m_curpc;
int do_linjmp(int jmp); int do_linjmp(u8 jmp);
}; };

8
src/mame/drivers/cubeqst.cpp
View File

@ -412,22 +412,22 @@ INPUT_PORTS_END
READ16_MEMBER(cubeqst_state::read_rotram) READ16_MEMBER(cubeqst_state::read_rotram)
{ {
return m_rotatecpu->rotram_r(space, offset, mem_mask); return m_rotatecpu->rotram_r(offset);
} }
WRITE16_MEMBER(cubeqst_state::write_rotram) WRITE16_MEMBER(cubeqst_state::write_rotram)
{ {
m_rotatecpu->rotram_w(space, offset, data, mem_mask); m_rotatecpu->rotram_w(offset, data, mem_mask);
} }
READ16_MEMBER(cubeqst_state::read_sndram) READ16_MEMBER(cubeqst_state::read_sndram)
{ {
return m_soundcpu->sndram_r(space, offset, mem_mask); return m_soundcpu->sndram_r(offset);
} }
WRITE16_MEMBER(cubeqst_state::write_sndram) WRITE16_MEMBER(cubeqst_state::write_sndram)
{ {
m_soundcpu->sndram_w(space, offset, data, mem_mask); m_soundcpu->sndram_w(offset, data, mem_mask);
} }
void cubeqst_state::m68k_program_map(address_map &map) void cubeqst_state::m68k_program_map(address_map &map)