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some more naomi/dc cleanup (nw)

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This commit is contained in:
Miodrag Milanovic 2013-04-05 09:08:49 +00:00
parent d491c0ddeb
commit d5ccd8d282
9 changed files with 421 additions and 432 deletions
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159
src/mame/drivers/naomi.c
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@ -1396,8 +1396,6 @@ Sushi Bar
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/z80/z80.h"
#include "machine/eeprom.h"
#include "machine/intelfsh.h"
#include "machine/x76f100.h"
#include "machine/maple-dc.h"
#include "machine/dc-ctrl.h"
@ -1408,42 +1406,36 @@ Sushi Bar
#include "machine/naomim2.h"
#include "machine/naomim4.h"
#include "machine/awboard.h"
#include "includes/dc.h"
#include "includes/naomi.h"
#include "cpu/sh4/sh4.h"
#include "cpu/arm7/arm7core.h"
#include "sound/aica.h"
#include "machine/jvsdev.h"
#include "machine/jvs13551.h"
#include "includes/dc.h"
#include "includes/naomi.h"
#define CPU_CLOCK (200000000)
static macronix_29l001mc_device *awflash;
/* MD2 MD1 MD0 MD6 MD4 MD3 MD5 MD7 MD8 */
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK };
static READ64_HANDLER( naomi_arm_r )
READ64_MEMBER(naomi_state::naomi_arm_r )
{
naomi_state *state = space.machine().driver_data<naomi_state>();
return *(reinterpret_cast<UINT64 *>(state->dc_sound_ram.target())+offset);
return *(reinterpret_cast<UINT64 *>(dc_sound_ram.target())+offset);
}
static WRITE64_HANDLER( naomi_arm_w )
WRITE64_MEMBER(naomi_state::naomi_arm_w )
{
naomi_state *state = space.machine().driver_data<naomi_state>();
COMBINE_DATA(reinterpret_cast<UINT64 *>(state->dc_sound_ram.target()) + offset);
COMBINE_DATA(reinterpret_cast<UINT64 *>(dc_sound_ram.target()) + offset);
}
static READ64_HANDLER( naomi_unknown1_r )
READ64_MEMBER(naomi_state::naomi_unknown1_r )
{
if ((offset * 8) == 0xc0) // trick so that it does not "wait for multiboard sync"
return -1;
return 0;
}
static WRITE64_HANDLER( naomi_unknown1_w )
WRITE64_MEMBER(naomi_state::naomi_unknown1_w )
{
}
@ -1452,24 +1444,23 @@ static WRITE64_HANDLER( naomi_unknown1_w )
*/
static READ64_DEVICE_HANDLER( eeprom_93c46a_r )
READ64_MEMBER(naomi_state::eeprom_93c46a_r )
{
int res;
/* bit 3 is EEPROM data */
res = downcast<eeprom_device *>(device)->read_bit() << 4;
res = m_eeprom->read_bit() << 4;
return res;
}
static WRITE64_DEVICE_HANDLER( eeprom_93c46a_w )
WRITE64_MEMBER(naomi_state::eeprom_93c46a_w )
{
/* bit 4 is data */
/* bit 2 is clock */
/* bit 5 is cs */
eeprom_device *eeprom = downcast<eeprom_device *>(device);
eeprom->write_bit(data & 0x8);
eeprom->set_cs_line((data & 0x20) ? CLEAR_LINE : ASSERT_LINE);
eeprom->set_clock_line((data & 0x4) ? ASSERT_LINE : CLEAR_LINE);
m_eeprom->write_bit(data & 0x8);
m_eeprom->set_cs_line((data & 0x20) ? CLEAR_LINE : ASSERT_LINE);
m_eeprom->set_clock_line((data & 0x4) ? ASSERT_LINE : CLEAR_LINE);
}
/* Dreamcast MAP
@ -1522,39 +1513,35 @@ static WRITE64_DEVICE_HANDLER( eeprom_93c46a_w )
* Common address map for Naomi 1, Naomi GD-Rom, Naomi 2, Atomiswave ...
*/
// SB_LMMODE0
static WRITE64_HANDLER( ta_texture_directpath0_w )
{
naomi_state *state = space.machine().driver_data<naomi_state>();
int mode = state->pvrctrl_regs[SB_LMMODE0]&1;
// SB_LMMODE0
WRITE64_MEMBER(naomi_state::ta_texture_directpath0_w )
{
int mode = pvrctrl_regs[SB_LMMODE0]&1;
if (mode&1)
{
printf("ta_texture_directpath0_w 32-bit access!\n");
COMBINE_DATA(&state->dc_framebuffer_ram[offset]);
COMBINE_DATA(&dc_framebuffer_ram[offset]);
}
else
{
COMBINE_DATA(&state->dc_texture_ram[offset]);
}
COMBINE_DATA(&dc_texture_ram[offset]);
}
}
// SB_LMMODE1
static WRITE64_HANDLER( ta_texture_directpath1_w )
{
naomi_state *state = space.machine().driver_data<naomi_state>();
int mode = state->pvrctrl_regs[SB_LMMODE1]&1;
// SB_LMMODE1
WRITE64_MEMBER(naomi_state::ta_texture_directpath1_w )
{
int mode = pvrctrl_regs[SB_LMMODE1]&1;
if (mode&1)
{
printf("ta_texture_directpath1_w 32-bit access!\n");
COMBINE_DATA(&state->dc_framebuffer_ram[offset]);
COMBINE_DATA(&dc_framebuffer_ram[offset]);
}
else
{
COMBINE_DATA(&state->dc_texture_ram[offset]);
}
COMBINE_DATA(&dc_texture_ram[offset]);
}
}
/*
@ -1566,21 +1553,21 @@ static ADDRESS_MAP_START( naomi_map, AS_PROGRAM, 64, naomi_state )
AM_RANGE(0x00000000, 0x001fffff) AM_MIRROR(0xa2000000) AM_ROM AM_REGION("maincpu", 0) // BIOS
AM_RANGE(0x00200000, 0x00207fff) AM_MIRROR(0x02000000) AM_RAM // bios uses it (battery backed ram ?)
AM_RANGE(0x005f6800, 0x005f69ff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6800, 0x005f69ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6c00, 0x005f6cff) AM_MIRROR(0x02000000) AM_DEVICE32( "maple_dc", maple_dc_device, amap, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", naomi_board, submap, U64(0x0000ffff0000ffff) )
AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(dc_modem_r, dc_modem_w )
AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(dc_rtc_r, dc_rtc_w )
AM_RANGE(0x00800000, 0x00ffffff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(naomi_arm_r, naomi_arm_w ) // sound RAM (8 MB)
AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
AM_RANGE(0x00800000, 0x00ffffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_arm_r, naomi_arm_w ) // sound RAM (8 MB)
/* External Device */
AM_RANGE(0x01010098, 0x0101009f) AM_MIRROR(0x02000000) AM_RAM // Naomi 2 BIOS tests this, needs to read back as written
AM_RANGE(0x0103ff00, 0x0103ffff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
AM_RANGE(0x0103ff00, 0x0103ffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
/* Area 1 */
AM_RANGE(0x04000000, 0x04ffffff) AM_MIRROR(0x02000000) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
@ -1595,9 +1582,9 @@ static ADDRESS_MAP_START( naomi_map, AS_PROGRAM, 64, naomi_state )
/* Area 4 */
AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_poly_w )
AM_RANGE(0x10800000, 0x10ffffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_yuv_w )
AM_RANGE(0x11000000, 0x11ffffff) AM_WRITE_LEGACY(ta_texture_directpath0_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
AM_RANGE(0x11000000, 0x11ffffff) AM_WRITE(ta_texture_directpath0_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
/* 0x12000000 -0x13ffffff Mirror area of 0x10000000 -0x11ffffff */
AM_RANGE(0x13000000, 0x13ffffff) AM_WRITE_LEGACY(ta_texture_directpath1_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
AM_RANGE(0x13000000, 0x13ffffff) AM_WRITE(ta_texture_directpath1_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
/* Area 5 */
//AM_RANGE(0x14000000, 0x17ffffff) AM_NOP // MPX Ext.
@ -1618,24 +1605,24 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
AM_RANGE(0x00000000, 0x001fffff) AM_MIRROR(0xa2000000) AM_ROM AM_REGION("maincpu", 0) // BIOS
AM_RANGE(0x00200000, 0x00207fff) AM_MIRROR(0x02000000) AM_RAM // bios uses it (battery backed ram ?)
AM_RANGE(0x005f6800, 0x005f69ff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6800, 0x005f69ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6c00, 0x005f6cff) AM_MIRROR(0x02000000) AM_DEVICE32( "maple_dc", maple_dc_device, amap, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", naomi_board, submap, U64(0x0000ffff0000ffff) )
AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE_LEGACY(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x005f8000, 0x005f9fff) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(dc_modem_r, dc_modem_w )
AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(dc_rtc_r, dc_rtc_w )
AM_RANGE(0x00800000, 0x00ffffff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(naomi_arm_r, naomi_arm_w ) // sound RAM (8 MB)
AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
AM_RANGE(0x00800000, 0x00ffffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_arm_r, naomi_arm_w ) // sound RAM (8 MB)
/* External Device */
AM_RANGE(0x01010098, 0x0101009f) AM_MIRROR(0x02000000) AM_RAM // Naomi 2 BIOS tests this, needs to read back as written
AM_RANGE(0x0103ff00, 0x0103ffff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
AM_RANGE(0x0103ff00, 0x0103ffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
// AM_RANGE(0x025f6800, 0x025f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w ) // second PVR DMA!
// AM_RANGE(0x025f7c00, 0x025f7cff) AM_READWRITE_LEGACY(pvr_ctrl_r, pvr_ctrl_w )
// AM_RANGE(0x025f7c00, 0x025f7cff) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x025f8000, 0x025f9fff) AM_READWRITE_LEGACY(pvr2_ta_r, pvr2_ta_w )
/* Area 1 */
@ -1645,7 +1632,7 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
AM_RANGE(0x07000000, 0x07ffffff) AM_RAM AM_SHARE("frameram2")// 32 bit access 2nd PVR RAM
/* Area 2*/
AM_RANGE(0x085f6800, 0x085f69ff) AM_WRITE_LEGACY(dc_sysctrl_w ) // writes to BOTH PVRs
AM_RANGE(0x085f6800, 0x085f69ff) AM_WRITE(dc_sysctrl_w ) // writes to BOTH PVRs
AM_RANGE(0x085f8000, 0x085f9fff) AM_WRITE_LEGACY(pvrs_ta_w ) // writes to BOTH PVRs
AM_RANGE(0x08800000, 0x088000ff) AM_READWRITE32_LEGACY(elan_regs_r, elan_regs_w, U64(0xffffffffffffffff) ) // T&L chip registers
// AM_RANGE(0x09000000, 0x09??????) T&L command processing
@ -1657,9 +1644,9 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
/* Area 4 */
AM_RANGE(0x10000000, 0x107fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
AM_RANGE(0x10800000, 0x10ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
AM_RANGE(0x11000000, 0x11ffffff) AM_WRITE_LEGACY(ta_texture_directpath0_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
AM_RANGE(0x11000000, 0x11ffffff) AM_WRITE(ta_texture_directpath0_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
/* 0x12000000 -0x13ffffff Mirror area of 0x10000000 -0x11ffffff */
AM_RANGE(0x13000000, 0x13ffffff) AM_WRITE_LEGACY(ta_texture_directpath1_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
AM_RANGE(0x13000000, 0x13ffffff) AM_WRITE(ta_texture_directpath1_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
/* Area 5 */
//AM_RANGE(0x14000000, 0x17ffffff) AM_NOP // MPX Ext.
@ -1673,20 +1660,20 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( naomi_port, AS_IO, 64, naomi_state )
AM_RANGE(0x00, 0x0f) AM_DEVREADWRITE_LEGACY("main_eeprom", eeprom_93c46a_r, eeprom_93c46a_w)
AM_RANGE(0x00, 0x0f) AM_READWRITE(eeprom_93c46a_r, eeprom_93c46a_w)
ADDRESS_MAP_END
/*
* Atomiswave address map, almost identical to Dreamcast
*/
static READ64_HANDLER( aw_flash_r )
READ64_MEMBER(naomi_state::aw_flash_r )
{
return (UINT64)awflash->read(offset*8) | (UINT64)awflash->read((offset*8)+1)<<8 | (UINT64)awflash->read((offset*8)+2)<<16 | (UINT64)awflash->read((offset*8)+3)<<24 |
(UINT64)awflash->read((offset*8)+4)<<32 | (UINT64)awflash->read((offset*8)+5)<<40 | (UINT64)awflash->read((offset*8)+6)<<48 | (UINT64)awflash->read((offset*8)+7)<<56;
return (UINT64)m_awflash->read(offset*8) | (UINT64)m_awflash->read((offset*8)+1)<<8 | (UINT64)m_awflash->read((offset*8)+2)<<16 | (UINT64)m_awflash->read((offset*8)+3)<<24 |
(UINT64)m_awflash->read((offset*8)+4)<<32 | (UINT64)m_awflash->read((offset*8)+5)<<40 | (UINT64)m_awflash->read((offset*8)+6)<<48 | (UINT64)m_awflash->read((offset*8)+7)<<56;
}
static WRITE64_HANDLER( aw_flash_w )
WRITE64_MEMBER(naomi_state::aw_flash_w )
{
int i;
UINT32 addr = offset * 8;
@ -1702,10 +1689,10 @@ static WRITE64_HANDLER( aw_flash_w )
data >>= (i*8);
awflash->write(addr, data);
m_awflash->write(addr, data);
}
INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_mask, UINT64 *shift)
inline int naomi_state::decode_reg32_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
{
int reg = offset * 2;
@ -1714,7 +1701,7 @@ INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_m
// non 32-bit accesses have not yet been seen here, we need to know when they are
if ((mem_mask != U64(0xffffffff00000000)) && (mem_mask != U64(0x00000000ffffffff)))
{
mame_printf_verbose("%s:Wrong mask!\n", machine.describe_context());
mame_printf_verbose("%s:Wrong mask!\n", machine().describe_context());
// debugger_break(machine);
}
@ -1727,16 +1714,16 @@ INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_m
return reg;
}
static READ64_HANDLER( aw_modem_r )
READ64_MEMBER(naomi_state::aw_modem_r )
{
int reg;
UINT64 shift;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
if (reg == 0x280/4)
{
UINT32 coins = space.machine().root_device().ioport("COINS")->read();
UINT32 coins = ioport("COINS")->read();
if (coins & 0x01)
{
@ -1754,37 +1741,37 @@ static READ64_HANDLER( aw_modem_r )
return 0;
}
static WRITE64_HANDLER( aw_modem_w )
WRITE64_MEMBER(naomi_state::aw_modem_w )
{
int reg;
UINT64 shift;
UINT32 dat;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
mame_printf_verbose("MODEM: [%08x=%x] write %" I64FMT "x to %x, mask %" I64FMT "x\n", 0x600000+reg*4, dat, data, offset, mem_mask);
}
static ADDRESS_MAP_START( aw_map, AS_PROGRAM, 64, naomi_state )
/* Area 0 */
AM_RANGE(0x00000000, 0x0001ffff) AM_READWRITE_LEGACY(aw_flash_r, aw_flash_w ) AM_REGION("awflash", 0)
AM_RANGE(0xa0000000, 0xa001ffff) AM_READWRITE_LEGACY(aw_flash_r, aw_flash_w ) AM_REGION("awflash", 0)
AM_RANGE(0x00000000, 0x0001ffff) AM_READWRITE(aw_flash_r, aw_flash_w ) AM_REGION("awflash", 0)
AM_RANGE(0xa0000000, 0xa001ffff) AM_READWRITE(aw_flash_r, aw_flash_w ) AM_REGION("awflash", 0)
AM_RANGE(0x00200000, 0x0021ffff) AM_RAM // battery backed up RAM
AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6c00, 0x005f6cff) AM_MIRROR(0x02000000) AM_DEVICE32( "maple_dc", maple_dc_device, amap, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", aw_rom_board, submap, U64(0x0000ffff0000ffff) )
AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE_LEGACY(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE_LEGACY(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x005f8000, 0x005f9fff) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE_LEGACY(aw_modem_r, aw_modem_w )
AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(aw_modem_r, aw_modem_w )
AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE_LEGACY(dc_rtc_r, dc_rtc_w )
AM_RANGE(0x00800000, 0x00ffffff) AM_READWRITE_LEGACY(naomi_arm_r, naomi_arm_w ) // sound RAM (8 MB)
AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )
AM_RANGE(0x00800000, 0x00ffffff) AM_READWRITE(naomi_arm_r, naomi_arm_w ) // sound RAM (8 MB)
AM_RANGE(0x0103ff00, 0x0103ffff) AM_READWRITE_LEGACY(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
AM_RANGE(0x0103ff00, 0x0103ffff) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
/* Area 1 - half the texture memory, like dreamcast, not naomi */
AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_MIRROR(0x00800000) AM_SHARE("dc_texture_ram") // texture memory 64 bit access
@ -1805,9 +1792,9 @@ static ADDRESS_MAP_START( aw_map, AS_PROGRAM, 64, naomi_state )
/* Area 4 - half the texture memory, like dreamcast, not naomi */
AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_poly_w )
AM_RANGE(0x10800000, 0x10ffffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_yuv_w )
AM_RANGE(0x11000000, 0x117fffff) AM_WRITE_LEGACY(ta_texture_directpath0_w ) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
AM_RANGE(0x11000000, 0x117fffff) AM_WRITE(ta_texture_directpath0_w ) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
/* 0x12000000 -0x13ffffff Mirror area of 0x10000000 -0x11ffffff */
AM_RANGE(0x13000000, 0x137fffff) AM_WRITE_LEGACY(ta_texture_directpath1_w ) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
AM_RANGE(0x13000000, 0x137fffff) AM_WRITE(ta_texture_directpath1_w ) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
/* Area 5 */
@ -7582,8 +7569,6 @@ DRIVER_INIT_MEMBER(naomi_state,atomiswave)
// patch out long startup delay
ROM[0x98e/8] = (ROM[0x98e/8] & U64(0xffffffffffff)) | (UINT64)0x0009<<48;
awflash = machine().device<macronix_29l001mc_device>("awflash");
}
ROM_START( fotns )

43
src/mame/includes/dc.h
View File

@ -90,30 +90,29 @@ class dc_state : public driver_device
DECLARE_WRITE64_MEMBER(dc_aica_reg_w);
DECLARE_READ32_MEMBER(dc_arm_aica_r);
DECLARE_WRITE32_MEMBER(dc_arm_aica_w);
void wave_dma_execute(address_space &space);
void pvr_dma_execute(address_space &space);
inline int decode_reg32_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift);
inline int decode_reg3216_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift);
int dc_compute_interrupt_level();
void dc_update_interrupt_status();
inline int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift);
void rtc_initial_setup();
DECLARE_READ64_MEMBER( dc_sysctrl_r );
DECLARE_WRITE64_MEMBER( dc_sysctrl_w );
DECLARE_READ64_MEMBER( dc_gdrom_r );
DECLARE_WRITE64_MEMBER( dc_gdrom_w );
DECLARE_READ64_MEMBER( dc_g2_ctrl_r );
DECLARE_WRITE64_MEMBER( dc_g2_ctrl_w );
DECLARE_READ64_MEMBER( pvr_ctrl_r );
DECLARE_WRITE64_MEMBER( pvr_ctrl_w );
DECLARE_READ64_MEMBER( dc_modem_r );
DECLARE_WRITE64_MEMBER( dc_modem_w );
DECLARE_READ64_MEMBER( dc_rtc_r );
DECLARE_WRITE64_MEMBER( dc_rtc_w );
};
/*----------- defined in machine/dc.c -----------*/
DECLARE_READ64_HANDLER( pvr_ctrl_r );
DECLARE_WRITE64_HANDLER( pvr_ctrl_w );
DECLARE_READ64_HANDLER( dc_sysctrl_r );
DECLARE_WRITE64_HANDLER( dc_sysctrl_w );
DECLARE_READ64_HANDLER( dc_gdrom_r );
DECLARE_WRITE64_HANDLER( dc_gdrom_w );
DECLARE_READ64_HANDLER( dc_g1_ctrl_r );
DECLARE_WRITE64_HANDLER( dc_g1_ctrl_w );
DECLARE_READ64_HANDLER( dc_g2_ctrl_r );
DECLARE_WRITE64_HANDLER( dc_g2_ctrl_w );
DECLARE_READ64_HANDLER( dc_modem_r );
DECLARE_WRITE64_HANDLER( dc_modem_w );
DECLARE_READ64_HANDLER( dc_rtc_r );
DECLARE_WRITE64_HANDLER( dc_rtc_w );
int dc_compute_interrupt_level(running_machine &machine);
void dc_update_interrupt_status(running_machine &machine);
/*--------- Ch2-DMA Control Registers ----------*/
#define SB_C2DSTAT ((0x005f6800-0x005f6800)/4)
#define SB_C2DLEN ((0x005f6804-0x005f6800)/4)

41
src/mame/includes/naomi.h
View File

@ -3,6 +3,8 @@
naomi.h -> NAOMI includes
*/
#include "machine/eeprom.h"
#include "machine/intelfsh.h"
enum {
JVSBD_DEFAULT = 0,
@ -18,12 +20,16 @@ class naomi_state : public dc_state
: dc_state(mconfig, type, tag),
pvr2_texture_ram(*this, "textureram2"),
pvr2_framebuffer_ram(*this, "frameram2"),
elan_ram(*this, "elan_ram") { }
elan_ram(*this, "elan_ram"),
m_awflash(*this, "awflash"),
m_eeprom(*this, "main_eeprom") { }
/* Naomi 2 specific (To be moved) */
optional_shared_ptr<UINT64> pvr2_texture_ram;
optional_shared_ptr<UINT64> pvr2_framebuffer_ram;
optional_shared_ptr<UINT64> elan_ram;
optional_device<macronix_29l001mc_device> m_awflash;
optional_device<eeprom_device> m_eeprom;
DECLARE_WRITE_LINE_MEMBER(aica_irq);
DECLARE_MACHINE_RESET(naomi);
@ -43,15 +49,40 @@ class naomi_state : public dc_state
DECLARE_DRIVER_INIT(vf4evoct);
DECLARE_DRIVER_INIT(naomi_mp);
DECLARE_DRIVER_INIT(mvsc2);
DECLARE_READ64_MEMBER( naomi_arm_r );
DECLARE_WRITE64_MEMBER( naomi_arm_w );
DECLARE_READ64_MEMBER( naomi_unknown1_r );
DECLARE_WRITE64_MEMBER( naomi_unknown1_w );
DECLARE_READ64_MEMBER( eeprom_93c46a_r );
DECLARE_WRITE64_MEMBER( eeprom_93c46a_w );
DECLARE_WRITE64_MEMBER( ta_texture_directpath0_w );
DECLARE_WRITE64_MEMBER( ta_texture_directpath1_w );
DECLARE_READ64_MEMBER( aw_flash_r );
DECLARE_WRITE64_MEMBER( aw_flash_w );
DECLARE_READ64_MEMBER( aw_modem_r );
DECLARE_WRITE64_MEMBER( aw_modem_w );
inline int decode_reg32_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift);
int jvsboard_type;
UINT16 actel_id;
UINT8 asciihex_to_dec(UINT8 in);
void create_pic_from_retdat();
DECLARE_READ64_MEMBER( naomi_biose_idle_skip_r );
DECLARE_READ64_MEMBER( naomi_biosh_idle_skip_r );
DECLARE_READ64_MEMBER( naomi2_biose_idle_skip_r );
DECLARE_READ64_MEMBER( naomigd_ggxxsla_idle_skip_r );
DECLARE_READ64_MEMBER( naomigd_ggxx_idle_skip_r );
DECLARE_READ64_MEMBER( naomigd_ggxxrl_idle_skip_r );
DECLARE_READ64_MEMBER( naomigd_sfz3ugd_idle_skip_r );
DECLARE_READ64_MEMBER( hotd2_idle_skip_r );
};
/*----------- defined in machine/gdcrypt.c -----------*/
extern void naomi_game_decrypt(running_machine& machine, UINT64 key, UINT8* region, int length);
/*----------- defined in machine/naomi.c -----------*/
extern int jvsboard_type;
extern UINT16 actel_id;
void naomi_g1_irq(running_machine &machine);

336
src/mame/machine/dc.c
View File

@ -79,14 +79,14 @@ TIMER_CALLBACK_MEMBER(dc_state::aica_dma_irq)
{
m_wave_dma.start = g2bus_regs[SB_ADST] = 0;
dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_AICA;
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
TIMER_CALLBACK_MEMBER(dc_state::pvr_dma_irq)
{
m_pvr_dma.start = pvrctrl_regs[SB_PDST] = 0;
dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_PVR;
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
void naomi_g1_irq(running_machine &machine)
@ -94,7 +94,7 @@ void naomi_g1_irq(running_machine &machine)
dc_state *state = machine.driver_data<dc_state>();
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_GDROM;
dc_update_interrupt_status(machine);
state->dc_update_interrupt_status();
}
void dc_maple_irq(running_machine &machine)
@ -102,7 +102,7 @@ void dc_maple_irq(running_machine &machine)
dc_state *state = machine.driver_data<dc_state>();
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_MAPLE;
dc_update_interrupt_status(machine);
state->dc_update_interrupt_status();
}
TIMER_CALLBACK_MEMBER(dc_state::ch2_dma_irq)
@ -110,30 +110,28 @@ TIMER_CALLBACK_MEMBER(dc_state::ch2_dma_irq)
dc_sysctrl_regs[SB_C2DLEN]=0;
dc_sysctrl_regs[SB_C2DST]=0;
dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_CH2;
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
TIMER_CALLBACK_MEMBER(dc_state::yuv_fifo_irq)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_YUV;
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
static void wave_dma_execute(address_space &space)
void dc_state::wave_dma_execute(address_space &space)
{
dc_state *state = space.machine().driver_data<dc_state>();
UINT32 src,dst,size;
dst = state->m_wave_dma.aica_addr;
src = state->m_wave_dma.root_addr;
dst = m_wave_dma.aica_addr;
src = m_wave_dma.root_addr;
size = 0;
/* 0 rounding size = 32 Mbytes */
if(state->m_wave_dma.size == 0) { state->m_wave_dma.size = 0x200000; }
if(m_wave_dma.size == 0) { m_wave_dma.size = 0x200000; }
if(state->m_wave_dma.dir == 0)
if(m_wave_dma.dir == 0)
{
for(;size<state->m_wave_dma.size;size+=4)
for(;size<m_wave_dma.size;size+=4)
{
space.write_dword(dst,space.read_dword(src));
src+=4;
@ -142,7 +140,7 @@ static void wave_dma_execute(address_space &space)
}
else
{
for(;size<state->m_wave_dma.size;size+=4)
for(;size<m_wave_dma.size;size+=4)
{
space.write_dword(src,space.read_dword(dst));
src+=4;
@ -151,35 +149,33 @@ static void wave_dma_execute(address_space &space)
}
/* update the params*/
state->m_wave_dma.aica_addr = state->g2bus_regs[SB_ADSTAG] = dst;
state->m_wave_dma.root_addr = state->g2bus_regs[SB_ADSTAR] = src;
state->m_wave_dma.size = state->g2bus_regs[SB_ADLEN] = 0;
state->m_wave_dma.flag = (state->m_wave_dma.indirect & 1) ? 1 : 0;
m_wave_dma.aica_addr = g2bus_regs[SB_ADSTAG] = dst;
m_wave_dma.root_addr = g2bus_regs[SB_ADSTAR] = src;
m_wave_dma.size = g2bus_regs[SB_ADLEN] = 0;
m_wave_dma.flag = (m_wave_dma.indirect & 1) ? 1 : 0;
/* Note: if you trigger an instant DMA IRQ trigger, sfz3upper doesn't play any bgm. */
/* TODO: timing of this */
space.machine().scheduler().timer_set(attotime::from_usec(300), timer_expired_delegate(FUNC(dc_state::aica_dma_irq),state));
machine().scheduler().timer_set(attotime::from_usec(300), timer_expired_delegate(FUNC(dc_state::aica_dma_irq),this));
}
static void pvr_dma_execute(address_space &space)
void dc_state::pvr_dma_execute(address_space &space)
{
dc_state *state = space.machine().driver_data<dc_state>();
UINT32 src,dst,size;
dst = state->m_pvr_dma.pvr_addr;
src = state->m_pvr_dma.sys_addr;
dst = m_pvr_dma.pvr_addr;
src = m_pvr_dma.sys_addr;
size = 0;
/* used so far by usagui and sprtjam*/
//printf("PVR-DMA start\n");
//printf("%08x %08x %08x\n",state->m_pvr_dma.pvr_addr,state->m_pvr_dma.sys_addr,state->m_pvr_dma.size);
//printf("src %s dst %08x\n",state->m_pvr_dma.dir ? "->" : "<-",state->m_pvr_dma.sel);
//printf("%08x %08x %08x\n",m_pvr_dma.pvr_addr,m_pvr_dma.sys_addr,m_pvr_dma.size);
//printf("src %s dst %08x\n",m_pvr_dma.dir ? "->" : "<-",m_pvr_dma.sel);
/* 0 rounding size = 16 Mbytes */
if(state->m_pvr_dma.size == 0) { state->m_pvr_dma.size = 0x100000; }
if(m_pvr_dma.size == 0) { m_pvr_dma.size = 0x100000; }
if(state->m_pvr_dma.dir == 0)
if(m_pvr_dma.dir == 0)
{
for(;size<state->m_pvr_dma.size;size+=4)
for(;size<m_pvr_dma.size;size+=4)
{
space.write_dword(dst,space.read_dword(src));
src+=4;
@ -188,7 +184,7 @@ static void pvr_dma_execute(address_space &space)
}
else
{
for(;size<state->m_pvr_dma.size;size+=4)
for(;size<m_pvr_dma.size;size+=4)
{
space.write_dword(src,space.read_dword(dst));
src+=4;
@ -197,13 +193,13 @@ static void pvr_dma_execute(address_space &space)
}
/* Note: do not update the params, since this DMA type doesn't support it. */
/* TODO: timing of this */
space.machine().scheduler().timer_set(attotime::from_usec(250), timer_expired_delegate(FUNC(dc_state::pvr_dma_irq),state));
machine().scheduler().timer_set(attotime::from_usec(250), timer_expired_delegate(FUNC(dc_state::pvr_dma_irq),this));
}
// register decode helpers
// this accepts only 32-bit accesses
INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_mask, UINT64 *shift)
int dc_state::decode_reg32_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
{
int reg = offset * 2;
@ -212,7 +208,7 @@ INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_m
// non 32-bit accesses have not yet been seen here, we need to know when they are
if ((mem_mask != U64(0xffffffff00000000)) && (mem_mask != U64(0x00000000ffffffff)))
{
mame_printf_verbose("%s:Wrong mask!\n", machine.describe_context());
mame_printf_verbose("%s:Wrong mask!\n", machine().describe_context());
// debugger_break(machine);
}
@ -226,7 +222,7 @@ INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_m
}
// this accepts only 32 and 16 bit accesses
INLINE int decode_reg3216_64(running_machine &machine, UINT32 offset, UINT64 mem_mask, UINT64 *shift)
int dc_state::decode_reg3216_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
{
int reg = offset * 2;
@ -236,7 +232,7 @@ INLINE int decode_reg3216_64(running_machine &machine, UINT32 offset, UINT64 mem
if ((mem_mask != U64(0x0000ffff00000000)) && (mem_mask != U64(0x000000000000ffff)) &&
(mem_mask != U64(0xffffffff00000000)) && (mem_mask != U64(0x00000000ffffffff)))
{
mame_printf_verbose("%s:Wrong mask!\n", machine.describe_context());
mame_printf_verbose("%s:Wrong mask!\n", machine().describe_context());
// debugger_break(machine);
}
@ -249,30 +245,29 @@ INLINE int decode_reg3216_64(running_machine &machine, UINT32 offset, UINT64 mem
return reg;
}
int dc_compute_interrupt_level(running_machine &machine)
int dc_state::dc_compute_interrupt_level()
{
dc_state *state = machine.driver_data<dc_state>();
UINT32 ln,lx,le;
ln=state->dc_sysctrl_regs[SB_ISTNRM] & state->dc_sysctrl_regs[SB_IML6NRM];
lx=state->dc_sysctrl_regs[SB_ISTEXT] & state->dc_sysctrl_regs[SB_IML6EXT];
le=state->dc_sysctrl_regs[SB_ISTERR] & state->dc_sysctrl_regs[SB_IML6ERR];
ln=dc_sysctrl_regs[SB_ISTNRM] & dc_sysctrl_regs[SB_IML6NRM];
lx=dc_sysctrl_regs[SB_ISTEXT] & dc_sysctrl_regs[SB_IML6EXT];
le=dc_sysctrl_regs[SB_ISTERR] & dc_sysctrl_regs[SB_IML6ERR];
if (ln | lx | le)
{
return 6;
}
ln=state->dc_sysctrl_regs[SB_ISTNRM] & state->dc_sysctrl_regs[SB_IML4NRM];
lx=state->dc_sysctrl_regs[SB_ISTEXT] & state->dc_sysctrl_regs[SB_IML4EXT];
le=state->dc_sysctrl_regs[SB_ISTERR] & state->dc_sysctrl_regs[SB_IML4ERR];
ln=dc_sysctrl_regs[SB_ISTNRM] & dc_sysctrl_regs[SB_IML4NRM];
lx=dc_sysctrl_regs[SB_ISTEXT] & dc_sysctrl_regs[SB_IML4EXT];
le=dc_sysctrl_regs[SB_ISTERR] & dc_sysctrl_regs[SB_IML4ERR];
if (ln | lx | le)
{
return 4;
}
ln=state->dc_sysctrl_regs[SB_ISTNRM] & state->dc_sysctrl_regs[SB_IML2NRM];
lx=state->dc_sysctrl_regs[SB_ISTEXT] & state->dc_sysctrl_regs[SB_IML2EXT];
le=state->dc_sysctrl_regs[SB_ISTERR] & state->dc_sysctrl_regs[SB_IML2ERR];
ln=dc_sysctrl_regs[SB_ISTNRM] & dc_sysctrl_regs[SB_IML2NRM];
lx=dc_sysctrl_regs[SB_ISTEXT] & dc_sysctrl_regs[SB_IML2EXT];
le=dc_sysctrl_regs[SB_ISTERR] & dc_sysctrl_regs[SB_IML2ERR];
if (ln | lx | le)
{
return 2;
@ -281,38 +276,37 @@ int dc_compute_interrupt_level(running_machine &machine)
return 0;
}
void dc_update_interrupt_status(running_machine &machine)
void dc_state::dc_update_interrupt_status()
{
dc_state *state = machine.driver_data<dc_state>();
int level;
if (state->dc_sysctrl_regs[SB_ISTERR])
if (dc_sysctrl_regs[SB_ISTERR])
{
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_ERROR;
dc_sysctrl_regs[SB_ISTNRM] |= IST_ERROR;
}
else
{
state->dc_sysctrl_regs[SB_ISTNRM] &= ~IST_ERROR;
dc_sysctrl_regs[SB_ISTNRM] &= ~IST_ERROR;
}
if (state->dc_sysctrl_regs[SB_ISTEXT])
if (dc_sysctrl_regs[SB_ISTEXT])
{
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_G1G2EXTSTAT;
dc_sysctrl_regs[SB_ISTNRM] |= IST_G1G2EXTSTAT;
}
else
{
state->dc_sysctrl_regs[SB_ISTNRM] &= ~IST_G1G2EXTSTAT;
dc_sysctrl_regs[SB_ISTNRM] &= ~IST_G1G2EXTSTAT;
}
level=dc_compute_interrupt_level(machine);
sh4_set_irln_input(machine.device("maincpu"), 15-level);
level=dc_compute_interrupt_level();
sh4_set_irln_input(machine().device("maincpu"), 15-level);
/* Wave DMA HW trigger */
if(state->m_wave_dma.flag && ((state->m_wave_dma.sel & 2) == 2))
if(m_wave_dma.flag && ((m_wave_dma.sel & 2) == 2))
{
if((state->dc_sysctrl_regs[SB_G2DTNRM] & state->dc_sysctrl_regs[SB_ISTNRM]) || (state->dc_sysctrl_regs[SB_G2DTEXT] & state->dc_sysctrl_regs[SB_ISTEXT]))
if((dc_sysctrl_regs[SB_G2DTNRM] & dc_sysctrl_regs[SB_ISTNRM]) || (dc_sysctrl_regs[SB_G2DTEXT] & dc_sysctrl_regs[SB_ISTEXT]))
{
address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
printf("Wave DMA HW trigger\n");
wave_dma_execute(space);
@ -320,11 +314,11 @@ void dc_update_interrupt_status(running_machine &machine)
}
/* PVR-DMA HW trigger */
if(state->m_pvr_dma.flag && ((state->m_pvr_dma.sel & 1) == 1))
if(m_pvr_dma.flag && ((m_pvr_dma.sel & 1) == 1))
{
if((state->dc_sysctrl_regs[SB_PDTNRM] & state->dc_sysctrl_regs[SB_ISTNRM]) || (state->dc_sysctrl_regs[SB_PDTEXT] & state->dc_sysctrl_regs[SB_ISTEXT]))
if((dc_sysctrl_regs[SB_PDTNRM] & dc_sysctrl_regs[SB_ISTNRM]) || (dc_sysctrl_regs[SB_PDTEXT] & dc_sysctrl_regs[SB_ISTEXT]))
{
address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
printf("PVR-DMA HW trigger\n");
pvr_dma_execute(space);
@ -332,54 +326,50 @@ void dc_update_interrupt_status(running_machine &machine)
}
}
READ64_HANDLER( dc_sysctrl_r )
READ64_MEMBER(dc_state::dc_sysctrl_r )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
#if DEBUG_SYSCTRL
if ((reg != 0x40) && (reg != 0x41) && (reg != 0x42) && (reg != 0x23) && (reg > 2)) // filter out IRQ status reads
{
mame_printf_verbose("SYSCTRL: [%08x] read %x @ %x (reg %x: %s), mask %" I64FMT "x (PC=%x)\n", 0x5f6800+reg*4, state->dc_sysctrl_regs[reg], offset, reg, sysctrl_names[reg], mem_mask, space.device().safe_pc());
mame_printf_verbose("SYSCTRL: [%08x] read %x @ %x (reg %x: %s), mask %" I64FMT "x (PC=%x)\n", 0x5f6800+reg*4, dc_sysctrl_regs[reg], offset, reg, sysctrl_names[reg], mem_mask, space.device().safe_pc());
}
#endif
return (UINT64)state->dc_sysctrl_regs[reg] << shift;
return (UINT64)dc_sysctrl_regs[reg] << shift;
}
WRITE64_HANDLER( dc_sysctrl_w )
WRITE64_MEMBER(dc_state::dc_sysctrl_w )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
UINT32 old,dat;
UINT32 address;
struct sh4_ddt_dma ddtdata;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
old = state->dc_sysctrl_regs[reg];
state->dc_sysctrl_regs[reg] = dat; // 5f6800+off*4=dat
old = dc_sysctrl_regs[reg];
dc_sysctrl_regs[reg] = dat; // 5f6800+off*4=dat
switch (reg)
{
case SB_C2DST:
if(((old & 1) == 0) && (dat & 1)) // 0 -> 1
{
address=(state->dc_sysctrl_regs[SB_C2DSTAT] & 0x03ffffe0) | 0x10000000;
if(state->dc_sysctrl_regs[SB_C2DSTAT] & 0x1f)
printf("C2DSTAT just used to reserved bits %02x\n",state->dc_sysctrl_regs[SB_C2DSTAT] & 0x1f);
address=(dc_sysctrl_regs[SB_C2DSTAT] & 0x03ffffe0) | 0x10000000;
if(dc_sysctrl_regs[SB_C2DSTAT] & 0x1f)
printf("C2DSTAT just used to reserved bits %02x\n",dc_sysctrl_regs[SB_C2DSTAT] & 0x1f);
ddtdata.destination=address;
/* 0 rounding size = 16 Mbytes */
if(state->dc_sysctrl_regs[SB_C2DLEN] == 0)
if(dc_sysctrl_regs[SB_C2DLEN] == 0)
ddtdata.length = 0x1000000;
else
ddtdata.length = state->dc_sysctrl_regs[SB_C2DLEN];
ddtdata.length = dc_sysctrl_regs[SB_C2DLEN];
ddtdata.size=1;
ddtdata.direction=0;
ddtdata.channel=2;
@ -387,49 +377,49 @@ WRITE64_HANDLER( dc_sysctrl_w )
sh4_dma_ddt(space.machine().device("maincpu"),&ddtdata);
#if DEBUG_SYSCTRL
if ((address >= 0x11000000) && (address <= 0x11FFFFFF))
if (state->dc_sysctrl_regs[SB_LMMODE0])
printf("SYSCTRL: Ch2 direct display lists dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", state->dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, state->dc_sysctrl_regs[SB_C2DSTAT],state->dc_sysctrl_regs[SB_LMMODE0],state->dc_sysctrl_regs[SB_LMMODE1]); // 1
if (dc_sysctrl_regs[SB_LMMODE0])
printf("SYSCTRL: Ch2 direct display lists dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, dc_sysctrl_regs[SB_C2DSTAT],dc_sysctrl_regs[SB_LMMODE0],dc_sysctrl_regs[SB_LMMODE1]); // 1
else
mame_printf_verbose("SYSCTRL: Ch2 direct textures dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", state->dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, state->dc_sysctrl_regs[SB_C2DSTAT],state->dc_sysctrl_regs[SB_LMMODE0],state->dc_sysctrl_regs[SB_LMMODE1]); // 0
mame_printf_verbose("SYSCTRL: Ch2 direct textures dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, dc_sysctrl_regs[SB_C2DSTAT],dc_sysctrl_regs[SB_LMMODE0],dc_sysctrl_regs[SB_LMMODE1]); // 0
else if ((address >= 0x13000000) && (address <= 0x13FFFFFF))
if (state->dc_sysctrl_regs[SB_LMMODE1])
printf("SYSCTRL: Ch2 direct display lists dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", state->dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, state->dc_sysctrl_regs[SB_C2DSTAT],state->dc_sysctrl_regs[SB_LMMODE0],state->dc_sysctrl_regs[SB_LMMODE1]); // 1
if (dc_sysctrl_regs[SB_LMMODE1])
printf("SYSCTRL: Ch2 direct display lists dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, dc_sysctrl_regs[SB_C2DSTAT],dc_sysctrl_regs[SB_LMMODE0],dc_sysctrl_regs[SB_LMMODE1]); // 1
else
mame_printf_verbose("SYSCTRL: Ch2 direct textures dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", state->dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, state->dc_sysctrl_regs[SB_C2DSTAT],state->dc_sysctrl_regs[SB_LMMODE0],state->dc_sysctrl_regs[SB_LMMODE1]); // 0
mame_printf_verbose("SYSCTRL: Ch2 direct textures dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, dc_sysctrl_regs[SB_C2DSTAT],dc_sysctrl_regs[SB_LMMODE0],dc_sysctrl_regs[SB_LMMODE1]); // 0
else if ((address >= 0x10800000) && (address <= 0x10ffffff))
printf("SYSCTRL: Ch2 YUV dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", state->dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, state->dc_sysctrl_regs[SB_C2DSTAT],state->dc_sysctrl_regs[SB_LMMODE0],state->dc_sysctrl_regs[SB_LMMODE1]);
printf("SYSCTRL: Ch2 YUV dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, dc_sysctrl_regs[SB_C2DSTAT],dc_sysctrl_regs[SB_LMMODE0],dc_sysctrl_regs[SB_LMMODE1]);
else if ((address >= 0x10000000) && (address <= 0x107fffff))
mame_printf_verbose("SYSCTRL: Ch2 TA Display List dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", state->dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, state->dc_sysctrl_regs[SB_C2DSTAT],state->dc_sysctrl_regs[SB_LMMODE0],state->dc_sysctrl_regs[SB_LMMODE1]);
mame_printf_verbose("SYSCTRL: Ch2 TA Display List dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, dc_sysctrl_regs[SB_C2DSTAT],dc_sysctrl_regs[SB_LMMODE0],dc_sysctrl_regs[SB_LMMODE1]);
else
mame_printf_verbose("SYSCTRL: Ch2 unknown dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", state->dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, state->dc_sysctrl_regs[SB_C2DSTAT],state->dc_sysctrl_regs[SB_LMMODE0],state->dc_sysctrl_regs[SB_LMMODE1]);
mame_printf_verbose("SYSCTRL: Ch2 unknown dma %x from %08x to %08x (lmmode0=%d lmmode1=%d)\n", dc_sysctrl_regs[SB_C2DLEN], ddtdata.source-ddtdata.length, dc_sysctrl_regs[SB_C2DSTAT],dc_sysctrl_regs[SB_LMMODE0],dc_sysctrl_regs[SB_LMMODE1]);
#endif
if ((!(address & 0x01000000)))
state->dc_sysctrl_regs[SB_C2DSTAT]=address;
dc_sysctrl_regs[SB_C2DSTAT]=address;
else //direct texture path
state->dc_sysctrl_regs[SB_C2DSTAT]=address+ddtdata.length;
dc_sysctrl_regs[SB_C2DSTAT]=address+ddtdata.length;
/* 200 usecs breaks sfz3upper */
space.machine().scheduler().timer_set(attotime::from_usec(50), timer_expired_delegate(FUNC(dc_state::ch2_dma_irq),state));
machine().scheduler().timer_set(attotime::from_usec(50), timer_expired_delegate(FUNC(dc_state::ch2_dma_irq),this));
/* simulate YUV FIFO processing here */
if((address & 0x1800000) == 0x0800000)
space.machine().scheduler().timer_set(attotime::from_usec(500), timer_expired_delegate(FUNC(dc_state::yuv_fifo_irq),state));
machine().scheduler().timer_set(attotime::from_usec(500), timer_expired_delegate(FUNC(dc_state::yuv_fifo_irq),this));
}
break;
case SB_ISTNRM:
state->dc_sysctrl_regs[SB_ISTNRM] = old & ~(dat | 0xC0000000); // bits 31,30 ro
dc_update_interrupt_status(space.machine());
dc_sysctrl_regs[SB_ISTNRM] = old & ~(dat | 0xC0000000); // bits 31,30 ro
dc_update_interrupt_status();
break;
case SB_ISTEXT:
state->dc_sysctrl_regs[SB_ISTEXT] = old;
dc_update_interrupt_status(space.machine());
dc_sysctrl_regs[SB_ISTEXT] = old;
dc_update_interrupt_status();
break;
case SB_ISTERR:
state->dc_sysctrl_regs[SB_ISTERR] = old & ~dat;
dc_update_interrupt_status(space.machine());
dc_sysctrl_regs[SB_ISTERR] = old & ~dat;
dc_update_interrupt_status();
break;
case SB_SDST:
if(dat & 1)
@ -437,9 +427,9 @@ WRITE64_HANDLER( dc_sysctrl_w )
// TODO: Sort-DMA routine goes here
printf("Sort-DMA irq\n");
state->dc_sysctrl_regs[SB_SDST] = 0;
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_SORT;
dc_update_interrupt_status(space.machine());
dc_sysctrl_regs[SB_SDST] = 0;
dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_SORT;
dc_update_interrupt_status();
}
break;
}
@ -452,10 +442,8 @@ WRITE64_HANDLER( dc_sysctrl_w )
#endif
}
READ64_HANDLER( dc_gdrom_r )
READ64_MEMBER(dc_state::dc_gdrom_r )
{
// dc_state *state = space.machine().driver_data<dc_state>();
UINT32 off;
if ((int)~mem_mask & 1)
@ -475,9 +463,8 @@ READ64_HANDLER( dc_gdrom_r )
return 0;
}
WRITE64_HANDLER( dc_gdrom_w )
WRITE64_MEMBER(dc_state::dc_gdrom_w )
{
// dc_state *state = space.machine().driver_data<dc_state>();
UINT32 dat,off;
if ((int)~mem_mask & 1)
@ -494,63 +481,61 @@ WRITE64_HANDLER( dc_gdrom_w )
mame_printf_verbose("GDROM: [%08x=%x]write %" I64FMT "x to %x, mask %" I64FMT "x\n", 0x5f7000+off*4, dat, data, offset, mem_mask);
}
READ64_HANDLER( dc_g2_ctrl_r )
READ64_MEMBER(dc_state::dc_g2_ctrl_r )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
mame_printf_verbose("G2CTRL: Unmapped read %08x\n", 0x5f7800+reg*4);
return (UINT64)state->g2bus_regs[reg] << shift;
return (UINT64)g2bus_regs[reg] << shift;
}
WRITE64_HANDLER( dc_g2_ctrl_w )
WRITE64_MEMBER(dc_state::dc_g2_ctrl_w )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
UINT32 dat;
UINT8 old;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
state->g2bus_regs[reg] = dat; // 5f7800+reg*4=dat
g2bus_regs[reg] = dat; // 5f7800+reg*4=dat
switch (reg)
{
/*AICA Address register*/
case SB_ADSTAG: state->m_wave_dma.aica_addr = dat; break;
case SB_ADSTAG: m_wave_dma.aica_addr = dat; break;
/*Root address (work ram)*/
case SB_ADSTAR: state->m_wave_dma.root_addr = dat; break;
case SB_ADSTAR: m_wave_dma.root_addr = dat; break;
/*DMA size (in dword units, bit 31 is "set dma initiation enable setting to 0"*/
case SB_ADLEN:
state->m_wave_dma.size = dat & 0x7fffffff;
state->m_wave_dma.indirect = (dat & 0x80000000)>>31;
m_wave_dma.size = dat & 0x7fffffff;
m_wave_dma.indirect = (dat & 0x80000000)>>31;
break;
/*0 = root memory to aica / 1 = aica to root memory*/
case SB_ADDIR: state->m_wave_dma.dir = (dat & 1); break;
case SB_ADDIR: m_wave_dma.dir = (dat & 1); break;
/*dma flag (active HIGH, bug in docs)*/
case SB_ADEN: state->m_wave_dma.flag = (dat & 1); break;
case SB_ADEN: m_wave_dma.flag = (dat & 1); break;
/*
SB_ADTSEL
bit 1: (0) Wave DMA through SB_ADST flag (1) Wave DMA through irq trigger, defined by SB_G2DTNRM / SB_G2DTEXT
*/
case SB_ADTSEL: state->m_wave_dma.sel = dat & 7; break;
case SB_ADTSEL: m_wave_dma.sel = dat & 7; break;
/*ready for dma'ing*/
case SB_ADST:
old = state->m_wave_dma.start & 1;
state->m_wave_dma.start = dat & 1;
old = m_wave_dma.start & 1;
m_wave_dma.start = dat & 1;
#if DEBUG_AICA_DMA
printf("AICA: G2-DMA start \n");
printf("DST %08x SRC %08x SIZE %08x IND %02x\n",state->m_wave_dma.aica_addr,state->m_wave_dma.root_addr,state->m_wave_dma.size,state->m_wave_dma.indirect);
printf("SEL %08x ST %08x FLAG %08x DIR %02x\n",state->m_wave_dma.sel,state->m_wave_dma.start,state->m_wave_dma.flag,state->m_wave_dma.dir);
printf("DST %08x SRC %08x SIZE %08x IND %02x\n",m_wave_dma.aica_addr,m_wave_dma.root_addr,m_wave_dma.size,m_wave_dma.indirect);
printf("SEL %08x ST %08x FLAG %08x DIR %02x\n",m_wave_dma.sel,m_wave_dma.start,m_wave_dma.flag,m_wave_dma.dir);
#endif
//mame_printf_verbose("SB_ADST data %08x\n",dat);
if(((old & 1) == 0) && state->m_wave_dma.flag && state->m_wave_dma.start && ((state->m_wave_dma.sel & 2) == 0)) // 0 -> 1
if(((old & 1) == 0) && m_wave_dma.flag && m_wave_dma.start && ((m_wave_dma.sel & 2) == 0)) // 0 -> 1
wave_dma_execute(space);
break;
@ -575,7 +560,7 @@ WRITE64_HANDLER( dc_g2_ctrl_w )
}
}
INLINE int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
int dc_state::decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
{
int reg = offset * 2;
@ -597,24 +582,22 @@ INLINE int decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
return reg;
}
READ64_HANDLER( pvr_ctrl_r )
READ64_MEMBER(dc_state::pvr_ctrl_r )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
reg = decode_reg_64(offset, mem_mask, &shift);
#if DEBUG_PVRCTRL
mame_printf_verbose("PVRCTRL: [%08x] read %x @ %x (reg %x), mask %" I64FMT "x (PC=%x)\n", 0x5f7c00+reg*4, state->pvrctrl_regs[reg], offset, reg, mem_mask, space.device().safe_pc());
mame_printf_verbose("PVRCTRL: [%08x] read %x @ %x (reg %x), mask %" I64FMT "x (PC=%x)\n", 0x5f7c00+reg*4, pvrctrl_regs[reg], offset, reg, mem_mask, space.device().safe_pc());
#endif
return (UINT64)state->pvrctrl_regs[reg] << shift;
return (UINT64)pvrctrl_regs[reg] << shift;
}
WRITE64_HANDLER( pvr_ctrl_w )
WRITE64_MEMBER(dc_state::pvr_ctrl_w )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
UINT32 dat;
@ -625,21 +608,21 @@ WRITE64_HANDLER( pvr_ctrl_w )
switch (reg)
{
case SB_PDSTAP: state->m_pvr_dma.pvr_addr = dat; break;
case SB_PDSTAR: state->m_pvr_dma.sys_addr = dat; break;
case SB_PDLEN: state->m_pvr_dma.size = dat; break;
case SB_PDDIR: state->m_pvr_dma.dir = dat & 1; break;
case SB_PDSTAP: m_pvr_dma.pvr_addr = dat; break;
case SB_PDSTAR: m_pvr_dma.sys_addr = dat; break;
case SB_PDLEN: m_pvr_dma.size = dat; break;
case SB_PDDIR: m_pvr_dma.dir = dat & 1; break;
case SB_PDTSEL:
state->m_pvr_dma.sel = dat & 1;
//if(state->m_pvr_dma.sel & 1)
m_pvr_dma.sel = dat & 1;
//if(m_pvr_dma.sel & 1)
// printf("Warning: Unsupported irq mode trigger PVR-DMA\n");
break;
case SB_PDEN: state->m_pvr_dma.flag = dat & 1; break;
case SB_PDEN: m_pvr_dma.flag = dat & 1; break;
case SB_PDST:
old = state->m_pvr_dma.start & 1;
state->m_pvr_dma.start = dat & 1;
old = m_pvr_dma.start & 1;
m_pvr_dma.start = dat & 1;
if(((old & 1) == 0) && state->m_pvr_dma.flag && state->m_pvr_dma.start && ((state->m_pvr_dma.sel & 1) == 0)) // 0 -> 1
if(((old & 1) == 0) && m_pvr_dma.flag && m_pvr_dma.start && ((m_pvr_dma.sel & 1) == 0)) // 0 -> 1
pvr_dma_execute(space);
break;
}
@ -648,18 +631,17 @@ WRITE64_HANDLER( pvr_ctrl_w )
mame_printf_verbose("PVRCTRL: [%08x=%x] write %" I64FMT "x to %x (reg %x), mask %" I64FMT "x\n", 0x5f7c00+reg*4, dat, data>>shift, offset, reg, mem_mask);
#endif
// state->pvrctrl_regs[reg] |= dat;
state->pvrctrl_regs[reg] = dat;
// pvrctrl_regs[reg] |= dat;
pvrctrl_regs[reg] = dat;
}
READ64_HANDLER( dc_modem_r )
READ64_MEMBER(dc_state::dc_modem_r )
{
// dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
// from ElSemi: this makes Atomiswave do it's "verbose boot" with a Sammy logo and diagnostics instead of just running the cart.
// our PVR emulation is apparently not good enough for that to work yet though.
@ -672,57 +654,54 @@ READ64_HANDLER( dc_modem_r )
return 0;
}
WRITE64_HANDLER( dc_modem_w )
WRITE64_MEMBER(dc_state::dc_modem_w )
{
// dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
UINT32 dat;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
mame_printf_verbose("MODEM: [%08x=%x] write %" I64FMT "x to %x, mask %" I64FMT "x\n", 0x600000+reg*4, dat, data, offset, mem_mask);
}
READ64_HANDLER( dc_rtc_r )
READ64_MEMBER(dc_state::dc_rtc_r )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
reg = decode_reg3216_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg3216_64(offset, mem_mask, &shift);
mame_printf_verbose("RTC: Unmapped read %08x\n", 0x710000+reg*4);
return (UINT64)state->dc_rtcregister[reg] << shift;
return (UINT64)dc_rtcregister[reg] << shift;
}
WRITE64_HANDLER( dc_rtc_w )
WRITE64_MEMBER(dc_state::dc_rtc_w )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
UINT32 old,dat;
reg = decode_reg3216_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg3216_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
old = state->dc_rtcregister[reg];
state->dc_rtcregister[reg] = dat & 0xFFFF; // 5f6c00+off*4=dat
old = dc_rtcregister[reg];
dc_rtcregister[reg] = dat & 0xFFFF; // 5f6c00+off*4=dat
switch (reg)
{
case RTC1:
if (state->dc_rtcregister[RTC3])
state->dc_rtcregister[RTC3] = 0;
if (dc_rtcregister[RTC3])
dc_rtcregister[RTC3] = 0;
else
state->dc_rtcregister[reg] = old;
dc_rtcregister[reg] = old;
break;
case RTC2:
if (state->dc_rtcregister[RTC3] == 0)
state->dc_rtcregister[reg] = old;
if (dc_rtcregister[RTC3] == 0)
dc_rtcregister[reg] = old;
else
state->dc_rtc_timer->adjust(attotime::zero, 0, attotime::from_seconds(1));
dc_rtc_timer->adjust(attotime::zero, 0, attotime::from_seconds(1));
break;
case RTC3:
state->dc_rtcregister[RTC3] &= 1;
dc_rtcregister[RTC3] &= 1;
break;
}
mame_printf_verbose("RTC: [%08x=%x] write %" I64FMT "x to %x, mask %" I64FMT "x\n", 0x710000 + reg*4, dat, data, offset, mem_mask);
@ -736,16 +715,15 @@ TIMER_CALLBACK_MEMBER(dc_state::dc_rtc_increment)
}
/* fill the RTC registers with the proper start-up values */
static void rtc_initial_setup(running_machine &machine)
{
dc_state *state = machine.driver_data<dc_state>();
void dc_state::rtc_initial_setup()
{
static UINT32 current_time;
static int year_count,cur_year,i;
static const int month_to_day_conversion[12] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 };
system_time systime;
machine.base_datetime(systime);
machine().base_datetime(systime);
memset(state->dc_rtcregister, 0, sizeof(state->dc_rtcregister));
memset(dc_rtcregister, 0, sizeof(dc_rtcregister));
/* put the seconds */
current_time = systime.local_time.second;
@ -770,15 +748,15 @@ static void rtc_initial_setup(running_machine &machine)
for(i=0;i<year_count-1;i++)
current_time += (((((i+1950) % 4) == 0) && (((i+1950) % 100) != 0)) || (((i+1950) % 400) == 0)) ? 60*60*24*366 : 60*60*24*365;
state->dc_rtcregister[RTC2] = current_time & 0x0000ffff;
state->dc_rtcregister[RTC1] = (current_time & 0xffff0000) >> 16;
dc_rtcregister[RTC2] = current_time & 0x0000ffff;
dc_rtcregister[RTC1] = (current_time & 0xffff0000) >> 16;
state->dc_rtc_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(dc_state::dc_rtc_increment),state));
dc_rtc_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(dc_state::dc_rtc_increment),this));
}
void dc_state::machine_start()
{
rtc_initial_setup(machine());
rtc_initial_setup();
// save states
state_save_register_global_pointer(machine(), dc_rtcregister, 4);
@ -825,7 +803,7 @@ READ64_MEMBER(dc_state::dc_aica_reg_r)
//int reg;
UINT64 shift;
/*reg = */decode_reg32_64(machine(), offset, mem_mask, &shift);
/*reg = */decode_reg32_64(offset, mem_mask, &shift);
// mame_printf_verbose("AICA REG: [%08x] read %" I64FMT "x, mask %" I64FMT "x\n", 0x700000+reg*4, (UINT64)offset, mem_mask);
@ -838,7 +816,7 @@ WRITE64_MEMBER(dc_state::dc_aica_reg_w)
UINT64 shift;
UINT32 dat;
reg = decode_reg32_64(machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
if (reg == (0x2c00/4))

85
src/mame/machine/naomi.c
View File

@ -23,10 +23,7 @@ hotd2o: bp 0xc0ba1f6, modify work RAM 0xc9c35a8 to be zero, bpclear
#include "includes/naomi.h"
#include "sound/aica.h"
int jvsboard_type;
UINT16 actel_id;
static READ64_HANDLER( naomi_biose_idle_skip_r )
READ64_MEMBER(naomi_state::naomi_biose_idle_skip_r )
{
if (space.device().safe_pc()==0xc04173c)
space.device().execute().spin_until_time(attotime::from_usec(500));
@ -34,20 +31,20 @@ static READ64_HANDLER( naomi_biose_idle_skip_r )
// else
// printf("%08x\n", space.device().safe_pc());
return space.machine().driver_data<naomi_state>()->dc_ram[0x2ad238/8];
return dc_ram[0x2ad238/8];
}
static READ64_HANDLER( naomi_biosh_idle_skip_r )
READ64_MEMBER(naomi_state::naomi_biosh_idle_skip_r )
{
if (space.device().safe_pc()==0xc045ffc)
space.device().execute().spin_until_time(attotime::from_usec(500));
// printf("%08x\n", space.device().safe_pc());
return space.machine().driver_data<naomi_state>()->dc_ram[0x2b0600/8];
return dc_ram[0x2b0600/8];
}
static READ64_HANDLER( naomi2_biose_idle_skip_r )
READ64_MEMBER(naomi_state::naomi2_biose_idle_skip_r )
{
if (space.device().safe_pc()==0xc04637c)
space.device().execute().spin_until_time(attotime::from_usec(500));
@ -55,10 +52,10 @@ static READ64_HANDLER( naomi2_biose_idle_skip_r )
// else
// printf("%08x\n", space.device().safe_pc());
return space.machine().driver_data<naomi_state>()->dc_ram[0x2b0600/8];
return dc_ram[0x2b0600/8];
}
static UINT8 asciihex_to_dec(UINT8 in)
UINT8 naomi_state::asciihex_to_dec(UINT8 in)
{
if (in>=0x30 && in<=0x39)
{
@ -85,12 +82,12 @@ static UINT8 asciihex_to_dec(UINT8 in)
}
// development helper function
static void create_pic_from_retdat(running_machine& machine)
void naomi_state::create_pic_from_retdat()
{
{
UINT8* hexregion = machine.root_device().memregion("pichex")->base();
UINT8* retregion = machine.root_device().memregion("picreturn")->base();
UINT8* newregion = machine.root_device().memregion("pic")->base();
UINT8* hexregion = memregion("pichex")->base();
UINT8* retregion = memregion("picreturn")->base();
UINT8* newregion = memregion("pic")->base();
int outcount = 0;
if (hexregion && retregion && newregion)
@ -171,7 +168,7 @@ static void create_pic_from_retdat(running_machine& machine)
{
FILE *fp;
char filename[256];
sprintf(filename,"picbin_%s", machine.system().name);
sprintf(filename,"picbin_%s", machine().system().name);
fp=fopen(filename, "w+b");
if (fp)
{
@ -193,111 +190,111 @@ static void create_pic_from_retdat(running_machine& machine)
DRIVER_INIT_MEMBER(naomi_state,naomi)
{
//machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2ad238, 0xc2ad23f, FUNC(naomi_biose_idle_skip_r)); // rev e bios
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2b0600, 0xc2b0607, FUNC(naomi_biosh_idle_skip_r)); // rev h bios
//machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2ad238, 0xc2ad23f, read64_delegate(FUNC(naomi_state::naomi_biose_idle_skip_r),this); // rev e bios
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2b0600, 0xc2b0607, read64_delegate(FUNC(naomi_state::naomi_biosh_idle_skip_r),this)); // rev h bios
jvsboard_type = JVSBD_DEFAULT;
actel_id = 0xffff;
create_pic_from_retdat(machine());
create_pic_from_retdat();
}
DRIVER_INIT_MEMBER(naomi_state,naomi2)
{
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2b0600, 0xc2b0607, FUNC(naomi2_biose_idle_skip_r)); // rev e bios
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2b0600, 0xc2b0607, read64_delegate(FUNC(naomi_state::naomi2_biose_idle_skip_r),this)); // rev e bios
jvsboard_type = JVSBD_DEFAULT;
actel_id = 0xffff;
create_pic_from_retdat(machine());
create_pic_from_retdat();
}
DRIVER_INIT_MEMBER(naomi_state,naomi_mp)
{
//machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2ad238, 0xc2ad23f, FUNC(naomi_biose_idle_skip_r)); // rev e bios
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2b0600, 0xc2b0607, FUNC(naomi_biosh_idle_skip_r)); // rev h bios
//machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2ad238, 0xc2ad23f, read64_delegate(FUNC(naomi_state::naomi_biose_idle_skip_r),this); // rev e bios
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2b0600, 0xc2b0607, read64_delegate(FUNC(naomi_state::naomi_biosh_idle_skip_r),this)); // rev h bios
jvsboard_type = JVSBD_MAHJONG;
actel_id = 0xffff;
create_pic_from_retdat(machine());
create_pic_from_retdat();
}
DRIVER_INIT_MEMBER(naomi_state,naomigd)
{
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2ad238, 0xc2ad23f, FUNC(naomi_biose_idle_skip_r)); // rev e bios
//machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2b0600, 0xc2b0607, FUNC(naomi_biosh_idle_skip_r)); // rev h bios
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2ad238, 0xc2ad23f, read64_delegate(FUNC(naomi_state::naomi_biose_idle_skip_r),this)); // rev e bios
//machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2b0600, 0xc2b0607, read64_delegate(FUNC(naomi_state::naomi_biosh_idle_skip_r),this)); // rev h bios
jvsboard_type = JVSBD_DEFAULT;
actel_id = 0xffff;
create_pic_from_retdat(machine());
create_pic_from_retdat();
}
DRIVER_INIT_MEMBER(naomi_state,naomigd_mp)
{
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2ad238, 0xc2ad23f, FUNC(naomi_biose_idle_skip_r)); // rev e bios
//machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2b0600, 0xc2b0607, FUNC(naomi_biosh_idle_skip_r)); // rev h bios
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2ad238, 0xc2ad23f, read64_delegate(FUNC(naomi_state::naomi_biose_idle_skip_r),this)); // rev e bios
//machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2b0600, 0xc2b0607, read64_delegate(FUNC(naomi_state::naomi_biosh_idle_skip_r),this)); // rev h bios
jvsboard_type = JVSBD_MAHJONG;
actel_id = 0xffff;
create_pic_from_retdat(machine());
create_pic_from_retdat();
}
static READ64_HANDLER( naomigd_ggxxsla_idle_skip_r )
READ64_MEMBER(naomi_state::naomigd_ggxxsla_idle_skip_r )
{
if (space.device().safe_pc()==0x0c0c9adc)
space.device().execute().spin_until_time(attotime::from_usec(500));
return space.machine().driver_data<naomi_state>()->dc_ram[0x1aae18/8];
return dc_ram[0x1aae18/8];
}
DRIVER_INIT_MEMBER(naomi_state,ggxxsla)
{
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc1aae18, 0xc1aae1f, FUNC(naomigd_ggxxsla_idle_skip_r));
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc1aae18, 0xc1aae1f, read64_delegate(FUNC(naomi_state::naomigd_ggxxsla_idle_skip_r),this));
DRIVER_INIT_CALL(naomigd);
}
static READ64_HANDLER( naomigd_ggxx_idle_skip_r )
READ64_MEMBER(naomi_state::naomigd_ggxx_idle_skip_r )
{
if (space.device().safe_pc()==0xc0b5c3c) // or 0xc0bab0c
space.device().execute().spin_until_time(attotime::from_usec(500));
return space.machine().driver_data<naomi_state>()->dc_ram[0x1837b8/8];
return dc_ram[0x1837b8/8];
}
DRIVER_INIT_MEMBER(naomi_state,ggxx)
{
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc1837b8, 0xc1837bf, FUNC(naomigd_ggxx_idle_skip_r));
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc1837b8, 0xc1837bf, read64_delegate(FUNC(naomi_state::naomigd_ggxx_idle_skip_r),this));
DRIVER_INIT_CALL(naomigd);
}
static READ64_HANDLER( naomigd_ggxxrl_idle_skip_r )
READ64_MEMBER(naomi_state::naomigd_ggxxrl_idle_skip_r )
{
if (space.device().safe_pc()==0xc0b84bc) // or 0xc0bab0c
space.device().execute().spin_until_time(attotime::from_usec(500));
//printf("%08x\n", space.device().safe_pc());
return space.machine().driver_data<naomi_state>()->dc_ram[0x18d6c8/8];
return dc_ram[0x18d6c8/8];
}
DRIVER_INIT_MEMBER(naomi_state,ggxxrl)
{
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc18d6c8, 0xc18d6cf, FUNC(naomigd_ggxxrl_idle_skip_r));
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc18d6c8, 0xc18d6cf, read64_delegate(FUNC(naomi_state::naomigd_ggxxrl_idle_skip_r),this));
DRIVER_INIT_CALL(naomigd);
}
/* at least speeds up the annoying copyright screens ;-) */
static READ64_HANDLER( naomigd_sfz3ugd_idle_skip_r )
READ64_MEMBER(naomi_state::naomigd_sfz3ugd_idle_skip_r )
{
if (space.device().safe_pc()==0xc36a2dc)
space.device().execute().spin_until_time(attotime::from_usec(500));
return space.machine().driver_data<naomi_state>()->dc_ram[0x5dc900/8];
return dc_ram[0x5dc900/8];
}
DRIVER_INIT_MEMBER(naomi_state,sfz3ugd)
{
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc5dc900, 0xc5dc907, FUNC(naomigd_sfz3ugd_idle_skip_r));
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc5dc900, 0xc5dc907, read64_delegate(FUNC(naomi_state::naomigd_sfz3ugd_idle_skip_r),this));
DRIVER_INIT_CALL(naomigd);
}
@ -332,7 +329,7 @@ DRIVER_INIT_MEMBER(naomi_state,kick4csh)
actel_id = 0; //FIXME: correct value
}
static READ64_HANDLER( hotd2_idle_skip_r )
READ64_MEMBER(naomi_state::hotd2_idle_skip_r )
{
if (space.device().safe_pc()==0xc0cfcbc)
space.device().execute().spin_until_time(attotime::from_usec(500));
@ -340,12 +337,12 @@ static READ64_HANDLER( hotd2_idle_skip_r )
// else
// printf("%08x\n", space.device().safe_pc());
return space.machine().driver_data<naomi_state>()->dc_ram[0xa25fb8/8];
return dc_ram[0xa25fb8/8];
}
DRIVER_INIT_MEMBER(naomi_state,hotd2)
{
machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xca25fb8, 0xca25fbf, FUNC(hotd2_idle_skip_r));
machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xca25fb8, 0xca25fbf, read64_delegate(FUNC(naomi_state::hotd2_idle_skip_r),this));
}
// f355 PC=0xc065f7c RAM=0xc26dafc

24
src/mame/video/dc.c
View File

@ -1293,31 +1293,31 @@ WRITE64_HANDLER( pvr_ta_w )
TIMER_CALLBACK_MEMBER(dc_state::transfer_opaque_list_irq)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_OPLST;
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
TIMER_CALLBACK_MEMBER(dc_state::transfer_opaque_modifier_volume_list_irq)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_OPMV;
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
TIMER_CALLBACK_MEMBER(dc_state::transfer_translucent_list_irq)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_TRLST;
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
TIMER_CALLBACK_MEMBER(dc_state::transfer_translucent_modifier_volume_list_irq)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_TRMV;
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
TIMER_CALLBACK_MEMBER(dc_state::transfer_punch_through_list_irq)
{
dc_sysctrl_regs[SB_ISTNRM] |= (1 << 21);
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
static void process_ta_fifo(running_machine& machine)
@ -2489,7 +2489,7 @@ TIMER_CALLBACK_MEMBER(dc_state::vbin)
dc_state *state = machine().driver_data<dc_state>();
dc_sysctrl_regs[SB_ISTNRM] |= IST_VBL_IN; // V Blank-in interrupt
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
vbin_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_in_irq_line_num));
}
@ -2499,7 +2499,7 @@ TIMER_CALLBACK_MEMBER(dc_state::vbout)
dc_state *state = machine().driver_data<dc_state>();
dc_sysctrl_regs[SB_ISTNRM] |= IST_VBL_OUT; // V Blank-out interrupt
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
vbout_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_out_irq_line_num));
}
@ -2513,14 +2513,14 @@ TIMER_CALLBACK_MEMBER(dc_state::hbin)
if(scanline == next_y)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_HBL_IN; // H Blank-in interrupt
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
next_y+=spg_line_comp_val;
}
}
else if((scanline == spg_line_comp_val) || (spg_hblank_int_mode & 2))
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_HBL_IN; // H Blank-in interrupt
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
}
// printf("hbin on scanline %d\n",scanline);
@ -2541,14 +2541,14 @@ TIMER_CALLBACK_MEMBER(dc_state::hbin)
TIMER_CALLBACK_MEMBER(dc_state::endofrender_video)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_VIDEO;// VIDEO end of render
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
endofrender_timer_video->adjust(attotime::never);
}
TIMER_CALLBACK_MEMBER(dc_state::endofrender_tsp)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_TSP; // TSP end of render
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
endofrender_timer_tsp->adjust(attotime::never);
endofrender_timer_video->adjust(attotime::from_usec(500) );
@ -2557,7 +2557,7 @@ TIMER_CALLBACK_MEMBER(dc_state::endofrender_tsp)
TIMER_CALLBACK_MEMBER(dc_state::endofrender_isp)
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_ISP; // ISP end of render
dc_update_interrupt_status(machine());
dc_update_interrupt_status();
endofrender_timer_isp->adjust(attotime::never);
endofrender_timer_tsp->adjust(attotime::from_usec(500) );

26
src/mess/drivers/dccons.c
View File

@ -33,14 +33,6 @@
#define CPU_CLOCK (200000000)
// things from mess/machine/dc.c
void dreamcast_atapi_init(running_machine &machine);
void dreamcast_atapi_reset(running_machine &machine);
extern DECLARE_READ64_HANDLER( dc_mess_gdrom_r );
extern DECLARE_WRITE64_HANDLER( dc_mess_gdrom_w );
extern DECLARE_READ64_HANDLER( dc_mess_g1_ctrl_r );
extern DECLARE_WRITE64_HANDLER( dc_mess_g1_ctrl_w );
READ64_MEMBER(dc_cons_state::dcus_idle_skip_r )
{
if (space.device().safe_pc()==0xc0ba52a)
@ -61,7 +53,7 @@ READ64_MEMBER(dc_cons_state::dcjp_idle_skip_r )
DRIVER_INIT_MEMBER(dc_cons_state,dc)
{
dreamcast_atapi_init(machine());
dreamcast_atapi_init();
}
DRIVER_INIT_MEMBER(dc_cons_state,dcus)
@ -152,16 +144,16 @@ WRITE64_MEMBER(dc_cons_state::ta_texture_directpath1_w )
static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
AM_RANGE(0x00000000, 0x001fffff) AM_ROM AM_WRITENOP // BIOS
AM_RANGE(0x00200000, 0x0021ffff) AM_ROM AM_REGION("maincpu", 0x200000) // flash
AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6c00, 0x005f6cff) AM_DEVICE32( "maple_dc", maple_dc_device, amap, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE_LEGACY(dc_mess_gdrom_r, dc_mess_gdrom_w )
AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE_LEGACY(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w )
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE_LEGACY(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE_LEGACY(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE(dc_mess_gdrom_r, dc_mess_gdrom_w )
AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w )
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
AM_RANGE(0x005f8000, 0x005f9fff) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE_LEGACY(dc_modem_r, dc_modem_w )
AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(dc_modem_r, dc_modem_w )
AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE_LEGACY(dc_rtc_r, dc_rtc_w )
AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )
AM_RANGE(0x00800000, 0x009fffff) AM_READWRITE(dc_arm_r, dc_arm_w )
/* Area 1 */
@ -202,7 +194,7 @@ MACHINE_RESET_MEMBER(dc_cons_state,dc_console)
device_t *aica = machine().device("aica");
dc_state::machine_reset();
aica_set_ram_base(aica, dc_sound_ram, 2*1024*1024);
dreamcast_atapi_reset(machine());
dreamcast_atapi_reset();
}
WRITE_LINE_MEMBER(dc_cons_state::aica_irq)

24
src/mess/includes/dccons.h
View File

@ -1,3 +1,6 @@
#include "imagedev/chd_cd.h"
#include "machine/gdrom.h"
class dc_cons_state : public dc_state
{
public:
@ -20,7 +23,26 @@ public:
DECLARE_WRITE64_MEMBER(ta_texture_directpath0_w);
DECLARE_WRITE64_MEMBER(ta_texture_directpath1_w);
DECLARE_WRITE_LINE_MEMBER(aica_irq);
void gdrom_raise_irq();
TIMER_CALLBACK_MEMBER( atapi_xfer_end );
READ32_MEMBER( atapi_r );
WRITE32_MEMBER( atapi_w );
void dreamcast_atapi_init();
void dreamcast_atapi_reset();
inline int decode_reg32_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift);
READ64_MEMBER( dc_mess_gdrom_r );
WRITE64_MEMBER( dc_mess_gdrom_w );
READ64_MEMBER( dc_mess_g1_ctrl_r );
WRITE64_MEMBER( dc_mess_g1_ctrl_w );
private:
UINT64 PDTRA, PCTRA;
UINT8 *atapi_regs;
emu_timer *atapi_timer;
gdrom_device *gdrom;
UINT8 *atapi_data;
int atapi_data_ptr, atapi_data_len, atapi_xferlen, atapi_xferbase, atapi_cdata_wait, atapi_xfermod;
UINT32 gdrom_alt_status;
UINT8 xfer_mode;
};

115
src/mess/machine/dccons.c
View File

@ -19,9 +19,7 @@
#include "includes/dc.h"
#include "cpu/sh4/sh4.h"
#include "sound/aica.h"
#include "includes/naomi.h"
#include "machine/gdrom.h"
#include "imagedev/chd_cd.h"
#include "includes/dccons.h"
#define ATAPI_CYCLES_PER_SECTOR (5000) // TBD for Dreamcast
@ -56,27 +54,16 @@
#define ATAPI_DATA_SIZE ( 64 * 1024 )
static UINT8 *atapi_regs;
static emu_timer *atapi_timer;
static gdrom_device *gdrom;
static UINT8 *atapi_data;
static int atapi_data_ptr, atapi_data_len, atapi_xferlen, atapi_xferbase, atapi_cdata_wait, atapi_xfermod;
static UINT32 gdrom_alt_status;
static UINT8 xfer_mode = ATAPI_XFER_PIO;
#define MAX_TRANSFER_SIZE ( 63488 )
static void gdrom_raise_irq(running_machine &machine)
void dc_cons_state::gdrom_raise_irq()
{
dc_state *state = machine.driver_data<dc_state>();
state->dc_sysctrl_regs[SB_ISTEXT] |= IST_EXT_GDROM;
dc_update_interrupt_status(machine);
dc_sysctrl_regs[SB_ISTEXT] |= IST_EXT_GDROM;
dc_update_interrupt_status();
}
static TIMER_CALLBACK( atapi_xfer_end )
TIMER_CALLBACK_MEMBER(dc_cons_state::atapi_xfer_end )
{
dc_state *state = machine.driver_data<dc_state>();
UINT8 sector_buffer[ 4096 ];
@ -104,7 +91,7 @@ static TIMER_CALLBACK( atapi_xfer_end )
ddtdata.channel= -1; // not used
ddtdata.mode= -1; // copy from/to buffer
printf("ATAPI: DMA one sector to %x, %x remaining\n", atapi_xferbase, atapi_xferlen);
sh4_dma_ddt(machine.device("maincpu"), &ddtdata);
sh4_dma_ddt(machine().device("maincpu"), &ddtdata);
atapi_xferbase += 2048;
}
@ -126,7 +113,7 @@ static TIMER_CALLBACK( atapi_xfer_end )
atapi_regs[ATAPI_REG_COUNTLOW] = atapi_xferlen & 0xff;
atapi_regs[ATAPI_REG_COUNTHIGH] = (atapi_xferlen>>8)&0xff;
atapi_timer->adjust(machine.device<cpu_device>("maincpu")->cycles_to_attotime((ATAPI_CYCLES_PER_SECTOR * (atapi_xferlen/2048))));
atapi_timer->adjust(machine().device<cpu_device>("maincpu")->cycles_to_attotime((ATAPI_CYCLES_PER_SECTOR * (atapi_xferlen/2048))));
}
else
{
@ -135,19 +122,18 @@ static TIMER_CALLBACK( atapi_xfer_end )
gdrom_alt_status = ATAPI_STAT_DRDY;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO | ATAPI_INTREASON_COMMAND;
state->g1bus_regs[SB_GDST]=0;
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_GDROM;
dc_update_interrupt_status(machine);
g1bus_regs[SB_GDST]=0;
dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_GDROM;
dc_update_interrupt_status();
}
gdrom_raise_irq(machine);
gdrom_raise_irq();
printf( "atapi_xfer_end: %d %d\n", atapi_xferlen, atapi_xfermod );
}
static READ32_HANDLER( atapi_r )
READ32_MEMBER(dc_cons_state::atapi_r )
{
running_machine &machine = space.machine();
int reg, data;
if (mem_mask == 0x0000ffff) // word-wide command read
@ -193,7 +179,7 @@ static READ32_HANDLER( atapi_r )
atapi_regs[ATAPI_REG_COUNTLOW] = atapi_xferlen & 0xff;
atapi_regs[ATAPI_REG_COUNTHIGH] = (atapi_xferlen>>8)&0xff;
gdrom_raise_irq(machine);
gdrom_raise_irq();
}
if( atapi_data_ptr < atapi_data_len )
@ -211,7 +197,7 @@ static READ32_HANDLER( atapi_r )
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
gdrom_alt_status = 0;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
gdrom_raise_irq(machine);
gdrom_raise_irq();
}
}
}
@ -268,9 +254,8 @@ static READ32_HANDLER( atapi_r )
return data;
}
static WRITE32_HANDLER( atapi_w )
WRITE32_MEMBER(dc_cons_state::atapi_w )
{
running_machine &machine = space.machine();
int reg;
// printf( "atapi_w( %08x, %08x, %08x )\n", offset, mem_mask, data );
@ -292,7 +277,7 @@ static WRITE32_HANDLER( atapi_w )
gdrom->WriteData( atapi_data, atapi_cdata_wait );
// assert IRQ
gdrom_raise_irq(machine);
gdrom_raise_irq();
// not sure here, but clear DRQ at least?
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
@ -374,7 +359,7 @@ static WRITE32_HANDLER( atapi_w )
}
// assert IRQ
gdrom_raise_irq(machine);
gdrom_raise_irq();
}
else
{
@ -491,7 +476,7 @@ static WRITE32_HANDLER( atapi_w )
atapi_regs[ATAPI_REG_COUNTLOW] = 0;
atapi_regs[ATAPI_REG_COUNTHIGH] = 2;
gdrom_raise_irq(space.machine());
gdrom_raise_irq();
break;
case 0xef: // SET FEATURES
@ -512,7 +497,7 @@ static WRITE32_HANDLER( atapi_w )
atapi_data_ptr = 0;
atapi_data_len = 0;
gdrom_raise_irq(space.machine());
gdrom_raise_irq();
break;
default:
@ -523,9 +508,11 @@ static WRITE32_HANDLER( atapi_w )
}
}
void dreamcast_atapi_init(running_machine &machine)
void dc_cons_state::dreamcast_atapi_init()
{
atapi_regs = auto_alloc_array_clear(machine, UINT8, ATAPI_REG_MAX);
xfer_mode = ATAPI_XFER_PIO;
atapi_regs = auto_alloc_array_clear(machine(), UINT8, ATAPI_REG_MAX);
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
atapi_regs[ATAPI_REG_ERROR] = 1;
@ -536,26 +523,26 @@ void dreamcast_atapi_init(running_machine &machine)
atapi_data_len = 0;
atapi_cdata_wait = 0;
atapi_timer = machine.scheduler().timer_alloc(FUNC(atapi_xfer_end));
atapi_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(dc_cons_state::atapi_xfer_end),this));
atapi_timer->adjust(attotime::never);
gdrom = NULL;
atapi_data = auto_alloc_array(machine, UINT8, ATAPI_DATA_SIZE );
atapi_data = auto_alloc_array(machine(), UINT8, ATAPI_DATA_SIZE );
state_save_register_global_pointer(machine, atapi_regs, ATAPI_REG_MAX );
state_save_register_global_pointer(machine, atapi_data, ATAPI_DATA_SIZE / 2 );
state_save_register_global(machine, atapi_data_ptr );
state_save_register_global(machine, atapi_data_len );
state_save_register_global(machine, atapi_xferlen );
state_save_register_global(machine, atapi_xferbase );
state_save_register_global(machine, atapi_cdata_wait );
state_save_register_global(machine, atapi_xfermod );
state_save_register_global_pointer(machine(), atapi_regs, ATAPI_REG_MAX );
state_save_register_global_pointer(machine(), atapi_data, ATAPI_DATA_SIZE / 2 );
state_save_register_global(machine(), atapi_data_ptr );
state_save_register_global(machine(), atapi_data_len );
state_save_register_global(machine(), atapi_xferlen );
state_save_register_global(machine(), atapi_xferbase );
state_save_register_global(machine(), atapi_cdata_wait );
state_save_register_global(machine(), atapi_xfermod );
gdrom = machine.device<gdrom_device>( "cdrom" );
gdrom = machine().device<gdrom_device>( "cdrom" );
}
void dreamcast_atapi_reset(running_machine &machine)
void dc_cons_state::dreamcast_atapi_reset()
{
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
atapi_regs[ATAPI_REG_ERROR] = 1;
@ -590,7 +577,7 @@ c000776 - DMA triggered to c008000
*/
READ64_HANDLER( dc_mess_gdrom_r )
READ64_MEMBER(dc_cons_state::dc_mess_gdrom_r )
{
UINT32 off;
@ -617,7 +604,7 @@ READ64_HANDLER( dc_mess_gdrom_r )
return 0;
}
WRITE64_HANDLER( dc_mess_gdrom_w )
WRITE64_MEMBER(dc_cons_state::dc_mess_gdrom_w )
{
UINT32 dat,off;
@ -643,7 +630,7 @@ WRITE64_HANDLER( dc_mess_gdrom_w )
// register decode helpers
// this accepts only 32-bit accesses
INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_mask, UINT64 *shift)
int dc_cons_state::decode_reg32_64( UINT32 offset, UINT64 mem_mask, UINT64 *shift)
{
int reg = offset * 2;
@ -652,7 +639,7 @@ INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_m
// non 32-bit accesses have not yet been seen here, we need to know when they are
if ((mem_mask != U64(0xffffffff00000000)) && (mem_mask != U64(0x00000000ffffffff)))
{
mame_printf_verbose("%s:Wrong mask!\n", machine.describe_context());
mame_printf_verbose("%s:Wrong mask!\n", machine().describe_context());
// debugger_break(machine);
}
@ -665,43 +652,41 @@ INLINE int decode_reg32_64(running_machine &machine, UINT32 offset, UINT64 mem_m
return reg;
}
READ64_HANDLER( dc_mess_g1_ctrl_r )
READ64_MEMBER(dc_cons_state::dc_mess_g1_ctrl_r )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
mame_printf_verbose("G1CTRL: Unmapped read %08x\n", 0x5f7400+reg*4);
return (UINT64)state->g1bus_regs[reg] << shift;
return (UINT64)g1bus_regs[reg] << shift;
}
WRITE64_HANDLER( dc_mess_g1_ctrl_w )
WRITE64_MEMBER(dc_cons_state::dc_mess_g1_ctrl_w )
{
dc_state *state = space.machine().driver_data<dc_state>();
int reg;
UINT64 shift;
UINT32 dat; //, old
reg = decode_reg32_64(space.machine(), offset, mem_mask, &shift);
reg = decode_reg32_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
// old = state->g1bus_regs[reg];
// old = g1bus_regs[reg];
state->g1bus_regs[reg] = dat; // 5f7400+reg*4=dat
g1bus_regs[reg] = dat; // 5f7400+reg*4=dat
mame_printf_verbose("G1CTRL: [%08x=%x] write %" I64FMT "x to %x, mask %" I64FMT "x\n", 0x5f7400+reg*4, dat, data, offset, mem_mask);
switch (reg)
{
case SB_GDST:
if (dat & 1 && state->g1bus_regs[SB_GDEN] == 1) // 0 -> 1
if (dat & 1 && g1bus_regs[SB_GDEN] == 1) // 0 -> 1
{
if (state->g1bus_regs[SB_GDDIR] == 0)
if (g1bus_regs[SB_GDDIR] == 0)
{
printf("G1CTRL: unsupported transfer\n");
return;
}
atapi_xferbase = state->g1bus_regs[SB_GDSTAR];
atapi_timer->adjust(space.machine().device<cpu_device>("maincpu")->cycles_to_attotime((ATAPI_CYCLES_PER_SECTOR * (atapi_xferlen/2048))));
atapi_xferbase = g1bus_regs[SB_GDSTAR];
atapi_timer->adjust(machine().device<cpu_device>("maincpu")->cycles_to_attotime((ATAPI_CYCLES_PER_SECTOR * (atapi_xferlen/2048))));
}
break;
}