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https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
sh2.cpp: first pass over SH7604 SoC refactoring [Angelo Salese]
* Fixed division unit overflow flag clearance;
This commit is contained in:
Angelo Salese
parent
fb50043856
commit
d6b22fa2c0
@ -123,15 +123,94 @@ READ32_MEMBER(sh2_device::sh2_internal_a5)
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sh2_internal_map - maps SH2 built-ins
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-------------------------------------------------*/
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void sh2_device::sh7604_map(address_map &map)
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{
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map(0x40000000, 0xbfffffff).r(FUNC(sh2_device::sh2_internal_a5));
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/*!
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@todo: cps3boot breaks with this enabled. Needs customization ...
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*/
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// TODO: cps3boot breaks with this enabled. Needs callback
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// AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM // cache data array
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// AM_RANGE(0xffffff88, 0xffffff8b) AM_READWRITE(dma_dtcr0_r,dma_dtcr0_w)
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map(0xe0000000, 0xe00001ff).mirror(0x1ffffe00).rw(FUNC(sh2_device::sh7604_r), FUNC(sh2_device::sh7604_w));
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// map(0xe0000000, 0xe00001ff).mirror(0x1ffffe00).rw(FUNC(sh2_device::sh7604_r), FUNC(sh2_device::sh7604_w));
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// TODO: internal map takes way too much resources if mirrored with 0x1ffffe00
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// we eventually internalize again via trampoline & sh7604_device
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// additionally SH7604 doc mentions that there's a DRAM located at 0xffff8000,
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// so this is not a full mirror? (needs confirmation)
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// SCI
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map(0xfffffe00, 0xfffffe00).rw(FUNC(sh2_device::smr_r), FUNC(sh2_device::smr_w));
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map(0xfffffe01, 0xfffffe01).rw(FUNC(sh2_device::brr_r), FUNC(sh2_device::brr_w));
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map(0xfffffe02, 0xfffffe02).rw(FUNC(sh2_device::scr_r), FUNC(sh2_device::scr_w));
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map(0xfffffe03, 0xfffffe03).rw(FUNC(sh2_device::tdr_r), FUNC(sh2_device::tdr_w));
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map(0xfffffe04, 0xfffffe04).rw(FUNC(sh2_device::ssr_r), FUNC(sh2_device::ssr_w));
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map(0xfffffe05, 0xfffffe05).r(FUNC(sh2_device::rdr_r));
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// FRC
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map(0xfffffe10, 0xfffffe10).rw(FUNC(sh2_device::tier_r), FUNC(sh2_device::tier_w));
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map(0xfffffe11, 0xfffffe11).rw(FUNC(sh2_device::ftcsr_r), FUNC(sh2_device::ftcsr_w));
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map(0xfffffe12, 0xfffffe13).rw(FUNC(sh2_device::frc_r), FUNC(sh2_device::frc_w));
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map(0xfffffe14, 0xfffffe15).rw(FUNC(sh2_device::ocra_b_r), FUNC(sh2_device::ocra_b_w));
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map(0xfffffe16, 0xfffffe16).rw(FUNC(sh2_device::frc_tcr_r), FUNC(sh2_device::frc_tcr_w));
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map(0xfffffe17, 0xfffffe17).rw(FUNC(sh2_device::tocr_r), FUNC(sh2_device::tocr_w));
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map(0xfffffe18, 0xfffffe19).r(FUNC(sh2_device::frc_icr_r));
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// INTC
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map(0xfffffe60, 0xfffffe61).rw(FUNC(sh2_device::iprb_r), FUNC(sh2_device::iprb_w));
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map(0xfffffe62, 0xfffffe63).rw(FUNC(sh2_device::vcra_r), FUNC(sh2_device::vcra_w));
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map(0xfffffe64, 0xfffffe65).rw(FUNC(sh2_device::vcrb_r), FUNC(sh2_device::vcrb_w));
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map(0xfffffe66, 0xfffffe67).rw(FUNC(sh2_device::vcrc_r), FUNC(sh2_device::vcrc_w));
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map(0xfffffe68, 0xfffffe69).rw(FUNC(sh2_device::vcrd_r), FUNC(sh2_device::vcrd_w));
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map(0xfffffe71, 0xfffffe71).rw(FUNC(sh2_device::drcr_r<0>), FUNC(sh2_device::drcr_w<0>));
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map(0xfffffe72, 0xfffffe72).rw(FUNC(sh2_device::drcr_r<1>), FUNC(sh2_device::drcr_w<1>));
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// WTC
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map(0xfffffe80, 0xfffffe81).rw(FUNC(sh2_device::wtcnt_r), FUNC(sh2_device::wtcnt_w));
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map(0xfffffe82, 0xfffffe83).rw(FUNC(sh2_device::rstcsr_r), FUNC(sh2_device::rstcsr_w));
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// standby and cache control
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map(0xfffffe91, 0xfffffe91).rw(FUNC(sh2_device::sbycr_r), FUNC(sh2_device::sbycr_w));
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map(0xfffffe92, 0xfffffe92).rw(FUNC(sh2_device::ccr_r), FUNC(sh2_device::ccr_w));
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// INTC second section
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map(0xfffffee0, 0xfffffee1).rw(FUNC(sh2_device::intc_icr_r), FUNC(sh2_device::intc_icr_w));
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map(0xfffffee2, 0xfffffee3).rw(FUNC(sh2_device::ipra_r), FUNC(sh2_device::ipra_w));
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map(0xfffffee4, 0xfffffee5).rw(FUNC(sh2_device::vcrwdt_r), FUNC(sh2_device::vcrwdt_w));
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// DIVU
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map(0xffffff00, 0xffffff03).rw(FUNC(sh2_device::dvsr_r), FUNC(sh2_device::dvsr_w));
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map(0xffffff04, 0xffffff07).rw(FUNC(sh2_device::dvdnt_r), FUNC(sh2_device::dvdnt_w));
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map(0xffffff08, 0xffffff0b).rw(FUNC(sh2_device::dvcr_r), FUNC(sh2_device::dvcr_w));
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// INTC third section
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map(0xffffff0c, 0xffffff0f).rw(FUNC(sh2_device::vcrdiv_r), FUNC(sh2_device::vcrdiv_w));
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// DIVU continued (64-bit plus mirrors)
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map(0xffffff10, 0xffffff13).rw(FUNC(sh2_device::dvdnth_r), FUNC(sh2_device::dvdnth_w));
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map(0xffffff14, 0xffffff17).rw(FUNC(sh2_device::dvdntl_r), FUNC(sh2_device::dvdntl_w));
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map(0xffffff18, 0xffffff1b).r(FUNC(sh2_device::dvdnth_r));
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map(0xffffff1c, 0xffffff1f).r(FUNC(sh2_device::dvdntl_r));
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// DMAC
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map(0xffffff80, 0xffffff83).rw(FUNC(sh2_device::sar_r<0>), FUNC(sh2_device::sar_w<0>));
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map(0xffffff84, 0xffffff87).rw(FUNC(sh2_device::dar_r<0>), FUNC(sh2_device::dar_w<0>));
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map(0xffffff88, 0xffffff8b).rw(FUNC(sh2_device::dmac_tcr_r<0>), FUNC(sh2_device::dmac_tcr_w<0>));
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map(0xffffff8c, 0xffffff8f).rw(FUNC(sh2_device::chcr_r<0>), FUNC(sh2_device::chcr_w<0>));
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map(0xffffff90, 0xffffff93).rw(FUNC(sh2_device::sar_r<1>), FUNC(sh2_device::sar_w<1>));
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map(0xffffff94, 0xffffff97).rw(FUNC(sh2_device::dar_r<1>), FUNC(sh2_device::dar_w<1>));
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map(0xffffff98, 0xffffff9b).rw(FUNC(sh2_device::dmac_tcr_r<1>), FUNC(sh2_device::dmac_tcr_w<1>));
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map(0xffffff9c, 0xffffff9f).rw(FUNC(sh2_device::chcr_r<1>), FUNC(sh2_device::chcr_w<1>));
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map(0xffffffa0, 0xffffffa3).rw(FUNC(sh2_device::vcrdma_r<0>), FUNC(sh2_device::vcrdma_w<0>));
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map(0xffffffa8, 0xffffffab).rw(FUNC(sh2_device::vcrdma_r<1>), FUNC(sh2_device::vcrdma_w<1>));
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map(0xffffffb0, 0xffffffb3).rw(FUNC(sh2_device::dmaor_r), FUNC(sh2_device::dmaor_w));
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// BSC
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map(0xffffffe0, 0xffffffe3).rw(FUNC(sh2_device::bcr1_r), FUNC(sh2_device::bcr1_w));
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map(0xffffffe4, 0xffffffe7).rw(FUNC(sh2_device::bcr2_r), FUNC(sh2_device::bcr2_w));
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map(0xffffffe8, 0xffffffeb).rw(FUNC(sh2_device::wcr_r), FUNC(sh2_device::wcr_w));
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map(0xffffffec, 0xffffffef).rw(FUNC(sh2_device::mcr_r), FUNC(sh2_device::mcr_w));
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map(0xfffffff0, 0xfffffff3).rw(FUNC(sh2_device::rtcsr_r), FUNC(sh2_device::rtcsr_w));
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map(0xfffffff4, 0xfffffff7).rw(FUNC(sh2_device::rtcnt_r), FUNC(sh2_device::rtcnt_w));
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map(0xfffffff8, 0xfffffffb).rw(FUNC(sh2_device::rtcor_r), FUNC(sh2_device::rtcor_w));
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}
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void sh2a_device::sh7021_map(address_map &map)
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@ -364,14 +443,12 @@ void sh2_device::device_reset()
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m_sh2_state->pending_irq = m_test_irq = 0;
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//memset(&m_irq_queue[0], 0, sizeof(m_irq_queue[0])*16);
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memset(&m_irq_line_state[0], 0, sizeof(m_irq_line_state[0])*17);
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m_frc = m_ocra = m_ocrb = m_icr = 0;
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m_frc = m_ocra = m_ocrb = m_frc_icr = 0;
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m_frc_base = 0;
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m_frt_input = m_sh2_state->internal_irq_level = m_internal_irq_vector = 0;
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m_dma_timer_active[0] = m_dma_timer_active[1] = 0;
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m_dma_irq[0] = m_dma_irq[1] = 0;
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memset(m_m, 0, 0x200);
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m_sh2_state->pc = RL(0);
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m_sh2_state->r[15] = RL(4);
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m_sh2_state->sr = SH_I;
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@ -467,13 +544,93 @@ void sh2_device::device_start()
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m_internal = &space(AS_PROGRAM);
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save_item(NAME(m_cpu_off));
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//save_item(NAME(m_dvsr));
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//save_item(NAME(m_dvdnth));
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//save_item(NAME(m_dvdntl));
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//save_item(NAME(m_dvcr));
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save_item(NAME(m_test_irq));
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// SCI
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save_item(NAME(m_smr));
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save_item(NAME(m_brr));
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save_item(NAME(m_scr));
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save_item(NAME(m_tdr));
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save_item(NAME(m_ssr));
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// FRT / FRC
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save_item(NAME(m_tier));
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save_item(NAME(m_ftcsr));
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save_item(NAME(m_frc_tcr));
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save_item(NAME(m_tocr));
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save_item(NAME(m_frc));
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save_item(NAME(m_ocra));
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save_item(NAME(m_ocrb));
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save_item(NAME(m_frc_icr));
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save_item(NAME(m_frc_base));
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save_item(NAME(m_frt_input));
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// INTC
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save_item(NAME(m_irq_level.frc));
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save_item(NAME(m_irq_level.sci));
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save_item(NAME(m_irq_level.divu));
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save_item(NAME(m_irq_level.dmac));
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save_item(NAME(m_irq_level.wdt));
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save_item(NAME(m_irq_vector.fic));
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save_item(NAME(m_irq_vector.foc));
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save_item(NAME(m_irq_vector.fov));
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save_item(NAME(m_irq_vector.divu));
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save_item(NAME(m_irq_vector.dmac[0]));
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save_item(NAME(m_irq_vector.dmac[1]));
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save_item(NAME(m_ipra));
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save_item(NAME(m_iprb));
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save_item(NAME(m_vcra));
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save_item(NAME(m_vcrb));
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save_item(NAME(m_vcrc));
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save_item(NAME(m_vcrd));
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save_item(NAME(m_vcrwdt));
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save_item(NAME(m_vcrdiv));
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save_item(NAME(m_intc_icr));
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save_item(NAME(m_vcrdma[0]));
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save_item(NAME(m_vcrdma[1]));
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save_item(NAME(m_vecmd));
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save_item(NAME(m_nmie));
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// DIVU
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save_item(NAME(m_divu_ovf));
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save_item(NAME(m_divu_ovfie));
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save_item(NAME(m_dvsr));
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save_item(NAME(m_dvdntl));
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save_item(NAME(m_dvdnth));
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// WTC
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save_item(NAME(m_wtcnt));
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save_item(NAME(m_wtcsr));
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save_item(NAME(m_rstcsr));
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save_item(NAME(m_wtcw[0]));
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save_item(NAME(m_wtcw[1]));
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// DMAC
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save_item(NAME(m_dmaor));
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save_item(NAME(m_dmac[0].drcr));
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save_item(NAME(m_dmac[1].drcr));
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save_item(NAME(m_dmac[0].sar));
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save_item(NAME(m_dmac[1].sar));
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save_item(NAME(m_dmac[0].dar));
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save_item(NAME(m_dmac[1].dar));
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save_item(NAME(m_dmac[0].tcr));
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save_item(NAME(m_dmac[1].tcr));
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save_item(NAME(m_dmac[0].chcr));
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save_item(NAME(m_dmac[1].chcr));
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// misc
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save_item(NAME(m_sbycr));
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save_item(NAME(m_ccr));
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// BSC
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save_item(NAME(m_bcr1));
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save_item(NAME(m_bcr2));
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save_item(NAME(m_wcr));
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save_item(NAME(m_mcr));
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save_item(NAME(m_rtcsr));
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save_item(NAME(m_rtcor));
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save_item(NAME(m_rtcnt));
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/*
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for (int i = 0; i < 16; ++i)
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{
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@ -482,22 +639,15 @@ void sh2_device::device_start()
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}
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*/
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// internals
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save_item(NAME(m_cpu_off));
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save_item(NAME(m_test_irq));
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save_item(NAME(m_irq_line_state));
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save_item(NAME(m_m));
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save_item(NAME(m_nmi_line_state));
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save_item(NAME(m_frc));
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save_item(NAME(m_ocra));
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save_item(NAME(m_ocrb));
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save_item(NAME(m_icr));
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save_item(NAME(m_frc_base));
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save_item(NAME(m_frt_input));
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save_item(NAME(m_internal_irq_vector));
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save_item(NAME(m_dma_timer_active));
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save_item(NAME(m_dma_irq));
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save_item(NAME(m_wtcnt));
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save_item(NAME(m_wtcsr));
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state_add( STATE_GENPC, "PC", m_sh2_state->pc).mask(SH12_AM).callimport();
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state_add( STATE_GENPCBASE, "CURPC", m_sh2_state->pc ).callimport().noshow();
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@ -509,14 +659,13 @@ void sh2_device::device_start()
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//m_dvcr = 0;
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m_test_irq = 0;
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memset(m_irq_line_state, 0, sizeof(m_irq_line_state));
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memset(m_m, 0, sizeof(m_m));
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m_nmi_line_state = 0;
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m_frc = 0;
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m_ocra = 0;
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m_ocrb = 0;
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m_icr = 0;
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m_frc_icr = 0;
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m_frc_base = 0;
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m_frt_input = 0;
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m_internal_irq_vector = 0;
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@ -641,7 +790,7 @@ void sh2_device::sh2_exception(const char *message, int irqline)
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}
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else
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{
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if(m_m[0x38] & 0x00010000)
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if(m_vecmd == true)
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{
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vector = standard_irq_callback(irqline);
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LOG("SH-2 exception #%d (external vector: $%x) after [%s]\n", irqline, vector, message);
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@ -81,10 +81,141 @@ public:
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}
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DECLARE_WRITE32_MEMBER( sh7604_w );
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DECLARE_READ32_MEMBER( sh7604_r );
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DECLARE_READ32_MEMBER(sh2_internal_a5);
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// SCI
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DECLARE_READ8_MEMBER( smr_r );
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DECLARE_WRITE8_MEMBER( smr_w );
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DECLARE_READ8_MEMBER( brr_r );
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DECLARE_WRITE8_MEMBER( brr_w );
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DECLARE_READ8_MEMBER( scr_r );
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DECLARE_WRITE8_MEMBER( scr_w );
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DECLARE_READ8_MEMBER( tdr_r );
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DECLARE_WRITE8_MEMBER( tdr_w );
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DECLARE_READ8_MEMBER( ssr_r );
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DECLARE_WRITE8_MEMBER( ssr_w );
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DECLARE_READ8_MEMBER( rdr_r );
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// FRT / FRC
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DECLARE_READ8_MEMBER( tier_r );
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DECLARE_WRITE8_MEMBER( tier_w );
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DECLARE_READ16_MEMBER( frc_r );
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DECLARE_WRITE16_MEMBER( frc_w );
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DECLARE_READ8_MEMBER( ftcsr_r );
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DECLARE_WRITE8_MEMBER( ftcsr_w );
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DECLARE_READ16_MEMBER( ocra_b_r );
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DECLARE_WRITE16_MEMBER( ocra_b_w );
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DECLARE_READ8_MEMBER( frc_tcr_r );
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DECLARE_WRITE8_MEMBER( frc_tcr_w );
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DECLARE_READ8_MEMBER( tocr_r );
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DECLARE_WRITE8_MEMBER( tocr_w );
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DECLARE_READ16_MEMBER( frc_icr_r );
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// INTC
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DECLARE_READ16_MEMBER( ipra_r );
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DECLARE_WRITE16_MEMBER( ipra_w );
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DECLARE_READ16_MEMBER( iprb_r );
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DECLARE_WRITE16_MEMBER( iprb_w );
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DECLARE_READ16_MEMBER( vcra_r );
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DECLARE_WRITE16_MEMBER( vcra_w );
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DECLARE_READ16_MEMBER( vcrb_r );
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DECLARE_WRITE16_MEMBER( vcrb_w );
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DECLARE_READ16_MEMBER( vcrc_r );
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DECLARE_WRITE16_MEMBER( vcrc_w );
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DECLARE_READ16_MEMBER( vcrd_r );
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DECLARE_WRITE16_MEMBER( vcrd_w );
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DECLARE_READ16_MEMBER( vcrwdt_r );
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DECLARE_WRITE16_MEMBER( vcrwdt_w );
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DECLARE_READ32_MEMBER( vcrdiv_r );
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DECLARE_WRITE32_MEMBER( vcrdiv_w );
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DECLARE_READ16_MEMBER( intc_icr_r );
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DECLARE_WRITE16_MEMBER( intc_icr_w );
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// DIVU
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DECLARE_READ32_MEMBER( dvsr_r );
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DECLARE_WRITE32_MEMBER( dvsr_w );
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DECLARE_READ32_MEMBER( dvdnt_r );
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DECLARE_WRITE32_MEMBER( dvdnt_w );
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DECLARE_READ32_MEMBER( dvdnth_r );
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DECLARE_WRITE32_MEMBER( dvdnth_w );
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||||
DECLARE_READ32_MEMBER( dvdntl_r );
|
||||
DECLARE_WRITE32_MEMBER( dvdntl_w );
|
||||
|
||||
DECLARE_READ32_MEMBER( dvcr_r );
|
||||
DECLARE_WRITE32_MEMBER( dvcr_w );
|
||||
|
||||
// DMAC
|
||||
template <int Channel> READ32_MEMBER(vcrdma_r)
|
||||
{
|
||||
return m_vcrdma[Channel] & 0x7f;
|
||||
}
|
||||
|
||||
template <int Channel> WRITE32_MEMBER(vcrdma_w)
|
||||
{
|
||||
COMBINE_DATA(&m_vcrdma[Channel]);
|
||||
m_irq_vector.dmac[Channel] = m_vcrdma[Channel] & 0x7f;
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
template <int Channel> READ8_MEMBER(drcr_r) { return m_dmac[Channel].drcr & 3; }
|
||||
template <int Channel> WRITE8_MEMBER(drcr_w) { m_dmac[Channel].drcr = data & 3; sh2_recalc_irq(); }
|
||||
template <int Channel> READ32_MEMBER(sar_r) { return m_dmac[Channel].sar; }
|
||||
template <int Channel> WRITE32_MEMBER(sar_w) { COMBINE_DATA(&m_dmac[Channel].sar); }
|
||||
template <int Channel> READ32_MEMBER(dar_r) { return m_dmac[Channel].dar; }
|
||||
template <int Channel> WRITE32_MEMBER(dar_w) { COMBINE_DATA(&m_dmac[Channel].dar); }
|
||||
template <int Channel> READ32_MEMBER(dmac_tcr_r) { return m_dmac[Channel].tcr; }
|
||||
template <int Channel> WRITE32_MEMBER(dmac_tcr_w) { COMBINE_DATA(&m_dmac[Channel].tcr); m_dmac[Channel].tcr &= 0xffffff; }
|
||||
template <int Channel> READ32_MEMBER(chcr_r) { return m_dmac[Channel].chcr; }
|
||||
template <int Channel> WRITE32_MEMBER(chcr_w)
|
||||
{
|
||||
uint32_t old;
|
||||
old = m_dmac[Channel].chcr;
|
||||
COMBINE_DATA(&m_dmac[Channel].chcr);
|
||||
m_dmac[Channel].chcr = (data & ~2) | (old & m_dmac[Channel].chcr & 2);
|
||||
sh2_dmac_check(Channel);
|
||||
}
|
||||
READ32_MEMBER( dmaor_r ) { return m_dmaor & 0xf; }
|
||||
WRITE32_MEMBER( dmaor_w )
|
||||
{
|
||||
if(ACCESSING_BITS_0_7)
|
||||
{
|
||||
uint8_t old;
|
||||
old = m_dmaor & 0xf;
|
||||
m_dmaor = (data & ~6) | (old & m_dmaor & 6);
|
||||
sh2_dmac_check(0);
|
||||
sh2_dmac_check(1);
|
||||
}
|
||||
}
|
||||
|
||||
// WTC
|
||||
DECLARE_READ16_MEMBER( wtcnt_r );
|
||||
DECLARE_WRITE16_MEMBER( wtcnt_w );
|
||||
DECLARE_READ16_MEMBER( rstcsr_r );
|
||||
DECLARE_WRITE16_MEMBER( rstcsr_w );
|
||||
|
||||
// misc
|
||||
DECLARE_READ8_MEMBER( sbycr_r );
|
||||
DECLARE_WRITE8_MEMBER( sbycr_w );
|
||||
DECLARE_READ8_MEMBER( ccr_r );
|
||||
DECLARE_WRITE8_MEMBER( ccr_w );
|
||||
|
||||
// BSC
|
||||
DECLARE_READ32_MEMBER( bcr1_r );
|
||||
DECLARE_WRITE32_MEMBER( bcr1_w );
|
||||
DECLARE_READ32_MEMBER( bcr2_r );
|
||||
DECLARE_WRITE32_MEMBER( bcr2_w );
|
||||
DECLARE_READ32_MEMBER( wcr_r );
|
||||
DECLARE_WRITE32_MEMBER( wcr_w );
|
||||
DECLARE_READ32_MEMBER( mcr_r );
|
||||
DECLARE_WRITE32_MEMBER( mcr_w );
|
||||
DECLARE_READ32_MEMBER( rtcsr_r );
|
||||
DECLARE_WRITE32_MEMBER( rtcsr_w );
|
||||
DECLARE_READ32_MEMBER( rtcor_r );
|
||||
DECLARE_WRITE32_MEMBER( rtcor_w );
|
||||
DECLARE_READ32_MEMBER( rtcnt_r );
|
||||
DECLARE_WRITE32_MEMBER( rtcnt_w );
|
||||
|
||||
|
||||
virtual void set_frt_input(int state) override;
|
||||
void sh2_notify_dma_data_available();
|
||||
void func_fastirq();
|
||||
@ -128,11 +259,58 @@ private:
|
||||
int8_t m_irq_line_state[17];
|
||||
|
||||
address_space *m_internal;
|
||||
uint32_t m_m[0x200/4];
|
||||
// SCI
|
||||
uint8_t m_smr, m_brr, m_scr, m_tdr, m_ssr;
|
||||
// FRT / FRC
|
||||
uint8_t m_tier, m_ftcsr, m_frc_tcr, m_tocr;
|
||||
uint16_t m_frc;
|
||||
uint16_t m_ocra, m_ocrb, m_frc_icr;
|
||||
// INTC
|
||||
struct {
|
||||
uint8_t frc;
|
||||
uint8_t sci;
|
||||
uint8_t divu;
|
||||
uint8_t dmac;
|
||||
uint8_t wdt;
|
||||
} m_irq_level;
|
||||
struct {
|
||||
uint8_t fic;
|
||||
uint8_t foc;
|
||||
uint8_t fov;
|
||||
uint8_t divu;
|
||||
uint8_t dmac[2];
|
||||
} m_irq_vector;
|
||||
uint16_t m_ipra, m_iprb;
|
||||
uint16_t m_vcra, m_vcrb, m_vcrc, m_vcrd, m_vcrwdt, m_vcrdiv, m_intc_icr, m_vcrdma[2];
|
||||
bool m_vecmd, m_nmie;
|
||||
|
||||
// DIVU
|
||||
bool m_divu_ovf, m_divu_ovfie;
|
||||
uint32_t m_dvsr, m_dvdntl, m_dvdnth;
|
||||
|
||||
// WTC
|
||||
uint8_t m_wtcnt, m_wtcsr;
|
||||
uint8_t m_rstcsr;
|
||||
uint16_t m_wtcw[2];
|
||||
|
||||
// DMAC
|
||||
struct {
|
||||
uint8_t drcr;
|
||||
uint32_t sar;
|
||||
uint32_t dar;
|
||||
uint32_t tcr;
|
||||
uint32_t chcr;
|
||||
} m_dmac[2];
|
||||
uint8_t m_dmaor;
|
||||
|
||||
// misc
|
||||
uint8_t m_sbycr, m_ccr;
|
||||
|
||||
// BSC
|
||||
uint32_t m_bcr1, m_bcr2, m_wcr, m_mcr, m_rtcsr, m_rtcor, m_rtcnt;
|
||||
|
||||
int8_t m_nmi_line_state;
|
||||
|
||||
uint16_t m_frc;
|
||||
uint16_t m_ocra, m_ocrb, m_icr;
|
||||
uint64_t m_frc_base;
|
||||
|
||||
int m_frt_input;
|
||||
@ -150,8 +328,6 @@ private:
|
||||
uint32_t m_active_dma_src[2];
|
||||
uint32_t m_active_dma_dst[2];
|
||||
uint32_t m_active_dma_count[2];
|
||||
uint16_t m_wtcnt;
|
||||
uint8_t m_wtcsr;
|
||||
|
||||
int m_is_slave;
|
||||
dma_kludge_delegate m_dma_kludge_cb;
|
||||
@ -181,7 +357,7 @@ private:
|
||||
TIMER_CALLBACK_MEMBER( sh2_dma_current_active_callback );
|
||||
void sh2_timer_resync();
|
||||
void sh2_timer_activate();
|
||||
void sh2_do_dma(int dma);
|
||||
void sh2_do_dma(int dmach);
|
||||
virtual void sh2_exception(const char *message, int irqline) override;
|
||||
void sh2_dmac_check(int dma);
|
||||
void sh2_recalc_irq();
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -15,10 +15,11 @@
|
||||
|
||||
enum
|
||||
{
|
||||
ICF = 0x00800000,
|
||||
OCFA = 0x00080000,
|
||||
OCFB = 0x00040000,
|
||||
OVF = 0x00020000
|
||||
ICF = 0x80,
|
||||
OCFA = 0x08,
|
||||
OCFB = 0x04,
|
||||
OVF = 0x02,
|
||||
CCLRA = 0x01
|
||||
};
|
||||
|
||||
#define SH12_AM 0xc7ffffff
|
||||
|
||||
Loading…
Reference in New Issue
Block a user