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apple/apple2e.cpp: reset IOU softswitches (#12003)

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xotmatrix 2024-03-09 11:12:50 -05:00 committed by GitHub
parent c74cacfb69
commit d6e5fbde0e
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1 changed files with 58 additions and 29 deletions
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87
src/mame/apple/apple2e.cpp
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@ -1119,16 +1119,42 @@ void apple2e_state::machine_start()
void apple2e_state::machine_reset()
{
// All MMU switches off (80STORE, RAMRD, RAMWRT, INTCXROM, ALTZP, SLOTC3ROM, PAGE2, HIRES, INTC8ROM)
// Sather, Fig 5.13
m_ramrd = false;
m_ramwrt = false;
m_altzp = false;
m_slotc3rom = false;
m_intc8rom = false;
// Certain IOU switches off (80STORE, 80COL, ALTCHR, PAGE2, HIRES, AN0, AN1, AN2, AN3)
// Sather, Fig 7.1
m_video->a80store_w(false);
m_video->a80col_w(false);
m_video->altcharset_w(false);
m_video->page2_w(false);
m_video->monohgr_w(m_iscecm);
m_video->res_w(0);
// IIe IOU
m_an0 = m_an1 = m_an2 = m_an3 = false;
m_gameio->an0_w(0);
m_gameio->an1_w(0);
m_gameio->an2_w(0);
m_gameio->an3_w(0);
m_vbl = m_vblmask = false;
m_slotc3rom = false;
// IIc IOU
m_ioudis = true;
m_romswitch = false;
// LC resets to read ROM, write RAM, no pre-write, bank 2
// Sather, Fig 5.13
m_lcram = false;
m_lcram2 = true;
m_lcprewrite = false;
m_lcwriteenable = true;
m_video->monohgr_w(m_iscecm);
m_vbl = m_vblmask = false;
m_irqmask = 0;
m_strobe = 0;
m_franklin_last_fkeys = 0;
@ -1142,7 +1168,6 @@ void apple2e_state::machine_reset()
m_xirq = false;
m_yirq = false;
m_mockingboard4c = false;
m_intc8rom = false;
m_cec_bank = 0;
m_accel_unlocked = false;
m_accel_stage = 0;
@ -1221,23 +1246,10 @@ void apple2e_state::machine_reset()
}
m_video->a80store_w(false);
m_altzp = false;
m_ramrd = false;
m_ramwrt = false;
m_ioudis = true;
// LC default state: read ROM, write enabled, Dxxx bank 2
m_lcram = false;
m_lcram2 = true;
m_lcprewrite = false;
m_lcwriteenable = true;
lcrom_update();
m_exp_bankhior = 0xf0;
// sync up the banking with the variables.
// Understanding the Apple IIe: RESET on the IIe always resets LC state, doesn't on II/II+ with discrete LC
lcrom_update();
auxbank_update();
update_slotrom_banks();
}
@ -1320,20 +1332,13 @@ TIMER_DEVICE_CALLBACK_MEMBER(apple2e_state::apple2_interrupt)
m_reset_latch = true;
m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
// As per Sather: LC resets to read ROM, write RAM, no pre-write, bank 2
m_lcram = false;
m_lcram2 = true;
m_lcprewrite = false;
m_lcwriteenable = true;
lcrom_update();
// More Sather: all MMU switches off (80STORE, RAMRD, RAMWRT, INTCXROM, ALTZP, SLOTC3ROM, PAGE2, HIRES, INTC8ROM)
m_video->a80store_w(false);
// All MMU switches off (80STORE, RAMRD, RAMWRT, INTCXROM, ALTZP, SLOTC3ROM, PAGE2, HIRES, INTC8ROM)
// Sather, Fig 5.13
m_ramrd = false;
m_ramwrt = false;
m_altzp = false;
m_video->page2_w(false);
m_video->res_w(0);
m_slotc3rom = false;
m_intc8rom = false;
// reset intcxrom to default
if ((m_isiic) || (m_isace500))
@ -1345,6 +1350,30 @@ TIMER_DEVICE_CALLBACK_MEMBER(apple2e_state::apple2_interrupt)
m_intcxrom = false;
m_slotc3rom = false;
}
// Certain IOU switches off (80STORE, 80COL, ALTCHR, PAGE2, HIRES, AN0, AN1, AN2, AN3)
// Sather, Fig 7.1
m_video->a80store_w(false);
m_video->a80col_w(false);
m_video->altcharset_w(false);
m_video->page2_w(false);
m_video->res_w(0);
// IIe IOU
m_an0 = m_an1 = m_an2 = m_an3 = false;
m_gameio->an0_w(0);
m_gameio->an1_w(0);
m_gameio->an2_w(0);
m_gameio->an3_w(0);
// LC resets to read ROM, write RAM, no pre-write, bank 2
// Sather, Fig 5.13
m_lcram = false;
m_lcram2 = true;
m_lcprewrite = false;
m_lcwriteenable = true;
lcrom_update();
auxbank_update();
update_slotrom_banks();
}