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https://github.com/holub/mame
synced 2025-06-05 12:26:35 +03:00
hd6301: save more internal registers to nvram
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hap
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@ -9,6 +9,11 @@ TODO:
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- improve STBY pin? RES pin (reset) should be ineffective while STBY is low
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- IS3 interrupt for 6801 port 3 handshake (already implemented for 6301Y)
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- address TRAP (at the moment, only illegal opcode TRAP is emulated)
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if PC directed these areas:
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'mode' is selected by the sense of p2.0,p2.1,and p2.3 at reset timing.
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mode 0,1,2,4,6 : $0000-$001f
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mode 5 : $0000-$001f,$0200-$efff
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mode 7 : $0000-$001f,$0100-$efff
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- finish 6301Y port 6 handshake, share implementation with p3csr?
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- 6301Y sci_trcsr2_r/w
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- add 6801U4 extra timer registers (bublbobl, kikikai, though they seem
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@ -1417,6 +1422,19 @@ bool hd6301_cpu_device::nvram_write(util::write_stream &file)
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return false;
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size_t actual;
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u8 buf[7];
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// misc registers
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buf[0] = m_s.b.h;
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buf[1] = m_s.b.l;
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buf[2] = m_x.b.h;
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buf[3] = m_x.b.l;
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buf[4] = m_d.b.h;
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buf[5] = m_d.b.l;
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buf[6] = m_tdr;
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if (file.write(&buf, sizeof(buf), actual) || (sizeof(buf) != actual))
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return false;
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// port output latches
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if (file.write(&m_port_data[0], sizeof(m_port_data), actual) || sizeof(m_port_data) != actual)
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@ -1445,6 +1463,19 @@ bool hd6301_cpu_device::nvram_read(util::read_stream &file)
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return false;
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size_t actual;
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u8 buf[7];
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// misc registers
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if (file.read(&buf, sizeof(buf), actual) || (sizeof(buf) != actual))
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return false;
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m_s.b.h = buf[0];
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m_s.b.l = buf[1];
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m_x.b.h = buf[2];
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m_x.b.l = buf[3];
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m_d.b.h = buf[4];
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m_d.b.l = buf[5];
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m_tdr = buf[6];
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// port output latches
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if (file.read(&m_port_data[0], sizeof(m_port_data), actual) || sizeof(m_port_data) != actual)
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@ -1467,28 +1498,42 @@ bool hd6301x_cpu_device::nvram_read(util::read_stream &file)
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return true;
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}
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void hd6301_cpu_device::nvram_default()
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// internal registers
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void m6801_cpu_device::p1_ddr_w(uint8_t data)
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{
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if (!nvram_backup_enabled() || m_nvram_bytes == 0)
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return;
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LOGPORT("Port 1 Data Direction Register: %02x\n", data);
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m6801_cpu_device::nvram_default();
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// clear other registers
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std::fill(std::begin(m_port_data), std::end(m_port_data), 0);
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if (m_port_ddr[0] != data)
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{
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m_port_ddr[0] = data;
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m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff), m_port_ddr[0]);
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}
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}
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void hd6301x_cpu_device::nvram_default()
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void hd6301y_cpu_device::p1_ddr_1bit_w(uint8_t data)
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{
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if (!nvram_backup_enabled() || m_nvram_bytes == 0)
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return;
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hd6301_cpu_device::nvram_default();
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// clear other registers
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std::fill(std::begin(m_portx_data), std::end(m_portx_data), 0);
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// HD6301Y DDR1 is 1-bit (HD6301X does not have DDR1)
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hd6301_cpu_device::p1_ddr_w((BIT(data, 0) ? 0xff : 0x00));
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}
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uint8_t m6801_cpu_device::p1_data_r()
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{
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if (m_port_ddr[0] == 0xff)
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return m_port_data[0];
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else
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return (m_in_port_func[0]() & (m_port_ddr[0] ^ 0xff)) | (m_port_data[0] & m_port_ddr[0]);
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}
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void m6801_cpu_device::p1_data_w(uint8_t data)
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{
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LOGPORT("Port 1 Data Register: %02x\n", data);
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m_port_data[0] = data;
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m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff), m_port_ddr[0]);
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}
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void m6801_cpu_device::write_port2()
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@ -1540,55 +1585,6 @@ void hd6301x_cpu_device::write_port2()
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m_out_port_func[1](0, data, ddr);
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}
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/*
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if change_pc() directed these areas, call hd63701_trap_pc().
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'mode' is selected by the sense of p2.0,p2.1,and p2.3 at reset timing.
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mode 0,1,2,4,6 : $0000-$001f
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mode 5 : $0000-$001f,$0200-$efff
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mode 7 : $0000-$001f,$0100-$efff
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*/
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void m6801_cpu_device::set_os3(int state)
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{
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LOG("OS3: %u\n", state);
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m_out_sc2_func(state);
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}
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void m6801_cpu_device::p1_ddr_w(uint8_t data)
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{
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LOGPORT("Port 1 Data Direction Register: %02x\n", data);
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if (m_port_ddr[0] != data)
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{
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m_port_ddr[0] = data;
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m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff), m_port_ddr[0]);
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}
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}
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void hd6301y_cpu_device::p1_ddr_1bit_w(uint8_t data)
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{
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// HD6301Y DDR1 is 1-bit (HD6301X does not have DDR1)
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hd6301_cpu_device::p1_ddr_w((BIT(data, 0) ? 0xff : 0x00));
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}
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uint8_t m6801_cpu_device::p1_data_r()
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{
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if (m_port_ddr[0] == 0xff)
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return m_port_data[0];
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else
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return (m_in_port_func[0]() & (m_port_ddr[0] ^ 0xff)) | (m_port_data[0] & m_port_ddr[0]);
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}
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void m6801_cpu_device::p1_data_w(uint8_t data)
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{
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LOGPORT("Port 1 Data Register: %02x\n", data);
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m_port_data[0] = data;
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m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff), m_port_ddr[0]);
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}
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void m6801_cpu_device::p2_ddr_w(uint8_t data)
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{
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LOGPORT("Port 2 Data Direction Register: %02x\n", data);
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@ -1623,6 +1619,14 @@ void m6801_cpu_device::p2_data_w(uint8_t data)
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write_port2();
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}
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void m6801_cpu_device::set_os3(int state)
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{
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LOG("OS3: %u\n", state);
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m_out_sc2_func(state);
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}
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void m6801_cpu_device::p3_ddr_w(uint8_t data)
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{
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LOGPORT("Port 3 Data Direction Register: %02x\n", data);
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@ -1736,6 +1740,7 @@ void m6801_cpu_device::p3_csr_w(uint8_t data)
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m_p3csr = data;
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}
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void m6801_cpu_device::p4_ddr_w(uint8_t data)
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{
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LOGPORT("Port 4 Data Direction Register: %02x\n", data);
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@ -1774,6 +1779,7 @@ void hd6301y_cpu_device::p5_ddr_w(uint8_t data)
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}
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}
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uint8_t hd6301x_cpu_device::p5_data_r()
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{
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// read-only
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@ -1796,6 +1802,7 @@ void hd6301y_cpu_device::p5_data_w(uint8_t data)
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m_out_portx_func[0](0, (m_portx_data[0] & m_portx_ddr[0]) | (m_portx_ddr[0] ^ 0xff), m_portx_ddr[0]);
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}
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void hd6301x_cpu_device::p6_ddr_w(uint8_t data)
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{
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LOGPORT("Port 6 Data Direction Register: %02x\n", data);
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@ -1865,6 +1872,7 @@ void hd6301y_cpu_device::p6_csr_w(uint8_t data)
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m6800_check_irq2();
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}
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uint8_t hd6301x_cpu_device::p7_data_r()
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{
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return 0xe0 | m_portx_data[2];
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@ -1880,6 +1888,7 @@ void hd6301x_cpu_device::p7_data_w(uint8_t data)
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m_out_portx_func[2](0, m_portx_data[2], 0x1f);
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}
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uint8_t m6801_cpu_device::tcsr_r()
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{
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if (!machine().side_effects_disabled())
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@ -1993,6 +2002,7 @@ uint8_t m6801_cpu_device::icrl_r()
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return (m_input_capture >> 8) & 0xff;
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}
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uint8_t hd6301x_cpu_device::tcsr2_r()
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{
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if (!machine().side_effects_disabled())
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@ -259,7 +259,6 @@ protected:
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hd6301_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const m6800_cpu_device::op_func *insn, const uint8_t *cycles, address_map_constructor internal, int nvram_bytes);
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// device_nvram_interface implementation
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virtual void nvram_default() override;
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virtual bool nvram_read(util::read_stream &file) override;
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virtual bool nvram_write(util::write_stream &file) override;
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@ -316,7 +315,6 @@ protected:
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hd6301x_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor internal, int nvram_bytes);
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// device_nvram_interface implementation
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virtual void nvram_default() override;
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virtual bool nvram_read(util::read_stream &file) override;
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virtual bool nvram_write(util::write_stream &file) override;
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