Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-07-05 01:48:29 +03:00
Code Issues Actions 33 Packages Projects Releases Wiki Activity

mcs51: clean up source code spacing

Browse Source
This commit is contained in:
hap 2025-01-22 20:44:02 +01:00
parent 252941fe51
commit d74df7ffaa
2 changed files with 558 additions and 557 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

301
src/devices/cpu/mcs51/mcs51.cpp
View File

@ -52,6 +52,7 @@
*****************************************************************************/
/******************************************************************************
*
* Notes:
*
* The term cycles is used here to really refer to clock oscilations, because 1 machine cycle
@ -252,7 +253,7 @@ mcs51_cpu_device::mcs51_cpu_device(const machine_config &mconfig, device_type ty
, m_features(features)
, m_inst_cycles(0)
, m_rom_size(program_width > 0 ? 1 << program_width : 0)
, m_ram_mask( (data_width == 8) ? 0xff : 0x7f )
, m_ram_mask((data_width == 8) ? 0xff : 0x7f)
, m_num_interrupts(5)
, m_sfr_ram(*this, "sfr_ram")
, m_scratchpad(*this, "scratchpad")
@ -588,15 +589,15 @@ void mcs51_cpu_device::iram_iwrite(offs_t a, uint8_t d) { if (a <= m_ram_mask) m
/* Macros for Setting Flags */
#define SET_X(R, v) do { R = (v);} while (0)
#define SET_CY(n) SET_PSW((PSW & 0x7f) | (n<<7)) //Carry Flag
#define SET_AC(n) SET_PSW((PSW & 0xbf) | (n<<6)) //Aux.Carry Flag
#define SET_FO(n) SET_PSW((PSW & 0xdf) | (n<<5)) //User Flag
#define SET_RS(n) SET_PSW((PSW & 0xe7) | (n<<3)) //R Bank Select
#define SET_OV(n) SET_PSW((PSW & 0xfb) | (n<<2)) //Overflow Flag
#define SET_P(n) SET_PSW((PSW & 0xfe) | (n<<0)) //Parity Flag
#define SET_CY(n) SET_PSW((PSW & 0x7f) | ((n) << 7)) //Carry Flag
#define SET_AC(n) SET_PSW((PSW & 0xbf) | ((n) << 6)) //Aux.Carry Flag
#define SET_FO(n) SET_PSW((PSW & 0xdf) | ((n) << 5)) //User Flag
#define SET_RS(n) SET_PSW((PSW & 0xe7) | ((n) << 3)) //R Bank Select
#define SET_OV(n) SET_PSW((PSW & 0xfb) | ((n) << 2)) //Overflow Flag
#define SET_P(n) SET_PSW((PSW & 0xfe) | ((n) << 0)) //Parity Flag
#define SET_BIT(R, n, v) do { R = (R & ~(1<<(n))) | ((v) << (n));} while (0)
#define GET_BIT(R, n) (((R)>>(n)) & 0x01)
#define SET_BIT(R, n, v) do { R = (R & ~(1 << (n))) | ((v) << (n)); } while (0)
#define GET_BIT(R, n) (((R) >> (n)) & 0x01)
#define SET_EA(n) SET_BIT(IE, 7, n) //Global Interrupt Enable/Disable
#define SET_ES(n) SET_BIT(IE, 4, v) //Serial Interrupt Enable/Disable
@ -608,7 +609,7 @@ void mcs51_cpu_device::iram_iwrite(offs_t a, uint8_t d) { if (a <= m_ram_mask) m
#define SET_ET2(n) SET_BIT(IE, 5, n) //Timer 2 Interrupt Enable/Disable
/* 8052 Only flags */
#define SET_PT2(n) SET_BIT(IP, 5, n); //Set Timer 2 Priority Level
#define SET_PT2(n) SET_BIT(IP, 5, n) //Set Timer 2 Priority Level
#define SET_PS0(n) SET_BIT(IP, 4, n) //Set Serial Priority Level
#define SET_PT1(n) SET_BIT(IP, 3, n) //Set Timer 1 Priority Level
@ -720,7 +721,7 @@ void mcs51_cpu_device::iram_iwrite(offs_t a, uint8_t d) { if (a <= m_ram_mask) m
#define GET_GF1 GET_BIT(PCON, 3)
#define GET_GF0 GET_BIT(PCON, 2)
#define GET_PD GET_BIT(PCON, 1)
#define GET_IDL (GET_BIT(PCON, 0) & ~(GET_PD)) /* PD takes precedence! */
#define GET_IDL (GET_BIT(PCON, 0) & ~(GET_PD)) // PD takes precedence!
/* 8052 Only flags */
#define GET_TF2 GET_BIT(T2CON, 7)
@ -753,7 +754,7 @@ void mcs51_cpu_device::iram_iwrite(offs_t a, uint8_t d) { if (a <= m_ram_mask) m
#define GET_SL GET_BIT(MCON, 0)
/* RPCTL Flags - DS5002FP */
#define GET_RNR GET_BIT(RPCTL, 7) /* Bit 6 ?? */
#define GET_RNR GET_BIT(RPCTL, 7) // Bit 6 ??
#define GET_EXBS GET_BIT(RPCTL, 5)
#define GET_AE GET_BIT(RPCTL, 4)
#define GET_IBI GET_BIT(RPCTL, 3)
@ -766,7 +767,7 @@ void mcs51_cpu_device::iram_iwrite(offs_t a, uint8_t d) { if (a <= m_ram_mask) m
#define DO_ADD_FLAGS(a,d,c) do_add_flags(a, d, c)
#define DO_SUB_FLAGS(a,d,c) do_sub_flags(a, d, c)
#define SET_PARITY() do {m_recalc_parity |= 1;} while (0)
#define SET_PARITY() do { m_recalc_parity |= 1; } while (0)
#define PUSH_PC() push_pc()
#define POP_PC() pop_pc()
@ -842,9 +843,11 @@ offs_t mcs51_cpu_device::external_ram_iaddr(offs_t offset, offs_t mem_mask)
/* Memory Range (RG1 and RG0 @ MCON and RPCTL registers) */
static const uint16_t ds5002fp_ranges[4] = { 0x1fff, 0x3fff, 0x7fff, 0xffff };
/* Memory Partition Table (RG1 & RG0 @ MCON & RPCTL registers) */
static const uint32_t ds5002fp_partitions[16] = {
static const uint32_t ds5002fp_partitions[16] =
{
0x0000, 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7000,
0x8000, 0x9000, 0xa000, 0xb000, 0xc000, 0xd000, 0xe000, 0x10000 };
0x8000, 0x9000, 0xa000, 0xb000, 0xc000, 0xd000, 0xe000, 0x10000
};
/* if partition mode is set, adjust offset based on the bus */
if (m_features & FEATURE_DS5002FP)
@ -872,12 +875,12 @@ offs_t mcs51_cpu_device::external_ram_iaddr(offs_t offset, offs_t mem_mask)
uint8_t mcs51_cpu_device::iram_read(size_t offset)
{
return (((offset) < 0x80) ? m_data.read_byte(offset) : sfr_read(offset));
return ((offset < 0x80) ? m_data.read_byte(offset) : sfr_read(offset));
}
void mcs51_cpu_device::iram_write(size_t offset, uint8_t data)
{
if ((offset) < 0x80)
if (offset < 0x80)
m_data.write_byte(offset, data);
else
sfr_write(offset, data);
@ -886,11 +889,11 @@ void mcs51_cpu_device::iram_write(size_t offset, uint8_t data)
/*Push the current PC to the stack*/
void mcs51_cpu_device::push_pc()
{
uint8_t tmpSP = SP+1; //Grab and Increment Stack Pointer
uint8_t tmpSP = SP + 1; //Grab and Increment Stack Pointer
IRAM_IW(tmpSP, (PC & 0xff)); //Store low byte of PC to Internal Ram (Use IRAM_IW to store stack above 128 bytes)
tmpSP++; // ""
SP = tmpSP; // ""
IRAM_IW(tmpSP, ( (PC & 0xff00) >> 8)); //Store hi byte of PC to next address in Internal Ram (Use IRAM_IW to store stack above 128 bytes)
IRAM_IW(tmpSP, ((PC & 0xff00) >> 8)); //Store hi byte of PC to next address in Internal Ram (Use IRAM_IW to store stack above 128 bytes)
}
/*Pop the current PC off the stack and into the pc*/
@ -907,10 +910,9 @@ void mcs51_cpu_device::set_parity()
{
//This flag will be set when the accumulator contains an odd # of bits set..
uint8_t p = 0;
int i;
uint8_t a = ACC;
for (i=0; i<8; i++) //Test for each of the 8 bits in the ACC!
for (int i = 0; i < 8; i++) //Test for each of the 8 bits in the ACC!
{
p ^= (a & 1);
a = (a >> 1);
@ -933,7 +935,7 @@ uint8_t mcs51_cpu_device::bit_address_r(uint8_t offset)
if (offset < 0x80)
{
distance = 1;
word = ( (offset & 0x78) >> 3) * distance + 0x20;
word = ((offset & 0x78) >> 3) * distance + 0x20;
bit_pos = offset & 0x7;
mask = (0x1 << bit_pos);
return((IRAM_R(word) & mask) >> bit_pos);
@ -942,7 +944,7 @@ uint8_t mcs51_cpu_device::bit_address_r(uint8_t offset)
else
{
distance = 8;
word = ( (offset & 0x78) >> 3) * distance + 0x80;
word = ((offset & 0x78) >> 3) * distance + 0x80;
bit_pos = offset & 0x7;
mask = (0x1 << bit_pos);
return ((IRAM_R(word) & mask) >> bit_pos);
@ -986,22 +988,22 @@ void mcs51_cpu_device::bit_address_w(uint8_t offset, uint8_t bit)
void mcs51_cpu_device::do_add_flags(uint8_t a, uint8_t data, uint8_t c)
{
uint16_t result = a+data+c;
int16_t result1 = (int8_t)a+(int8_t)data+c;
uint16_t result = a + data + c;
int16_t result1 = (int8_t)a + (int8_t)data + c;
SET_CY((result & 0x100) >> 8);
result = (a&0x0f)+(data&0x0f)+c;
result = (a & 0x0f) + (data & 0x0f) + c;
SET_AC((result & 0x10) >> 4);
SET_OV(result1 < -128 || result1 > 127);
}
void mcs51_cpu_device::do_sub_flags(uint8_t a, uint8_t data, uint8_t c)
{
uint16_t result = a-(data+c);
int16_t result1 = (int8_t)a-(int8_t)(data+c);
uint16_t result = a - (data + c);
int16_t result1 = (int8_t)a - (int8_t)(data + c);
SET_CY((result & 0x100) >> 8);
result = (a&0x0f)-((data&0x0f)+c);
result = (a & 0x0f) - ((data & 0x0f) + c);
SET_AC((result & 0x10) >> 4);
SET_OV((result1 < -128 || result1 > 127));
}
@ -1025,12 +1027,12 @@ void mcs51_cpu_device::transmit(int state)
void mcs51_cpu_device::transmit_receive(int source)
{
int mode = (GET_SM0<<1) | GET_SM1;
int mode = (GET_SM0 << 1) | GET_SM1;
if (source == 1) /* timer1 */
m_uart.smod_div = (m_uart.smod_div + 1) & (1-GET_SMOD);
switch(mode)
switch (mode)
{
// 8 bit shifter - rate set by clock freq / 12
case 0:
@ -1231,7 +1233,7 @@ void mcs51_cpu_device::transmit_receive(int source)
void mcs51_cpu_device::update_timer_t0(int cycles)
{
int mode = (GET_M0_1<<1) | GET_M0_0;
int mode = (GET_M0_1 << 1) | GET_M0_0;
uint32_t count;
if (GET_TR0)
@ -1248,27 +1250,27 @@ void mcs51_cpu_device::update_timer_t0(int cycles)
if (GET_GATE0 && !GET_IE0)
delta = 0;
switch(mode)
switch (mode)
{
case 0: /* 13 Bit Timer Mode */
count = ((TH0<<5) | ( TL0 & 0x1f ) );
count = ((TH0 << 5) | (TL0 & 0x1f));
count += delta;
if ( count & 0xffffe000 ) /* Check for overflow */
if (count & 0xffffe000) /* Check for overflow */
SET_TF0(1);
TH0 = (count>>5) & 0xff;
TH0 = (count >> 5) & 0xff;
TL0 = count & 0x1f;
break;
case 1: /* 16 Bit Timer Mode */
count = ((TH0<<8) | TL0);
count = ((TH0 << 8) | TL0);
count += delta;
if ( count & 0xffff0000 ) /* Check for overflow */
if (count & 0xffff0000) /* Check for overflow */
SET_TF0(1);
TH0 = (count>>8) & 0xff;
TH0 = (count >> 8) & 0xff;
TL0 = count & 0xff;
break;
case 2: /* 8 Bit Autoreload */
count = ((uint32_t) TL0) + delta;
if ( count & 0xffffff00 ) /* Check for overflow */
count = ((uint32_t)TL0) + delta;
if (count & 0xffffff00) /* Check for overflow */
{
SET_TF0(1);
count += TH0; /* Reload timer */
@ -1278,8 +1280,8 @@ void mcs51_cpu_device::update_timer_t0(int cycles)
break;
case 3:
/* Split Timer 1 */
count = ((uint32_t) TL0) + delta;
if ( count & 0xffffff00 ) /* Check for overflow */
count = ((uint32_t)TL0) + delta;
if (count & 0xffffff00) /* Check for overflow */
SET_TF0(1);
TL0 = count & 0xff; /* Update new values of the counter */
break;
@ -1287,12 +1289,12 @@ void mcs51_cpu_device::update_timer_t0(int cycles)
}
if (GET_TR1)
{
switch(mode)
switch (mode)
{
case 3:
/* Split Timer 2 */
count = ((uint32_t) TH0) + cycles; /* No gate control or counting !*/
if ( count & 0xffffff00 ) /* Check for overflow */
count = ((uint32_t)TH0) + cycles; /* No gate control or counting !*/
if (count & 0xffffff00) /* Check for overflow */
SET_TF1(1);
TH0 = count & 0xff; /* Update new values of the counter */
break;
@ -1318,8 +1320,8 @@ switching it into or out of Mode 3 or it can be assigned as a baud rate generato
void mcs51_cpu_device::update_timer_t1(int cycles)
{
uint8_t mode = (GET_M1_1<<1) | GET_M1_0;
uint8_t mode_0 = (GET_M0_1<<1) | GET_M0_0;
uint8_t mode = (GET_M1_1 << 1) | GET_M1_0;
uint8_t mode_0 = (GET_M0_1 << 1) | GET_M0_0;
uint32_t count;
if (mode_0 != 3)
@ -1339,29 +1341,27 @@ void mcs51_cpu_device::update_timer_t1(int cycles)
if (GET_GATE1 && !GET_IE1)
delta = 0;
switch(mode)
switch (mode)
{
case 0: /* 13 Bit Timer Mode */
count = ((TH1<<5) | ( TL1 & 0x1f ) );
count = ((TH1 << 5) | (TL1 & 0x1f));
count += delta;
overflow = count & 0xffffe000; /* Check for overflow */
TH1 = (count>>5) & 0xff;
TH1 = (count >> 5) & 0xff;
TL1 = count & 0x1f;
break;
case 1: /* 16 Bit Timer Mode */
count = ((TH1<<8) | TL1);
count = ((TH1 << 8) | TL1);
count += delta;
overflow = count & 0xffff0000; /* Check for overflow */
TH1 = (count>>8) & 0xff;
TH1 = (count >> 8) & 0xff;
TL1 = count & 0xff;
break;
case 2: /* 8 Bit Autoreload */
count = ((uint32_t) TL1) + delta;
count = ((uint32_t)TL1) + delta;
overflow = count & 0xffffff00; /* Check for overflow */
if ( overflow )
{
if (overflow)
count += TH1; /* Reload timer */
}
/* Update new values of the counter */
TL1 = count & 0xff;
break;
@ -1384,29 +1384,27 @@ void mcs51_cpu_device::update_timer_t1(int cycles)
delta = cycles;
/* taken, reset */
m_t1_cnt = 0;
switch(mode)
switch (mode)
{
case 0: /* 13 Bit Timer Mode */
count = ((TH1<<5) | ( TL1 & 0x1f ) );
count = ((TH1 << 5) | (TL1 & 0x1f));
count += delta;
overflow = count & 0xffffe000; /* Check for overflow */
TH1 = (count>>5) & 0xff;
TH1 = (count >> 5) & 0xff;
TL1 = count & 0x1f;
break;
case 1: /* 16 Bit Timer Mode */
count = ((TH1<<8) | TL1);
count = ((TH1 << 8) | TL1);
count += delta;
overflow = count & 0xffff0000; /* Check for overflow */
TH1 = (count>>8) & 0xff;
TH1 = (count >> 8) & 0xff;
TL1 = count & 0xff;
break;
case 2: /* 8 Bit Autoreload */
count = ((uint32_t) TL1) + delta;
count = ((uint32_t)TL1) + delta;
overflow = count & 0xffffff00; /* Check for overflow */
if ( overflow )
{
if (overflow)
count += TH1; /* Reload timer */
}
/* Update new values of the counter */
TL1 = count & 0xff;
break;
@ -1424,37 +1422,37 @@ void mcs51_cpu_device::update_timer_t1(int cycles)
void mcs51_cpu_device::update_timer_t2(int cycles)
{
/* Update Timer 2 */
if(GET_TR2)
if (GET_TR2)
{
int mode = ((GET_TCLK | GET_RCLK) << 1) | GET_CP;
int delta = GET_CT2 ? m_t2_cnt : (mode & 2) ? cycles * (12/2) : cycles;
uint32_t count = ((TH2<<8) | TL2) + delta;
uint32_t count = ((TH2 << 8) | TL2) + delta;
m_t2_cnt = 0;
switch (mode)
{
case 0: /* 16 Bit Auto Reload */
if ( count & 0xffff0000 )
if (count & 0xffff0000)
{
SET_TF2(1);
count += ((RCAP2H<<8) | RCAP2L);
count += ((RCAP2H << 8) | RCAP2L);
}
else if (GET_EXEN2 && m_t2ex_cnt>0)
else if (GET_EXEN2 && m_t2ex_cnt > 0)
{
count += ((RCAP2H<<8) | RCAP2L);
count += ((RCAP2H << 8) | RCAP2L);
m_t2ex_cnt = 0;
}
TH2 = (count>>8) & 0xff;
TH2 = (count >> 8) & 0xff;
TL2 = count & 0xff;
break;
case 1: /* 16 Bit Capture */
if ( count & 0xffff0000 )
if (count & 0xffff0000)
SET_TF2(1);
TH2 = (count>>8) & 0xff;
TH2 = (count >> 8) & 0xff;
TL2 = count & 0xff;
if (GET_EXEN2 && m_t2ex_cnt>0)
if (GET_EXEN2 && m_t2ex_cnt > 0)
{
RCAP2H = TH2;
RCAP2L = TL2;
@ -1463,12 +1461,12 @@ void mcs51_cpu_device::update_timer_t2(int cycles)
break;
case 2:
case 3: /* Baud rate */
if ( count & 0xffff0000 )
if (count & 0xffff0000)
{
count += ((RCAP2H<<8) | RCAP2L);
count += ((RCAP2H << 8) | RCAP2L);
transmit_receive(2);
}
TH2 = (count>>8) & 0xff;
TH2 = (count >> 8) & 0xff;
TL2 = count & 0xff;
break;
}
@ -1478,8 +1476,8 @@ void mcs51_cpu_device::update_timer_t2(int cycles)
/* Check and update status of serial port */
void mcs51_cpu_device::update_irq_prio(uint8_t ipl, uint8_t iph)
{
for (int i=0; i<8; i++)
m_irq_prio[i] = ((ipl >> i) & 1) | (((iph >>i ) & 1) << 1);
for (int i = 0; i < 8; i++)
m_irq_prio[i] = ((ipl >> i) & 1) | (((iph >> i) & 1) << 1);
}
@ -1502,17 +1500,17 @@ void mcs51_cpu_device::execute_op(uint8_t op)
m_last_op = op;
switch( op )
switch (op)
{
case 0x00: nop(op); break; //NOP
case 0x01: ajmp(op); break; //AJMP code addr
case 0x02: ljmp(op); break; //LJMP code addr
case 0x03: rr_a(op); break; //RR A
case 0x04: inc_a(op); break; //INC A
case 0x05: RWM=1; inc_mem(op); RWM=0; break; //INC data addr
case 0x05: RWM = 1; inc_mem(op); RWM = 0; break; //INC data addr
case 0x06:
case 0x07: inc_ir(op&1); break; //INC @R0/@R1
case 0x07: inc_ir(op & 1); break; //INC @R0/@R1
case 0x08:
case 0x09:
@ -1521,17 +1519,17 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f: inc_r(op&7); break; //INC R0 to R7
case 0x0f: inc_r(op & 7); break; //INC R0 to R7
case 0x10: RWM=1; jbc(op); RWM=0; break; //JBC bit addr, code addr
case 0x10: RWM = 1; jbc(op); RWM = 0; break; //JBC bit addr, code addr
case 0x11: acall(op); break; //ACALL code addr
case 0x12: lcall(op); break; //LCALL code addr
case 0x13: rrc_a(op); break; //RRC A
case 0x14: dec_a(op); break; //DEC A
case 0x15: RWM=1; dec_mem(op); RWM=0; break; //DEC data addr
case 0x15: RWM = 1; dec_mem(op); RWM = 0; break; //DEC data addr
case 0x16:
case 0x17: dec_ir(op&1); break; //DEC @R0/@R1
case 0x17: dec_ir(op & 1); break; //DEC @R0/@R1
case 0x18:
case 0x19:
@ -1540,7 +1538,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x1c:
case 0x1d:
case 0x1e:
case 0x1f: dec_r(op&7); break; //DEC R0 to R7
case 0x1f: dec_r(op & 7); break; //DEC R0 to R7
case 0x20: jb(op); break; //JB bit addr, code addr
case 0x21: ajmp(op); break; //AJMP code addr
@ -1550,7 +1548,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x25: add_a_mem(op); break; //ADD A, data addr
case 0x26:
case 0x27: add_a_ir(op&1); break; //ADD A, @R0/@R1
case 0x27: add_a_ir(op & 1); break; //ADD A, @R0/@R1
case 0x28:
case 0x29:
@ -1559,7 +1557,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x2c:
case 0x2d:
case 0x2e:
case 0x2f: add_a_r(op&7); break; //ADD A, R0 to R7
case 0x2f: add_a_r(op & 7); break; //ADD A, R0 to R7
case 0x30: jnb(op); break; //JNB bit addr, code addr
case 0x31: acall(op); break; //ACALL code addr
@ -1569,7 +1567,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x35: addc_a_mem(op); break; //ADDC A, data addr
case 0x36:
case 0x37: addc_a_ir(op&1); break; //ADDC A, @R0/@R1
case 0x37: addc_a_ir(op & 1); break; //ADDC A, @R0/@R1
case 0x38:
case 0x39:
@ -1578,17 +1576,17 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x3c:
case 0x3d:
case 0x3e:
case 0x3f: addc_a_r(op&7); break; //ADDC A, R0 to R7
case 0x3f: addc_a_r(op & 7); break; //ADDC A, R0 to R7
case 0x40: jc(op); break; //JC code addr
case 0x41: ajmp(op); break; //AJMP code addr
case 0x42: RWM=1; orl_mem_a(op); RWM=0; break; //ORL data addr, A
case 0x43: RWM=1; orl_mem_byte(op); RWM=0; break; //ORL data addr, #data
case 0x42: RWM = 1; orl_mem_a(op); RWM = 0; break; //ORL data addr, A
case 0x43: RWM = 1; orl_mem_byte(op); RWM = 0; break; //ORL data addr, #data
case 0x44: orl_a_byte(op); break;
case 0x45: orl_a_mem(op); break; //ORL A, data addr
case 0x46:
case 0x47: orl_a_ir(op&1); break; //ORL A, @RO/@R1
case 0x47: orl_a_ir(op & 1); break; //ORL A, @RO/@R1
case 0x48:
case 0x49:
@ -1597,17 +1595,17 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x4c:
case 0x4d:
case 0x4e:
case 0x4f: orl_a_r(op&7); break; //ORL A, RO to R7
case 0x4f: orl_a_r(op & 7); break; //ORL A, RO to R7
case 0x50: jnc(op); break; //JNC code addr
case 0x51: acall(op); break; //ACALL code addr
case 0x52: RWM=1; anl_mem_a(op); RWM=0; break; //ANL data addr, A
case 0x53: RWM=1; anl_mem_byte(op); RWM=0; break; //ANL data addr, #data
case 0x52: RWM = 1; anl_mem_a(op); RWM = 0; break; //ANL data addr, A
case 0x53: RWM = 1; anl_mem_byte(op); RWM = 0; break; //ANL data addr, #data
case 0x54: anl_a_byte(op); break; //ANL A, #data
case 0x55: anl_a_mem(op); break; //ANL A, data addr
case 0x56:
case 0x57: anl_a_ir(op&1); break; //ANL A, @RO/@R1
case 0x57: anl_a_ir(op & 1); break; //ANL A, @RO/@R1
case 0x58:
case 0x59:
@ -1616,17 +1614,17 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x5c:
case 0x5d:
case 0x5e:
case 0x5f: anl_a_r(op&7); break; //ANL A, RO to R7
case 0x5f: anl_a_r(op & 7); break; //ANL A, RO to R7
case 0x60: jz(op); break; //JZ code addr
case 0x61: ajmp(op); break; //AJMP code addr
case 0x62: RWM=1; xrl_mem_a(op); RWM=0; break; //XRL data addr, A
case 0x63: RWM=1; xrl_mem_byte(op); RWM=0; break; //XRL data addr, #data
case 0x62: RWM = 1; xrl_mem_a(op); RWM = 0; break; //XRL data addr, A
case 0x63: RWM = 1; xrl_mem_byte(op); RWM = 0; break; //XRL data addr, #data
case 0x64: xrl_a_byte(op); break; //XRL A, #data
case 0x65: xrl_a_mem(op); break; //XRL A, data addr
case 0x66:
case 0x67: xrl_a_ir(op&1); break; //XRL A, @R0/@R1
case 0x67: xrl_a_ir(op & 1); break; //XRL A, @R0/@R1
case 0x68:
case 0x69:
@ -1635,7 +1633,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x6c:
case 0x6d:
case 0x6e:
case 0x6f: xrl_a_r(op&7); break; //XRL A, R0 to R7
case 0x6f: xrl_a_r(op & 7); break; //XRL A, R0 to R7
case 0x70: jnz(op); break; //JNZ code addr
case 0x71: acall(op); break; //ACALL code addr
@ -1645,7 +1643,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x75: mov_mem_byte(op); break; //MOV data addr, #data
case 0x76:
case 0x77: mov_ir_byte(op&1); break; //MOV @R0/@R1, #data
case 0x77: mov_ir_byte(op & 1); break; //MOV @R0/@R1, #data
case 0x78:
case 0x79:
@ -1654,7 +1652,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x7c:
case 0x7d:
case 0x7e:
case 0x7f: mov_r_byte(op&7); break; //MOV R0 to R7, #data
case 0x7f: mov_r_byte(op & 7); break; //MOV R0 to R7, #data
case 0x80: sjmp(op); break; //SJMP code addr
case 0x81: ajmp(op); break; //AJMP code addr
@ -1664,7 +1662,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x85: mov_mem_mem(op); break; //MOV data addr, data addr
case 0x86:
case 0x87: mov_mem_ir(op&1); break; //MOV data addr, @R0/@R1
case 0x87: mov_mem_ir(op & 1); break; //MOV data addr, @R0/@R1
case 0x88:
case 0x89:
@ -1673,7 +1671,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x8c:
case 0x8d:
case 0x8e:
case 0x8f: mov_mem_r(op&7); break; //MOV data addr,R0 to R7
case 0x8f: mov_mem_r(op & 7); break; //MOV data addr,R0 to R7
case 0x90: mov_dptr_byte(op); break; //MOV DPTR, #data
case 0x91: acall(op); break; //ACALL code addr
@ -1683,7 +1681,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x95: subb_a_mem(op); break; //SUBB A, data addr
case 0x96:
case 0x97: subb_a_ir(op&1); break; //SUBB A, @R0/@R1
case 0x97: subb_a_ir(op & 1); break; //SUBB A, @R0/@R1
case 0x98:
case 0x99:
@ -1692,7 +1690,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0x9c:
case 0x9d:
case 0x9e:
case 0x9f: subb_a_r(op&7); break; //SUBB A, R0 to R7
case 0x9f: subb_a_r(op & 7); break; //SUBB A, R0 to R7
case 0xa0: orl_c_nbitaddr(op); break; //ORL C, /bit addr
case 0xa1: ajmp(op); break; //AJMP code addr
@ -1702,7 +1700,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0xa5: illegal(op); break; //reserved
case 0xa6:
case 0xa7: mov_ir_mem(op&1); break; //MOV @R0/@R1, data addr
case 0xa7: mov_ir_mem(op & 1); break; //MOV @R0/@R1, data addr
case 0xa8:
case 0xa9:
@ -1711,17 +1709,17 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0xac:
case 0xad:
case 0xae:
case 0xaf: mov_r_mem(op&7); break; //MOV R0 to R7, data addr
case 0xaf: mov_r_mem(op & 7); break; //MOV R0 to R7, data addr
case 0xb0: anl_c_nbitaddr(op); break; //ANL C,/bit addr
case 0xb1: acall(op); break; //ACALL code addr
case 0xb2: RWM=1; cpl_bitaddr(op); RWM=0; break; //CPL bit addr
case 0xb2: RWM = 1; cpl_bitaddr(op); RWM = 0; break; //CPL bit addr
case 0xb3: cpl_c(op); break; //CPL C
case 0xb4: cjne_a_byte(op); break; //CJNE A, #data, code addr
case 0xb5: cjne_a_mem(op); break; //CJNE A, data addr, code addr
case 0xb6:
case 0xb7: cjne_ir_byte(op&1); break; //CJNE @R0/@R1, #data, code addr
case 0xb7: cjne_ir_byte(op & 1); break; //CJNE @R0/@R1, #data, code addr
case 0xb8:
case 0xb9:
@ -1730,17 +1728,17 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0xbc:
case 0xbd:
case 0xbe:
case 0xbf: cjne_r_byte(op&7); break; //CJNE R0 to R7, #data, code addr
case 0xbf: cjne_r_byte(op & 7); break; //CJNE R0 to R7, #data, code addr
case 0xc0: push(op); break; //PUSH data addr
case 0xc1: ajmp(op); break; //AJMP code addr
case 0xc2: RWM=1; clr_bitaddr(op); RWM=0; break; //CLR bit addr
case 0xc2: RWM = 1; clr_bitaddr(op); RWM = 0; break; //CLR bit addr
case 0xc3: clr_c(op); break; //CLR C
case 0xc4: swap_a(op); break; //SWAP A
case 0xc5: xch_a_mem(op); break; //XCH A, data addr
case 0xc6:
case 0xc7: xch_a_ir(op&1); break; //XCH A, @RO/@R1
case 0xc7: xch_a_ir(op & 1); break; //XCH A, @RO/@R1
case 0xc8:
case 0xc9:
@ -1749,17 +1747,17 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0xcc:
case 0xcd:
case 0xce:
case 0xcf: xch_a_r(op&7); break; //XCH A, RO to R7
case 0xcf: xch_a_r(op & 7); break; //XCH A, RO to R7
case 0xd0: pop(op); break; //POP data addr
case 0xd1: acall(op); break; //ACALL code addr
case 0xd2: RWM=1; setb_bitaddr(op); RWM=0; break; //SETB bit addr
case 0xd2: RWM = 1; setb_bitaddr(op); RWM = 0; break; //SETB bit addr
case 0xd3: setb_c(op); break; //SETB C
case 0xd4: da_a(op); break; //DA A
case 0xd5: RWM=1; djnz_mem(op); RWM=0; break; //DJNZ data addr, code addr
case 0xd5: RWM = 1; djnz_mem(op); RWM = 0; break; //DJNZ data addr, code addr
case 0xd6:
case 0xd7: xchd_a_ir(op&1); break; //XCHD A, @R0/@R1
case 0xd7: xchd_a_ir(op & 1); break; //XCHD A, @R0/@R1
case 0xd8:
case 0xd9:
@ -1768,18 +1766,18 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0xdc:
case 0xdd:
case 0xde:
case 0xdf: djnz_r(op&7); break; //DJNZ R0 to R7,code addr
case 0xdf: djnz_r(op & 7); break; //DJNZ R0 to R7,code addr
case 0xe0: movx_a_idptr(op); break; //MOVX A,@DPTR
case 0xe1: ajmp(op); break; //AJMP code addr
case 0xe2:
case 0xe3: movx_a_ir(op&1); break; //MOVX A, @R0/@R1
case 0xe3: movx_a_ir(op & 1); break; //MOVX A, @R0/@R1
case 0xe4: clr_a(op); break; //CLR A
case 0xe5: mov_a_mem(op); break; //MOV A, data addr
case 0xe6:
case 0xe7: mov_a_ir(op&1); break; //MOV A,@RO/@R1
case 0xe7: mov_a_ir(op & 1); break; //MOV A,@RO/@R1
case 0xe8:
case 0xe9:
@ -1788,19 +1786,19 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0xec:
case 0xed:
case 0xee:
case 0xef: mov_a_r(op&7); break; //MOV A,R0 to R7
case 0xef: mov_a_r(op & 7); break; //MOV A,R0 to R7
case 0xf0: movx_idptr_a(op); break; //MOVX @DPTR,A
case 0xf1: acall(op); break; //ACALL code addr
case 0xf2:
case 0xf3: movx_ir_a(op&1); break; //MOVX @R0/@R1,A
case 0xf3: movx_ir_a(op & 1); break; //MOVX @R0/@R1,A
case 0xf4: cpl_a(op); break; //CPL A
case 0xf5: mov_mem_a(op); break; //MOV data addr, A
case 0xf6:
case 0xf7: mov_ir_a(op&1); break; //MOV @R0/@R1, A
case 0xf7: mov_ir_a(op & 1); break; //MOV @R0/@R1, A
case 0xf8:
case 0xf9:
@ -1809,7 +1807,7 @@ void mcs51_cpu_device::execute_op(uint8_t op)
case 0xfc:
case 0xfd:
case 0xfe:
case 0xff: mov_r_a(op&7); break; //MOV R0 to R7, A
case 0xff: mov_r_a(op & 7); break; //MOV R0 to R7, A
default:
illegal(op);
}
@ -1859,8 +1857,7 @@ const uint8_t mcs51_cpu_device::mcs51_cycles[256] =
**********************************************************************************/
void mcs51_cpu_device::check_irqs()
{
uint8_t ints = (GET_IE0 | (GET_TF0<<1) | (GET_IE1<<2) | (GET_TF1<<3)
| ((GET_RI|GET_TI)<<4));
uint8_t ints = (GET_IE0 | (GET_TF0 << 1) | (GET_IE1 << 2) | (GET_TF1 << 3) | ((GET_RI | GET_TI) << 4));
uint8_t int_vec = 0;
uint8_t int_mask;
int priority_request = -1;
@ -1869,14 +1866,14 @@ void mcs51_cpu_device::check_irqs()
int_mask = (GET_EA ? IE : 0x00);
if (m_features & FEATURE_I8052)
ints |= ((GET_TF2|GET_EXF2)<<5);
ints |= ((GET_TF2 | GET_EXF2) << 5);
if (m_features & FEATURE_DS5002FP)
{
ints |= ((GET_PFW)<<5);
ints |= ((GET_PFW) << 5);
m_irq_prio[6] = 3; /* force highest priority */
/* mask out interrupts not enabled */
ints &= ((int_mask & 0x1f) | ((GET_EPFW)<<5));
ints &= ((int_mask & 0x1f) | ((GET_EPFW) << 5));
}
else
{
@ -1904,14 +1901,14 @@ void mcs51_cpu_device::check_irqs()
if ((m_features & FEATURE_CMOS) && GET_PD)
return;
for (int i=0; i<m_num_interrupts; i++)
for (int i = 0; i < m_num_interrupts; i++)
{
if (ints & (1<<i))
if (ints & (1 << i))
{
if (m_irq_prio[i] > priority_request)
{
priority_request = m_irq_prio[i];
int_vec = (i<<3) | 3;
int_vec = (i << 3) | 3;
}
}
}
@ -1956,11 +1953,11 @@ void mcs51_cpu_device::check_irqs()
LOG("Take: %d %02x\n", m_cur_irq_prio, m_irq_active);
//Clear any interrupt flags that should be cleared since we're servicing the irq!
switch(int_vec)
switch (int_vec)
{
case V_IE0:
//External Int Flag only cleared when configured as Edge Triggered..
if(GET_IT0) /* for some reason having this, breaks alving dmd games */
if (GET_IT0) /* for some reason having this, breaks alving dmd games */
SET_IE0(0);
break;
case V_TF0:
@ -1969,7 +1966,7 @@ void mcs51_cpu_device::check_irqs()
break;
case V_IE1:
//External Int Flag only cleared when configured as Edge Triggered..
if(GET_IT1) /* for some reason having this, breaks alving dmd games */
if (GET_IT1) /* for some reason having this, breaks alving dmd games */
SET_IE1(0);
break;
case V_TF1:
@ -2025,7 +2022,7 @@ void mcs51_cpu_device::execute_set_input(int irqline, int state)
/* detect 0->1 transitions */
uint32_t tr_state = (~m_last_line_state) & new_state;
switch( irqline )
switch (irqline)
{
//External Interrupt 0
case MCS51_INT0_LINE:
@ -2057,7 +2054,7 @@ void mcs51_cpu_device::execute_set_input(int irqline, int state)
if (state != CLEAR_LINE)
{
//Need cleared->active line transition? (Logical 1-0 Pulse on the line) - CLEAR->ASSERT Transition since INT1 active lo!
if(GET_IT1)
if (GET_IT1)
{
if (GET_BIT(tr_state, MCS51_INT1_LINE))
SET_IE1(1);
@ -2428,11 +2425,11 @@ void mcs51_cpu_device::device_reset()
{
// set initial values (some of them are set using the bootstrap loader)
PCON = 0;
MCON = m_sfr_ram[ADDR_MCON-0x80];
RPCTL = m_sfr_ram[ADDR_RPCTL-0x80];
MCON = m_sfr_ram[ADDR_MCON - 0x80];
RPCTL = m_sfr_ram[ADDR_RPCTL - 0x80];
RPS = 0;
RNR = 0;
CRCR = m_sfr_ram[ADDR_CRCR-0x80];
CRCR = m_sfr_ram[ADDR_CRCR - 0x80];
CRCL = 0;
CRCH = 0;
TA = 0;
@ -2637,25 +2634,25 @@ Documentation states that having the battery connected "maintains the internal s
void ds5002fp_device::nvram_default()
{
memset( m_scratchpad, 0, 0x80 );
memset( m_sfr_ram, 0, 0x80 );
memset(m_scratchpad, 0, 0x80);
memset(m_sfr_ram, 0, 0x80);
int expected_bytes = 0x80 + 0x80;
if (!m_region.found())
{
logerror( "ds5002fp_device region not found\n" );
logerror("ds5002fp_device region not found\n");
}
else if( m_region->bytes() != expected_bytes )
else if (m_region->bytes() != expected_bytes)
{
logerror( "ds5002fp_device region length 0x%x expected 0x%x\n", m_region->bytes(), expected_bytes );
logerror("ds5002fp_device region length 0x%x expected 0x%x\n", m_region->bytes(), expected_bytes);
}
else
{
uint8_t *region = m_region->base();
memcpy( m_scratchpad, region, 0x80 ); region += 0x80;
memcpy( m_sfr_ram, region, 0x80 ); region += 0x80;
memcpy(m_scratchpad, region, 0x80); region += 0x80;
memcpy(m_sfr_ram, region, 0x80); region += 0x80;
/* does anything else need storing? any registers that aren't in sfr ram?
It isn't clear if the various initial MCON registers etc. are just stored in sfr ram
or if the DS5002FP stores them elsewhere and the bootstrap copies them */

210
src/devices/cpu/mcs51/mcs51ops.hxx
View File

@ -20,7 +20,7 @@ OPHANDLER( add_a_byte )
{
uint8_t data = ROP_ARG(PC++); //Grab data
uint8_t result = ACC + data; //Add data to accumulator
DO_ADD_FLAGS(ACC,data,0); //Set Flags
DO_ADD_FLAGS(ACC, data, 0); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -30,7 +30,7 @@ OPHANDLER( add_a_mem )
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = IRAM_R(addr); //Grab data from data address
uint8_t result = ACC + data; //Add data to accumulator
DO_ADD_FLAGS(ACC,data,0); //Set Flags
DO_ADD_FLAGS(ACC, data, 0); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -39,7 +39,7 @@ OPHANDLER( add_a_ir )
{
uint8_t data = IRAM_IR(R_REG(r)); //Grab data from memory pointed to by R0 or R1
uint8_t result = ACC + data; //Add data to accumulator
DO_ADD_FLAGS(ACC,data,0); //Set Flags
DO_ADD_FLAGS(ACC, data, 0); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -48,7 +48,7 @@ OPHANDLER( add_a_r )
{
uint8_t data = R_REG(r); //Grab data from R0 - R7
uint8_t result = ACC + data; //Add data to accumulator
DO_ADD_FLAGS(ACC,data,0); //Set Flags
DO_ADD_FLAGS(ACC, data, 0); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -57,7 +57,7 @@ OPHANDLER( addc_a_byte )
{
uint8_t data = ROP_ARG(PC++); //Grab data
uint8_t result = ACC + data + GET_CY; //Add data + carry flag to accumulator
DO_ADD_FLAGS(ACC,data,GET_CY); //Set Flags
DO_ADD_FLAGS(ACC, data, GET_CY); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -67,7 +67,7 @@ OPHANDLER( addc_a_mem )
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = IRAM_R(addr); //Grab data from data address
uint8_t result = ACC + data + GET_CY; //Add data + carry flag to accumulator
DO_ADD_FLAGS(ACC,data,GET_CY); //Set Flags
DO_ADD_FLAGS(ACC, data, GET_CY); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -76,7 +76,7 @@ OPHANDLER( addc_a_ir )
{
uint8_t data = IRAM_IR(R_REG(r)); //Grab data from memory pointed to by R0 or R1
uint8_t result = ACC + data + GET_CY; //Add data + carry flag to accumulator
DO_ADD_FLAGS(ACC,data,GET_CY); //Set Flags
DO_ADD_FLAGS(ACC, data, GET_CY); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -85,7 +85,7 @@ OPHANDLER( addc_a_r )
{
uint8_t data = R_REG(r); //Grab data from R0 - R7
uint8_t result = ACC + data + GET_CY; //Add data + carry flag to accumulator
DO_ADD_FLAGS(ACC,data,GET_CY); //Set Flags
DO_ADD_FLAGS(ACC, data, GET_CY); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -102,7 +102,7 @@ OPHANDLER( anl_mem_a )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = IRAM_R(addr); //Grab data from data address
IRAM_W(addr,data & ACC); //Set data address value to it's value Logical AND with ACC
IRAM_W(addr, data & ACC); //Set data address value to it's value Logical AND with ACC
}
//ANL data addr, #data /* 1: 0101 0011 */
@ -111,7 +111,7 @@ OPHANDLER( anl_mem_byte )
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = ROP_ARG(PC++); //Grab data
uint8_t srcdata = IRAM_R(addr); //Grab data from data address
IRAM_W(addr,srcdata & data); //Set data address value to it's value Logical AND with Data
IRAM_W(addr, srcdata & data); //Set data address value to it's value Logical AND with Data
}
//ANL A, #data /* 1: 0101 0100 */
@ -149,7 +149,7 @@ OPHANDLER( anl_c_bitaddr )
int cy = GET_CY;
uint8_t addr = ROP_ARG(PC++); //Grab bit address
uint8_t bit = BIT_R(addr); //Grab bit data from bit address
SET_CY( (cy & bit) ); //Set Carry flag to Carry Flag Value Logical AND with Bit
SET_CY(cy & bit); //Set Carry flag to Carry Flag Value Logical AND with Bit
}
//ANL C,/bit addr /* 1: 1011 0000 */
@ -158,8 +158,8 @@ OPHANDLER( anl_c_nbitaddr )
int cy = GET_CY;
uint8_t addr = ROP_ARG(PC++); //Grab bit address
uint8_t bit = BIT_R(addr); //Grab bit data from bit address
bit = ((~bit)&1); //Complement bit
SET_CY( (cy & bit) ); //Set Carry flag to Carry Flag Value Logical AND with Complemented Bit
bit = (~bit & 1); //Complement bit
SET_CY(cy & bit); //Set Carry flag to Carry Flag Value Logical AND with Complemented Bit
}
//CJNE A, #data, code addr /* 1: 1011 0100 */
@ -168,13 +168,13 @@ OPHANDLER( cjne_a_byte )
uint8_t data = ROP_ARG(PC++); //Grab data
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
if(ACC != data) //Jump if values are not equal
if (ACC != data) //Jump if values are not equal
{
PC = PC + rel_addr;
}
//Set carry flag to 1 if 1st compare value is < 2nd compare value
SET_CY( (ACC < data) );
SET_CY(ACC < data);
}
//CJNE A, data addr, code addr /* 1: 1011 0101 */
@ -184,13 +184,13 @@ OPHANDLER( cjne_a_mem )
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
uint8_t data = IRAM_R(addr); //Pull value from data address
if(ACC != data) //Jump if values are not equal
if (ACC != data) //Jump if values are not equal
{
PC = PC + rel_addr;
}
//Set carry flag to 1 if 1st compare value is < 2nd compare value
SET_CY( (ACC < data) );
SET_CY(ACC < data);
}
//CJNE @R0/@R1, #data, code addr /* 1: 1011 011i */
@ -200,13 +200,13 @@ OPHANDLER( cjne_ir_byte )
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
uint8_t srcdata = IRAM_IR(R_REG(r)); //Grab value pointed to by R0 or R1
if(srcdata != data) //Jump if values are not equal
if (srcdata != data) //Jump if values are not equal
{
PC = PC + rel_addr;
}
//Set carry flag to 1 if 1st compare value is < 2nd compare value
SET_CY( (srcdata < data) );
SET_CY(srcdata < data);
}
//CJNE R0 to R7, #data, code addr /* 1: 1011 1rrr */
@ -216,20 +216,20 @@ OPHANDLER( cjne_r_byte )
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
uint8_t srcdata = R_REG(r); //Grab value of R0 - R7
if(srcdata != data) //Jump if values are not equal
if (srcdata != data) //Jump if values are not equal
{
PC = PC + rel_addr;
}
//Set carry flag to 1 if 1st compare value is < 2nd compare value
SET_CY( (srcdata < data) );
SET_CY(srcdata < data);
}
//CLR bit addr /* 1: 1100 0010 */
OPHANDLER( clr_bitaddr )
{
uint8_t addr = ROP_ARG(PC++); //Grab bit address
BIT_W(addr,0); //Clear bit at specified bit address
BIT_W(addr, 0); //Clear bit at specified bit address
}
//CLR C /* 1: 1100 0011 */
@ -248,21 +248,21 @@ OPHANDLER( clr_a )
OPHANDLER( cpl_bitaddr )
{
uint8_t addr = ROP_ARG(PC++); //Grab bit address
uint8_t data = (~BIT_R(addr))&1;
BIT_W(addr,data); //Complement bit at specified bit address
uint8_t data = (~BIT_R(addr)) & 1;
BIT_W(addr, data); //Complement bit at specified bit address
}
//CPL C /* 1: 1011 0011 */
OPHANDLER( cpl_c )
{
uint8_t bit = (~GET_CY)&1; //Complement Carry Flag
uint8_t bit = (~GET_CY) & 1; //Complement Carry Flag
SET_CY(bit);
}
//CPL A /* 1: 1111 0100 */
OPHANDLER( cpl_a )
{
uint8_t data = ((~ACC)&0xff);
uint8_t data = ((~ACC) & 0xff);
SET_ACC(data); //Complement Accumulator
}
@ -278,19 +278,19 @@ OPHANDLER( da_a )
The carry flag will be set if the result is > 0x99, but not cleared otherwise */
uint16_t new_acc = ACC & 0xff;
if(GET_AC || (new_acc & 0x0f) > 0x09)
if (GET_AC || (new_acc & 0x0f) > 0x09)
new_acc += 0x06;
if(GET_CY || ((new_acc & 0xf0) > 0x90) || (new_acc & ~0xff))
if (GET_CY || ((new_acc & 0xf0) > 0x90) || (new_acc & ~0xff))
new_acc += 0x60;
SET_ACC(new_acc&0xff);
if(new_acc & ~0xff)
SET_ACC(new_acc & 0xff);
if (new_acc & ~0xff)
SET_CY(1);
}
//DEC A /* 1: 0001 0100 */
OPHANDLER( dec_a )
{
SET_ACC(ACC-1);
SET_ACC(ACC - 1);
}
//DEC data addr /* 1: 0001 0101 */
@ -298,14 +298,14 @@ OPHANDLER( dec_mem )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = IRAM_R(addr);
IRAM_W(addr,data-1);
IRAM_W(addr, data - 1);
}
//DEC @R0/@R1 /* 1: 0001 011i */
OPHANDLER( dec_ir )
{
uint8_t data = IRAM_IR(R_REG(r));
IRAM_IW(R_REG(r),data-1);
IRAM_IW(R_REG(r), data - 1);
}
//DEC R0 to R7 /* 1: 0001 1rrr */
@ -317,14 +317,16 @@ OPHANDLER( dec_r )
//DIV AB /* 1: 1000 0100 */
OPHANDLER( div_ab )
{
if( B == 0 ) {
if (B == 0)
{
//Overflow flag is set!
SET_OV(1);
//Really the values are undefined according to the manual, but we'll just leave them as is..
//SET_ACC(0xff);
//SFR_W(B,0xff);
//SFR_W(B, 0xff);
}
else {
else
{
int a = (int)ACC / B;
int b = (int)ACC % B;
//A gets quotient byte, B gets remainder byte
@ -342,8 +344,8 @@ OPHANDLER( djnz_mem )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
IRAM_W(addr,IRAM_R(addr) - 1); //Decrement value contained at data address
if(IRAM_R(addr) != 0) //Branch if contents of data address is not 0
IRAM_W(addr, IRAM_R(addr) - 1); //Decrement value contained at data address
if (IRAM_R(addr) != 0) //Branch if contents of data address is not 0
{
PC = PC + rel_addr;
}
@ -353,8 +355,8 @@ OPHANDLER( djnz_mem )
OPHANDLER( djnz_r )
{
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
SET_REG(r ,R_REG(r) - 1); //Decrement value
if(R_REG(r) != 0) //Branch if contents of R0 - R7 is not 0
SET_REG(r, R_REG(r) - 1); //Decrement value
if (R_REG(r) != 0) //Branch if contents of R0 - R7 is not 0
{
PC = PC + rel_addr;
}
@ -363,7 +365,7 @@ OPHANDLER( djnz_r )
//INC A /* 1: 0000 0100 */
OPHANDLER( inc_a )
{
SET_ACC(ACC+1);
SET_ACC(ACC + 1);
}
//INC data addr /* 1: 0000 0101 */
@ -371,14 +373,14 @@ OPHANDLER( inc_mem )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = IRAM_R(addr);
IRAM_W(addr,data+1);
IRAM_W(addr, data + 1);
}
//INC @R0/@R1 /* 1: 0000 011i */
OPHANDLER( inc_ir )
{
uint8_t data = IRAM_IR(R_REG(r));
IRAM_IW(R_REG(r),data+1);
IRAM_IW(R_REG(r), data + 1);
}
//INC R0 to R7 /* 1: 0000 1rrr */
@ -391,7 +393,7 @@ OPHANDLER( inc_r )
//INC DPTR /* 1: 1010 0011 */
OPHANDLER( inc_dptr )
{
uint16_t dptr = (DPTR)+1;
uint16_t dptr = (DPTR) + 1;
SET_DPTR(dptr);
}
@ -400,7 +402,7 @@ OPHANDLER( jb )
{
uint8_t addr = ROP_ARG(PC++); //Grab bit address
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
if(BIT_R(addr)) //If bit set at specified bit address, jump
if (BIT_R(addr)) //If bit set at specified bit address, jump
{
PC = PC + rel_addr;
}
@ -411,9 +413,10 @@ OPHANDLER( jbc )
{
uint8_t addr = ROP_ARG(PC++); //Grab bit address
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
if(BIT_R(addr)) { //If bit set at specified bit address, jump
if (BIT_R(addr)) //If bit set at specified bit address, jump
{
PC = PC + rel_addr;
BIT_W(addr,0); //Clear Bit also
BIT_W(addr, 0); //Clear Bit also
}
}
@ -421,7 +424,7 @@ OPHANDLER( jbc )
OPHANDLER( jc )
{
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
if(GET_CY) //Jump if Carry Flag Set
if (GET_CY) //Jump if Carry Flag Set
{
PC = PC + rel_addr;
}
@ -438,7 +441,7 @@ OPHANDLER( jnb )
{
uint8_t addr = ROP_ARG(PC++); //Grab bit address
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
if(!BIT_R(addr)) //If bit NOT set at specified bit address, jump
if (!BIT_R(addr)) //If bit NOT set at specified bit address, jump
{
PC = PC + rel_addr;
}
@ -448,7 +451,7 @@ OPHANDLER( jnb )
OPHANDLER( jnc )
{
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
if(!GET_CY) //Jump if Carry Flag not set
if (!GET_CY) //Jump if Carry Flag not set
{
PC = PC + rel_addr;
}
@ -458,9 +461,9 @@ OPHANDLER( jnc )
OPHANDLER( jnz )
{
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
if(ACC != 0) //Branch if ACC is not 0
if (ACC != 0) //Branch if ACC is not 0
{
PC = PC+rel_addr;
PC = PC + rel_addr;
}
}
@ -468,9 +471,9 @@ OPHANDLER( jnz )
OPHANDLER( jz )
{
int8_t rel_addr = ROP_ARG(PC++); //Grab relative code address
if(ACC == 0) //Branch if ACC is 0
if (ACC == 0) //Branch if ACC is 0
{
PC = PC+rel_addr;
PC = PC + rel_addr;
}
}
@ -481,7 +484,7 @@ OPHANDLER( lcall )
addr_hi = ROP_ARG(PC++);
addr_lo = ROP_ARG(PC++);
PUSH_PC();
PC = (uint16_t)((addr_hi<<8) | addr_lo);
PC = (uint16_t)((addr_hi << 8) | addr_lo);
}
//LJMP code addr /* 1: 0000 0010 */
@ -490,7 +493,7 @@ OPHANDLER( ljmp )
uint8_t addr_hi, addr_lo;
addr_hi = ROP_ARG(PC++);
addr_lo = ROP_ARG(PC++);
PC = (uint16_t)((addr_hi<<8) | addr_lo);
PC = (uint16_t)((addr_hi << 8) | addr_lo);
}
//MOV A, #data /* 1: 0111 0100 */
@ -524,7 +527,7 @@ OPHANDLER( mov_mem_byte )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = ROP_ARG(PC++); //Grab data
IRAM_W(addr,data); //Store data to data address location
IRAM_W(addr, data); //Store data to data address location
}
//MOV data addr, data addr /* 1: 1000 0101 */
@ -534,14 +537,14 @@ OPHANDLER( mov_mem_mem )
uint8_t src,dst;
src = ROP_ARG(PC++); //Grab source data address
dst = ROP_ARG(PC++); //Grab destination data address
IRAM_W(dst,IRAM_R(src)); //Read source address contents and store to destination address
IRAM_W(dst, IRAM_R(src)); //Read source address contents and store to destination address
}
//MOV @R0/@R1, #data /* 1: 0111 011i */
OPHANDLER( mov_ir_byte )
{
uint8_t data = ROP_ARG(PC++); //Grab data
IRAM_IW(R_REG(r),data); //Store data to address pointed by R0 or R1
IRAM_IW(R_REG(r), data); //Store data to address pointed by R0 or R1
}
//MOV R0 to R7, #data /* 1: 0111 1rrr */
@ -555,14 +558,14 @@ OPHANDLER( mov_r_byte )
OPHANDLER( mov_mem_ir )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
IRAM_W(addr,IRAM_IR(R_REG(r))); //Store contents pointed to by R0 or R1 to data address
IRAM_W(addr, IRAM_IR(R_REG(r))); //Store contents pointed to by R0 or R1 to data address
}
//MOV data addr,R0 to R7 /* 1: 1000 1rrr */
OPHANDLER( mov_mem_r )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
IRAM_W(addr,R_REG(r)); //Store contents of R0 - R7 to data address
IRAM_W(addr, R_REG(r)); //Store contents of R0 - R7 to data address
}
//MOV DPTR, #data16 /* 1: 1001 0000 */
@ -571,21 +574,21 @@ OPHANDLER( mov_dptr_byte )
uint8_t data_hi, data_lo;
data_hi = ROP_ARG(PC++); //Grab hi byte
data_lo = ROP_ARG(PC++); //Grab lo byte
SET_DPTR((uint16_t)((data_hi<<8)|data_lo)); //Store to DPTR
SET_DPTR((uint16_t)((data_hi << 8) | data_lo)); //Store to DPTR
}
//MOV bit addr, C /* 1: 1001 0010 */
OPHANDLER( mov_bitaddr_c )
{
uint8_t addr = ROP_ARG(PC++); //Grab bit address
BIT_W(addr,GET_CY); //Store Carry Flag to Bit Address
BIT_W(addr, GET_CY); //Store Carry Flag to Bit Address
}
//MOV @R0/@R1, data addr /* 1: 1010 011i */
OPHANDLER( mov_ir_mem )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
IRAM_IW(R_REG(r),IRAM_R(addr)); //Store data from data address to address pointed to by R0 or R1
IRAM_IW(R_REG(r), IRAM_R(addr)); //Store data from data address to address pointed to by R0 or R1
}
//MOV R0 to R7, data addr /* 1: 1010 1rrr */
@ -599,13 +602,13 @@ OPHANDLER( mov_r_mem )
OPHANDLER( mov_mem_a )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
IRAM_W(addr,ACC); //Store A to data address
IRAM_W(addr, ACC); //Store A to data address
}
//MOV @R0/@R1, A /* 1: 1111 011i */
OPHANDLER( mov_ir_a )
{
IRAM_IW(R_REG(r),ACC); //Store A to location pointed to by R0 or R1
IRAM_IW(R_REG(r), ACC); //Store A to location pointed to by R0 or R1
}
//MOV R0 to R7, A /* 1: 1111 1rrr */
@ -618,7 +621,7 @@ OPHANDLER( mov_r_a )
OPHANDLER( movc_a_iapc )
{
uint8_t data;
data = CODEMEM_R(ACC+PC); //Move a byte from CODE(Program) Memory and store to ACC
data = CODEMEM_R(ACC + PC); //Move a byte from CODE(Program) Memory and store to ACC
SET_ACC(data);
}
@ -626,7 +629,7 @@ OPHANDLER( movc_a_iapc )
OPHANDLER( mov_c_bitaddr )
{
uint8_t addr = ROP_ARG(PC++); //Grab bit address
SET_CY( (BIT_R(addr)) ); //Store Bit from Bit Address to Carry Flag
SET_CY(BIT_R(addr)); //Store Bit from Bit Address to Carry Flag
}
//MOVC A, @A + DPTR /* 1: 1001 0011 */
@ -642,7 +645,7 @@ OPHANDLER( movc_a_iadptr )
OPHANDLER( movx_a_idptr )
{
// uint8_t byte = DATAMEM_R(R_DPTR); //Grab 1 byte from External DATA memory pointed to by dptr
uint32_t addr = ERAM_ADDR(DPTR, 0xFFFF);
uint32_t addr = ERAM_ADDR(DPTR, 0xffff);
uint8_t byte = DATAMEM_R(addr); //Grab 1 byte from External DATA memory pointed to by dptr
SET_ACC(byte); //Store to ACC
}
@ -651,7 +654,7 @@ OPHANDLER( movx_a_idptr )
//(Move External Ram 8 bit address to A)
OPHANDLER( movx_a_ir )
{
uint32_t addr = ERAM_ADDR(R_REG(r),0xFF); //Grab address by reading location pointed to by R0 or R1
uint32_t addr = ERAM_ADDR(R_REG(r), 0xff); //Grab address by reading location pointed to by R0 or R1
uint8_t byte = DATAMEM_R(addr); //Grab 1 byte from External DATA memory pointed to by address
SET_ACC(byte); //Store to ACC
}
@ -661,7 +664,7 @@ OPHANDLER( movx_a_ir )
OPHANDLER( movx_idptr_a )
{
// DATAMEM_W(R_DPTR, ACC); //Store ACC to External DATA memory address pointed to by DPTR
uint32_t addr = ERAM_ADDR(DPTR, 0xFFFF);
uint32_t addr = ERAM_ADDR(DPTR, 0xffff);
DATAMEM_W(addr, ACC); //Store ACC to External DATA memory address pointed to by DPTR
}
@ -669,7 +672,7 @@ OPHANDLER( movx_idptr_a )
//(Move A to External Ram 8 bit address)
OPHANDLER( movx_ir_a )
{
uint32_t addr = ERAM_ADDR(R_REG(r),0xFF); //Grab address by reading location pointed to by R0 or R1
uint32_t addr = ERAM_ADDR(R_REG(r), 0xff); //Grab address by reading location pointed to by R0 or R1
DATAMEM_W(addr, ACC); //Store ACC to External DATA memory address
}
@ -678,10 +681,10 @@ OPHANDLER( mul_ab )
{
uint16_t result = ACC * B;
//A gets lo bits, B gets hi bits of result
B = (uint8_t) ((result & 0xFF00) >> 8);
SET_ACC((uint8_t)(result & 0x00FF));
B = (uint8_t)((result & 0xff00) >> 8);
SET_ACC((uint8_t)(result & 0x00ff));
//Set flags
SET_OV( ((result & 0x100) >> 8) ); //Set/Clear Overflow Flag if result > 255
SET_OV((result & 0x100) >> 8); //Set/Clear Overflow Flag if result > 255
SET_CY(0); //Carry Flag always cleared
}
@ -695,7 +698,7 @@ OPHANDLER( orl_mem_a )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = IRAM_R(addr); //Grab data from data address
IRAM_W(addr,data | ACC); //Set data address value to it's value Logical OR with ACC
IRAM_W(addr, data | ACC); //Set data address value to it's value Logical OR with ACC
}
//ORL data addr, #data /* 1: 0100 0011 */
@ -704,7 +707,7 @@ OPHANDLER( orl_mem_byte )
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = ROP_ARG(PC++); //Grab data
uint8_t srcdata = IRAM_R(addr); //Grab data from data address
IRAM_W(addr,srcdata | data); //Set data address value to it's value Logical OR with Data
IRAM_W(addr, srcdata | data); //Set data address value to it's value Logical OR with Data
}
//ORL A, #data /* 1: 0100 0100 */
@ -742,7 +745,7 @@ OPHANDLER( orl_c_bitaddr )
int cy = GET_CY;
uint8_t addr = ROP_ARG(PC++); //Grab bit address
uint8_t bit = BIT_R(addr); //Grab bit data from bit address
SET_CY( (cy | bit) ); //Set Carry flag to Carry Flag Value Logical OR with Bit
SET_CY(cy | bit); //Set Carry flag to Carry Flag Value Logical OR with Bit
}
//ORL C, /bit addr /* 1: 1010 0000 */
@ -751,8 +754,8 @@ OPHANDLER( orl_c_nbitaddr )
int cy = GET_CY;
uint8_t addr = ROP_ARG(PC++); //Grab bit address
uint8_t bit = BIT_R(addr); //Grab bit data from bit address
bit = ((~bit)&1); //Complement bit
SET_CY( (cy | bit) ); //Set Carry flag to Carry Flag Value Logical OR with Complemented Bit
bit = (~bit & 1); //Complement bit
SET_CY(cy | bit); //Set Carry flag to Carry Flag Value Logical OR with Complemented Bit
}
//POP data addr /* 1: 1101 0000 */
@ -761,14 +764,14 @@ OPHANDLER( pop )
uint8_t addr = ROP_ARG(PC++); //Grab data address
IRAM_W(addr, IRAM_IR(SP)); //Store to contents of data addr, data pointed to by Stack - IRAM_IR needed to access upper 128 bytes of stack
//IRAM_IW(addr, IRAM_IR(R_SP)); //Store to contents of data addr, data pointed to by Stack - doesn't work, sfr's are not restored this way and it's not an indirect access anyway
SP = SP-1; //Decrement SP
SP = SP - 1; //Decrement SP
}
//PUSH data addr /* 1: 1100 0000 */
OPHANDLER( push )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t tmpSP = SP+1; //Grab and Increment Stack Pointer
uint8_t tmpSP = SP + 1; //Grab and Increment Stack Pointer
SP = tmpSP; // ""
IRAM_IW(tmpSP, IRAM_R(addr)); //Store to stack contents of data address - IRAM_IW needed to store to upper 128 bytes of stack, however, can't use IRAM_IR because that won't store the sfrs and it's not an indirect access anyway
}
@ -791,8 +794,8 @@ OPHANDLER( rl_a )
{
//Left Shift A, Bit 7 carries to Bit 0
int carry = ((ACC & 0x80) >> 7);
int data = (ACC<<1) & 0xfe;
SET_ACC( data | carry);
int data = (ACC << 1) & 0xfe;
SET_ACC(data | carry);
}
//RLC A /* 1: 0011 0011 */
@ -800,8 +803,8 @@ OPHANDLER( rlc_a )
{
//Left Shift A, Bit 7 goes to Carry Flag, Original Carry Flag goes to Bit 0 of ACC
int carry = ((ACC & 0x80) >> 7);
int data = ((ACC<<1) & 0xfe) | GET_CY;
SET_ACC( data);
int data = ((ACC << 1) & 0xfe) | GET_CY;
SET_ACC(data);
SET_CY(carry);
}
@ -810,8 +813,8 @@ OPHANDLER( rr_a )
{
//Right Shift A, Bit 0 carries to Bit 7
int carry = ((ACC & 1) << 7);
int data = (ACC>>1) & 0x7f;
SET_ACC( data | carry);
int data = (ACC >> 1) & 0x7f;
SET_ACC(data | carry);
}
//RRC A /* 1: 0001 0011 */
@ -819,22 +822,23 @@ OPHANDLER( rrc_a )
{
//Right Shift A, Bit 0 goes to Carry Flag, Bit 7 of ACC gets set to original Carry Flag
int carry = (ACC & 1);
int data = ((ACC>>1) & 0x7f) | (GET_CY<<7);
SET_ACC( data);
int data = ((ACC >> 1) & 0x7f) | (GET_CY << 7);
SET_ACC(data);
SET_CY(carry);
}
//SETB C /* 1: 1101 0011 */
OPHANDLER( setb_c )
{
SET_CY(1); //Set Carry Flag
//Set Carry Flag
SET_CY(1);
}
//SETB bit addr /* 1: 1101 0010 */
OPHANDLER( setb_bitaddr )
{
uint8_t addr = ROP_ARG(PC++); //Grab bit address
BIT_W(addr,1); //Set Bit at Bit Address
BIT_W(addr, 1); //Set Bit at Bit Address
}
//SJMP code addr /* 1: 1000 0000 */
@ -849,7 +853,7 @@ OPHANDLER( subb_a_byte )
{
uint8_t data = ROP_ARG(PC++); //Grab data
uint8_t result = ACC - data - GET_CY; //Subtract data & carry flag from accumulator
DO_SUB_FLAGS(ACC,data,GET_CY); //Set Flags
DO_SUB_FLAGS(ACC, data, GET_CY); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -860,7 +864,7 @@ OPHANDLER( subb_a_mem )
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = IRAM_R(addr); //Grab data from data address
uint8_t result = ACC - data - GET_CY; //Subtract data & carry flag from accumulator
DO_SUB_FLAGS(ACC,data,GET_CY); //Set Flags
DO_SUB_FLAGS(ACC, data, GET_CY); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -869,7 +873,7 @@ OPHANDLER( subb_a_ir )
{
uint8_t data = IRAM_IR(R_REG(r)); //Grab data from memory pointed to by R0 or R1
uint8_t result = ACC - data - GET_CY; //Subtract data & carry flag from accumulator
DO_SUB_FLAGS(ACC,data,GET_CY); //Set Flags
DO_SUB_FLAGS(ACC, data, GET_CY); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -878,7 +882,7 @@ OPHANDLER( subb_a_r )
{
uint8_t data = R_REG(r); //Grab data from R0 - R7
uint8_t result = ACC - data - GET_CY; //Subtract data & carry flag from accumulator
DO_SUB_FLAGS(ACC,data,GET_CY); //Set Flags
DO_SUB_FLAGS(ACC, data, GET_CY); //Set Flags
SET_ACC(result); //Store 8 bit result of addtion in ACC
}
@ -888,7 +892,7 @@ OPHANDLER( swap_a )
uint8_t a_nib_lo, a_nib_hi;
a_nib_hi = (ACC & 0x0f) << 4; //Grab lo byte of ACC and move to hi
a_nib_lo = (ACC & 0xf0) >> 4; //Grab hi byte of ACC and move to lo
SET_ACC( a_nib_hi | a_nib_lo);
SET_ACC(a_nib_hi | a_nib_lo);
}
//XCH A, data addr /* 1: 1100 0101 */
@ -898,7 +902,7 @@ OPHANDLER( xch_a_mem )
uint8_t data = IRAM_R(addr); //Grab data
uint8_t oldACC = ACC; //Hold value of ACC
SET_ACC(data); //Sets ACC to data
IRAM_W(addr,oldACC); //Sets data address to old value of ACC
IRAM_W(addr, oldACC); //Sets data address to old value of ACC
}
//XCH A, @RO/@R1 /* 1: 1100 011i */
@ -907,7 +911,7 @@ OPHANDLER( xch_a_ir )
uint8_t data = IRAM_IR(R_REG(r)); //Grab data pointed to by R0 or R1
uint8_t oldACC = ACC; //Hold value of ACC
SET_ACC(data); //Sets ACC to data
IRAM_IW(R_REG(r),oldACC); //Sets data address to old value of ACC
IRAM_IW(R_REG(r), oldACC); //Sets data address to old value of ACC
}
//XCH A, RO to R7 /* 1: 1100 1rrr */
@ -925,8 +929,8 @@ OPHANDLER( xchd_a_ir )
uint8_t acc, ir_data;
ir_data = IRAM_IR(R_REG(r)); //Grab data pointed to by R0 or R1
acc = ACC; //Grab ACC value
SET_ACC( (acc & 0xf0) | (ir_data & 0x0f) ); //Set ACC to lower nibble of data pointed to by R0 or R1
IRAM_W(R_REG(r), (ir_data & 0xf0) | (acc & 0x0f) ); //Set data pointed to by R0 or R1 to lower nibble of ACC
SET_ACC((acc & 0xf0) | (ir_data & 0x0f)); //Set ACC to lower nibble of data pointed to by R0 or R1
IRAM_W(R_REG(r), (ir_data & 0xf0) | (acc & 0x0f)); //Set data pointed to by R0 or R1 to lower nibble of ACC
}
//XRL data addr, A /* 1: 0110 0010 */
@ -934,7 +938,7 @@ OPHANDLER( xrl_mem_a )
{
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = IRAM_R(addr); //Grab data from data address
IRAM_W(addr,data ^ ACC); //Set data address value to it's value Logical XOR with ACC
IRAM_W(addr, data ^ ACC); //Set data address value to it's value Logical XOR with ACC
}
//XRL data addr, #data /* 1: 0110 0011 */
@ -943,7 +947,7 @@ OPHANDLER( xrl_mem_byte )
uint8_t addr = ROP_ARG(PC++); //Grab data address
uint8_t data = ROP_ARG(PC++); //Grab data
uint8_t srcdata = IRAM_R(addr); //Grab data from data address
IRAM_W(addr,srcdata ^ data); //Set data address value to it's value Logical XOR with Data
IRAM_W(addr, srcdata ^ data); //Set data address value to it's value Logical XOR with Data
}
//XRL A, #data /* 1: 0110 0100 */