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https://github.com/holub/mame
synced 2025-05-05 22:04:43 +03:00
smc91c9x: Switch from queue to vector for save state support. (nw)
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9f9310b44d
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@ -126,6 +126,10 @@ void smc91c9x_device::device_start()
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m_irq_handler.resolve_safe();
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// Set completion queues to max size to save properly
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m_comp_rx.resize(ETHER_BUFFERS);
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m_comp_tx.resize(ETHER_BUFFERS);
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/* register ide states */
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save_item(NAME(m_reg));
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save_item(NAME(m_regmask));
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@ -135,9 +139,8 @@ void smc91c9x_device::device_start()
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save_item(NAME(m_recd));
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save_item(NAME(m_alloc_rx));
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save_item(NAME(m_alloc_tx));
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// TODO: Need to save these
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//save_item(NAME(m_comp_rx));
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//save_item(NAME(m_comp_tx));
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save_item(NAME(m_comp_rx));
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save_item(NAME(m_comp_tx));
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}
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//-------------------------------------------------
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@ -222,11 +225,10 @@ void smc91c9x_device::mmu_reset()
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// Reset MMU allocations
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m_alloc_rx = 0;
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m_alloc_tx = 0;
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// Reset completion FIFOs
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while (!m_comp_tx.empty())
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m_comp_tx.pop();
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while (!m_comp_rx.empty())
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m_comp_rx.pop();
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m_comp_tx.clear();
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m_comp_rx.clear();
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// Flush fifos.
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clear_tx_fifo();
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@ -426,7 +428,7 @@ void smc91c9x_device::recv_cb(uint8_t *data, int length)
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packet[3] = (dst) >> 8;
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// Push packet number to rx completion fifo
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m_comp_rx.push(packet_num);
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m_comp_rx.push_back(packet_num);
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}
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else
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{
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@ -627,7 +629,7 @@ void smc91c9x_device::process_command(uint16_t data)
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case ECMD_REMOVE_TOPFRAME_TX:
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LOG(" REMOVE FRAME FROM TX FIFO\n");
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m_comp_tx.pop();
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m_comp_tx.erase(m_comp_tx.begin());
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// TODO: Should we clear TX_INT?
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break;
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@ -639,7 +641,7 @@ void smc91c9x_device::process_command(uint16_t data)
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case ECMD_REMOVE_TOPFRAME_RX:
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LOG(" REMOVE FRAME FROM RX FIFO\n");
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// remove entry from rx queue
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m_comp_rx.pop();
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m_comp_rx.erase(m_comp_rx.begin());
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update_ethernet_irq();
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m_recd++;
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@ -661,7 +663,7 @@ void smc91c9x_device::process_command(uint16_t data)
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{
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const int packet_number = m_reg[EREG_PNR_ARR] & 0xff;
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// Push packet number tx completion fifo
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m_comp_tx.push(packet_number);
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m_comp_tx.push_back(packet_number);
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m_tx_timer->adjust(attotime::from_usec(10));
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}
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break;
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@ -873,7 +875,7 @@ WRITE16_MEMBER( smc91c9x_device::write )
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case EREG_INTERRUPT:
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// Pop tx fifo packet from completion fifo if clear tx int is set
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if (m_reg[EREG_INTERRUPT] & data & EINT_TX) {
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m_comp_tx.pop();
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m_comp_tx.erase(m_comp_tx.begin());
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m_reg[EREG_INTERRUPT] &= ~EINT_TX;
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}
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m_reg[EREG_INTERRUPT] &= ~(data & 0x56);
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@ -11,8 +11,6 @@
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#ifndef MAME_MACHINE_SMC91C9X_H
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#define MAME_MACHINE_SMC91C9X_H
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#include <queue>
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/***************************************************************************
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TYPE DEFINITIONS
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***************************************************************************/
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@ -45,7 +43,7 @@ private:
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// mmu
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// The bits in these vectors indicate a packet has been allocated
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u32 m_alloc_rx, m_alloc_tx;
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std::queue<int> m_comp_tx, m_comp_rx;
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std::vector<int> m_comp_tx, m_comp_rx;
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// Requests a packet allocation and returns true
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// and sets the packet number if successful
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bool alloc_req(const int tx, int &packet_num);
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