From d7f1b7ae495a2855e022e5d6e1758fd80f3df86e Mon Sep 17 00:00:00 2001 From: MetalliC <0vetal0@gmail.com> Date: Thu, 24 Oct 2019 01:24:38 +0300 Subject: [PATCH] few notes (nw) --- src/mame/drivers/cps3.cpp | 2 +- src/mame/drivers/cv1k.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mame/drivers/cps3.cpp b/src/mame/drivers/cps3.cpp index cea86300d50..fac2c927a22 100644 --- a/src/mame/drivers/cps3.cpp +++ b/src/mame/drivers/cps3.cpp @@ -428,7 +428,7 @@ Notes: 29F400 - Fujitsu 29F400TA-90PFTN 512k x8 FlashROM (TSOP48) Custom ASIC - CAPCOM DL-3229 SCU (QFP144). Decapping reveals this is a Hitachi HD6417099 SH2 variant with built-in encryption, clocked at 6.250MHz - FM1208S - RAMTRON FM1208S 4k (512bytes x8) Nonvolatile Ferroelectric RAM (not populated) + FM1208S - RAMTRON FM1208S 4k (512bytes x8) Nonvolatile Ferroelectric RAM (not populated on type D boards) MACH111 - AMD MACH111 CPLD stamped 'CP3B1A' (PLCC44) * - These components located on the other side of the PCB diff --git a/src/mame/drivers/cv1k.cpp b/src/mame/drivers/cv1k.cpp index 3b6c65b0de8..9180342ed1e 100644 --- a/src/mame/drivers/cv1k.cpp +++ b/src/mame/drivers/cv1k.cpp @@ -472,7 +472,7 @@ void cv1k_state::cv1k(machine_config &config) m_maincpu->set_sh4_clock(12.8_MHz_XTAL*8); // 102.4MHz m_maincpu->set_addrmap(AS_PROGRAM, &cv1k_state::cv1k_map); m_maincpu->set_addrmap(AS_IO, &cv1k_state::cv1k_port); - m_maincpu->set_vblank_int("screen", FUNC(cv1k_state::irq2_line_hold)); + m_maincpu->set_vblank_int("screen", FUNC(cv1k_state::irq2_line_hold)); // irq2 actually asserted at V-sync pulse, not at V-blank RTC9701(config, m_eeprom); SERFLASH(config, m_serflash, 0);