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https://github.com/holub/mame
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im01: add bus error
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@ -17,11 +17,6 @@ TODO:
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around 1.1 times faster, maybe К1801ВМ1 internal timing differs from T11,
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and/or T11 core timing itself is not 100% accurate.
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- verify actual XTAL, the label couldn't be seen
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- Bus conflict between RAM and I/O is not understood, ИМ-01(not Т) is picky
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about it. It expects RAM 0x003f to be non-0, which only gets set in the
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hardware bus error trap routine. But that routine also overwrites the stack,
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so I don't think that's it. Another hint that points to a bus conflict is
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that the game clears RAM 0x003e before reading inputs.
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- is ИМ-01Т extra RAM chip used at all?
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*******************************************************************************
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@ -80,7 +75,6 @@ public:
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m_maincpu(*this, "maincpu"),
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m_display(*this, "display"),
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m_dac(*this, "dac"),
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m_ram(*this, "ram"),
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m_inputs(*this, "IN.%u", 0)
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{ }
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@ -94,7 +88,6 @@ private:
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required_device<t11_device> m_maincpu;
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required_device<pwm_display_device> m_display;
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required_device<dac_bit_interface> m_dac;
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required_shared_ptr<u16> m_ram;
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required_ioport_array<6> m_inputs;
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void main_map(address_map &map);
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@ -109,7 +102,7 @@ private:
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u16 digit_r(offs_t offset, u16 mem_mask);
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void digit_w(offs_t offset, u16 data, u16 mem_mask);
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u16 input_r(offs_t offset, u16 mem_mask);
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u16 conflict_r(offs_t offset, u16 mem_mask);
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void error_w(offs_t offset, u16 data, u16 mem_mask);
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u16 m_inp_mux = 0;
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u16 m_digit_data = 0;
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@ -194,11 +187,10 @@ u16 im01_state::input_r(offs_t offset, u16 mem_mask)
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return data << 8;
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}
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u16 im01_state::conflict_r(offs_t offset, u16 mem_mask)
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void im01_state::error_w(offs_t offset, u16 data, u16 mem_mask)
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{
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// bus conflict between RAM and I/O
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u16 conflict = (offset >= 0x18 && offset < 0x20) ? 0xff : 0;
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return m_ram[offset] | conflict;
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// unmapped port, expects a bus error
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m_maincpu->pulse_input_line(t11_device::BUS_ERROR, attotime::zero);
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}
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@ -209,11 +201,12 @@ u16 im01_state::conflict_r(offs_t offset, u16 mem_mask)
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void im01_state::main_map(address_map &map)
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{
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map(0x0000, 0x07ff).ram().r(FUNC(im01_state::conflict_r)).share("ram");
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map(0x0000, 0x07ff).ram();
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map(0x2000, 0x5fff).rom();
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map(0xe030, 0xe031).mirror(0x1800).rw(FUNC(im01_state::mux_r), FUNC(im01_state::mux_w));
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map(0xe03c, 0xe03d).mirror(0x1800).rw(FUNC(im01_state::digit_r), FUNC(im01_state::digit_w));
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map(0xe03e, 0xe03f).mirror(0x1800).r(FUNC(im01_state::input_r));
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map(0xffe8, 0xffe9).w(FUNC(im01_state::error_w)).nopr();
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}
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