mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
pcipc: sandbox for emulating a modern-ish pc (nw)
This commit is contained in:
Olivier Galibert
parent
0036e43b7b
commit
d8aa10fbc1
@ -1786,6 +1786,10 @@ if (MACHINES["PCI"]~=null) then
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MAME_DIR .. "src/devices/machine/i82875p.h",
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MAME_DIR .. "src/devices/machine/i6300esb.cpp",
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MAME_DIR .. "src/devices/machine/i6300esb.h",
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MAME_DIR .. "src/devices/machine/i82439hx.cpp",
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MAME_DIR .. "src/devices/machine/i82439hx.h",
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MAME_DIR .. "src/devices/machine/i82371sb.cpp",
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MAME_DIR .. "src/devices/machine/i82371sb.h",
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MAME_DIR .. "src/devices/machine/lpc.cpp",
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MAME_DIR .. "src/devices/machine/lpc.h",
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MAME_DIR .. "src/devices/machine/lpc-acpi.cpp",
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@ -244,6 +244,18 @@ if (VIDEOS["GF7600GS"]~=null) then
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/mga2064w.h,VIDEOS["MGA2064W"] = true
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--------------------------------------------------
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if (VIDEOS["MGA2064W"]~=null) then
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files {
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MAME_DIR .. "src/devices/video/mga2064w.cpp",
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MAME_DIR .. "src/devices/video/mga2064w.h",
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/hd44102.h,VIDEOS["HD44102"] = true
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@ -334,6 +334,7 @@ VIDEOS["VIC4567"] = true
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VIDEOS["SCN2674"] = true
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VIDEOS["GB_LCD"] = true
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VIDEOS["GBA_LCD"] = true
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VIDEOS["MGA2064W"] = true
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--------------------------------------------------
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-- specify available machine cores
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@ -2445,6 +2446,7 @@ files {
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MAME_DIR .. "src/mame/drivers/ibmpc.cpp",
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MAME_DIR .. "src/mame/drivers/ibmpcjr.cpp",
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MAME_DIR .. "src/mame/drivers/pc.cpp",
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MAME_DIR .. "src/mame/drivers/pcipc.cpp",
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MAME_DIR .. "src/mame/drivers/tandy1t.cpp",
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MAME_DIR .. "src/mame/video/pc_t1t.cpp",
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MAME_DIR .. "src/mame/video/pc_t1t.h",
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361
src/devices/machine/i82371sb.cpp
Normal file
361
src/devices/machine/i82371sb.cpp
Normal file
@ -0,0 +1,361 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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#include "i82371sb.h"
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const device_type I82371SB_ISA = &device_creator<i82371sb_isa_device>;
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DEVICE_ADDRESS_MAP_START(config_map, 32, i82371sb_isa_device)
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AM_RANGE(0x4c, 0x4f) AM_READWRITE8 (iort_r, iort_w, 0x000000ff)
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AM_RANGE(0x4c, 0x4f) AM_READWRITE16(xbcs_r, xbcs_w, 0xffff0000)
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AM_RANGE(0x60, 0x63) AM_READWRITE8 (pirqrc_r, pirqrc_w, 0xffffffff)
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AM_RANGE(0x68, 0x6b) AM_READWRITE8 (tom_r, tom_w, 0x000000ff)
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AM_RANGE(0x68, 0x6b) AM_READWRITE16(mstat_r, mstat_w, 0xffff0000)
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AM_RANGE(0x70, 0x73) AM_READWRITE8 (mbirq0_r, mbirq0_w, 0x000000ff)
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AM_RANGE(0x74, 0x77) AM_READWRITE8 (mbdma_r, mbdma_w, 0xffff0000)
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AM_RANGE(0x80, 0x83) AM_READWRITE8 (dlc_r, dlc_w, 0x00ff0000)
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AM_RANGE(0xa0, 0xa3) AM_READWRITE8 (smicntl_r, smicntl_w, 0x000000ff)
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AM_RANGE(0xa0, 0xa3) AM_READWRITE16(smien_r, smien_w, 0xffff0000)
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AM_RANGE(0xa4, 0xa7) AM_READWRITE (see_r, see_w)
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AM_RANGE(0xa8, 0xab) AM_READWRITE8 (ftmr_r, ftmr_w, 0x000000ff)
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AM_RANGE(0xa8, 0xab) AM_READWRITE16(smireq_r, smireq_w, 0xffff0000)
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AM_RANGE(0xac, 0xaf) AM_READWRITE8 (ctltmr_r, ctltmr_w, 0x000000ff)
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AM_RANGE(0xac, 0xaf) AM_READWRITE8 (cthtmr_r, cthtmr_w, 0x00ff0000)
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AM_INHERIT_FROM(pci_device::config_map)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(internal_io_map, 32, i82371sb_isa_device)
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// AM_RANGE(0x0060, 0x0063) AM_READ8 (reset_irq12_1_r, 0x000000ff)
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// AM_RANGE(0x0060, 0x0063) AM_READWRITE8 (nmi_st_r, nmi_st_w, 0x0000ff00)
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AM_RANGE(0x0080, 0x0083) AM_WRITE8 (boot_state_w, 0x000000ff) // POST/non-existing, used for delays by the bios/os
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AM_RANGE(0x00ec, 0x00ef) AM_WRITE8 (nop_w, 0x0000ff00) // Non-existing, used for delays by the bios/os
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ADDRESS_MAP_END
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i82371sb_isa_device::i82371sb_isa_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: pci_device(mconfig, I82371SB_ISA, "i82371sb southbridge ISA bridge", tag, owner, clock, "i82371sb_isa", __FILE__),
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m_boot_state_hook(*this)
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{
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}
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void i82371sb_isa_device::device_start()
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{
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pci_device::device_start();
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m_boot_state_hook.resolve();
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}
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void i82371sb_isa_device::device_reset()
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{
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pci_device::device_reset();
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iort = 0x4d;
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xbcs = 0x0003;
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memset(pirqrc, 0x80, sizeof(pirqrc));
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tom = 0x02;
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mstat = 0x0000;
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mbirq0 = 0x80;
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memset(mbdma, 0x0c, sizeof(mbdma));
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pcsc = 0x0002;
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apicbase = 0x00;
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dlc = 0x00;
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smicntl = 0x08;
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smien = 0x0000;
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see = 0x00000000;
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ftmr = 0x0f;
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smireq = 0x0000;
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ctlmtr = 0x00;
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cthmtr = 0x00;
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}
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void i82371sb_isa_device::reset_all_mappings()
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{
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pci_device::reset_all_mappings();
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}
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WRITE8_MEMBER (i82371sb_isa_device::boot_state_w)
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{
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m_boot_state_hook((offs_t)0, data);
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}
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WRITE8_MEMBER (i82371sb_isa_device::nop_w)
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{
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}
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READ8_MEMBER (i82371sb_isa_device::iort_r)
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{
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return iort;
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}
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WRITE8_MEMBER(i82371sb_isa_device::iort_w)
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{
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iort = data;
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logerror("iort = %02x\n", iort);
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}
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READ16_MEMBER (i82371sb_isa_device::xbcs_r)
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{
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return xbcs;
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}
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WRITE16_MEMBER(i82371sb_isa_device::xbcs_w)
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{
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COMBINE_DATA(&xbcs);
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logerror("xbcs = %04x\n", xbcs);
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}
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READ8_MEMBER (i82371sb_isa_device::pirqrc_r)
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{
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return pirqrc[offset];
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}
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WRITE8_MEMBER(i82371sb_isa_device::pirqrc_w)
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{
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pirqrc[offset] = data;
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logerror("pirqrc[%d] = %02x\n", offset, pirqrc[offset]);
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}
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READ8_MEMBER (i82371sb_isa_device::tom_r)
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{
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return tom;
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}
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WRITE8_MEMBER(i82371sb_isa_device::tom_w)
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{
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tom = data;
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logerror("tom = %02x\n", tom);
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}
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READ16_MEMBER (i82371sb_isa_device::mstat_r)
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{
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return mstat;
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}
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WRITE16_MEMBER(i82371sb_isa_device::mstat_w)
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{
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COMBINE_DATA(&mstat);
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logerror("mstat = %04x\n", mstat);
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}
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READ8_MEMBER (i82371sb_isa_device::mbirq0_r)
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{
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return mbirq0;
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}
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WRITE8_MEMBER(i82371sb_isa_device::mbirq0_w)
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{
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mbirq0 = data;
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logerror("mbirq0 = %02x\n", mbirq0);
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}
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READ8_MEMBER (i82371sb_isa_device::mbdma_r)
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{
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return mbdma[offset];
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}
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WRITE8_MEMBER(i82371sb_isa_device::mbdma_w)
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{
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mbdma[offset] = data;
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logerror("mbdma[%d] = %02x\n", offset, mbdma);
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}
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READ8_MEMBER (i82371sb_isa_device::apicbase_r)
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{
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return apicbase;
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}
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WRITE8_MEMBER(i82371sb_isa_device::apicbase_w)
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{
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apicbase = data;
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logerror("apicbase = %02x\n", apicbase);
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}
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READ8_MEMBER (i82371sb_isa_device::dlc_r)
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{
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return dlc;
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}
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WRITE8_MEMBER(i82371sb_isa_device::dlc_w)
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{
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dlc = data;
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logerror("dlc = %02x\n", dlc);
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}
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READ8_MEMBER (i82371sb_isa_device::smicntl_r)
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{
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return smicntl;
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}
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WRITE8_MEMBER(i82371sb_isa_device::smicntl_w)
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{
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smicntl = data;
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logerror("smicntl = %02x\n", smicntl);
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}
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READ16_MEMBER (i82371sb_isa_device::smien_r)
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{
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return smien;
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}
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WRITE16_MEMBER(i82371sb_isa_device::smien_w)
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{
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COMBINE_DATA(&smien);
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logerror("smien = %04x\n", smien);
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}
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READ32_MEMBER (i82371sb_isa_device::see_r)
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{
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return see;
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}
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WRITE32_MEMBER(i82371sb_isa_device::see_w)
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{
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COMBINE_DATA(&see);
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logerror("see = %08x\n", see);
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}
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READ8_MEMBER (i82371sb_isa_device::ftmr_r)
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{
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return ftmr;
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}
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WRITE8_MEMBER(i82371sb_isa_device::ftmr_w)
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{
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ftmr = data;
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logerror("ftmr = %02x\n", ftmr);
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}
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READ16_MEMBER (i82371sb_isa_device::smireq_r)
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{
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return smireq;
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}
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WRITE16_MEMBER(i82371sb_isa_device::smireq_w)
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{
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COMBINE_DATA(&smireq);
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logerror("smireq = %04x\n", smireq);
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}
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READ8_MEMBER (i82371sb_isa_device::ctltmr_r)
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{
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return ctlmtr;
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}
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WRITE8_MEMBER(i82371sb_isa_device::ctltmr_w)
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{
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ctlmtr = data;
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logerror("ctlmtr = %02x\n", ctlmtr);
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}
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READ8_MEMBER (i82371sb_isa_device::cthtmr_r)
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{
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return cthmtr;
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}
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WRITE8_MEMBER(i82371sb_isa_device::cthtmr_w)
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{
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cthmtr = data;
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logerror("cthmtr = %02x\n", cthmtr);
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}
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void i82371sb_isa_device::map_bios(address_space *memory_space, UINT32 start, UINT32 end)
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{
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UINT32 mask = m_region->bytes() - 1;
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memory_space->install_rom(start, end, m_region->base() + (start & mask));
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}
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void i82371sb_isa_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
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UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
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{
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map_bios(memory_space, 0xfffe0000, 0xffffffff);
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map_bios(memory_space, 0x000e0000, 0x000fffff);
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io_space->install_device(0, 0xffff, *this, &i82371sb_isa_device::internal_io_map);
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#if 0
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if(fwh_dec_en1 & 0x80) {
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map_bios(memory_space, 0xfff80000, 0xffffffff, 7);
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map_bios(memory_space, 0xffb80000, 0xffbfffff, 7);
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map_bios(memory_space, 0x000e0000, 0x000fffff, 7);
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}
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if(fwh_dec_en1 & 0x40) {
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map_bios(memory_space, 0xfff00000, 0xfff7ffff, 6);
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map_bios(memory_space, 0xffb00000, 0xffb7ffff, 6);
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}
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if(fwh_dec_en1 & 0x20) {
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map_bios(memory_space, 0xffe80000, 0xffefffff, 5);
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map_bios(memory_space, 0xffa80000, 0xffafffff, 5);
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}
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if(fwh_dec_en1 & 0x10) {
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map_bios(memory_space, 0xffe00000, 0xffe7ffff, 4);
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map_bios(memory_space, 0xffa00000, 0xffa7ffff, 4);
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}
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if(fwh_dec_en1 & 0x08) {
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map_bios(memory_space, 0xffd80000, 0xffdfffff, 3);
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map_bios(memory_space, 0xff980000, 0xff9fffff, 3);
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}
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if(fwh_dec_en1 & 0x04) {
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map_bios(memory_space, 0xffd00000, 0xffd7ffff, 2);
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map_bios(memory_space, 0xff900000, 0xff97ffff, 2);
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}
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if(fwh_dec_en1 & 0x02) {
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map_bios(memory_space, 0xffc80000, 0xffcfffff, 1);
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map_bios(memory_space, 0xff880000, 0xff8fffff, 1);
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}
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if(fwh_dec_en1 & 0x01) {
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map_bios(memory_space, 0xffc00000, 0xffc7ffff, 0);
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map_bios(memory_space, 0xff800000, 0xff87ffff, 0);
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}
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if(acpi_cntl & 0x10)
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acpi->map_device(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, pmbase, io_space);
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if(gpio_cntl & 0x10)
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logerror("%s: Warning: gpio range enabled at %04x-%04x\n", tag(), gpio_base, gpio_base+63);
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UINT32 hpet = 0xfed00000 + ((gen_cntl & 0x00018000) >> 3);
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logerror("%s: Warning: hpet at %08x-%08x\n", tag(), hpet, hpet+0x3ff);
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if(lpc_en & 0x1000)
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logerror("%s: Warning: superio at 2e-2f\n", tag());
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if(lpc_en & 0x0800)
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logerror("%s: Warning: mcu at 62/66\n", tag());
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if(lpc_en & 0x0400)
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logerror("%s: Warning: mcu at 60/64\n", tag());
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if(lpc_en & 0x0200)
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logerror("%s: Warning: gameport at 208-20f\n", tag());
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if(lpc_en & 0x0100)
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logerror("%s: Warning: gameport at 200-207\n", tag());
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if(lpc_en & 0x0008) {
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UINT16 fdc = lpc_if_fdd_lpt_range & 0x10 ? 0x370 : 0x3f0;
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logerror("%s: Warning: floppy at %04x-%04x\n", tag(), fdc, fdc+7);
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}
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if(lpc_en & 0x0004) {
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static const UINT16 lpt_pos[4] = { 0x378, 0x278, 0x3bc, 0x000 };
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UINT16 lpt = lpt_pos[lpc_if_fdd_lpt_range & 3];
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if(lpt)
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logerror("%s: Warning: lpt at %04x-%04x %04x-%04x\n", tag(), lpt, lpt+7, lpt+0x400, lpt+0x407);
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}
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static const UINT16 com_pos[8] = { 0x3f8, 0x2f8, 0x220, 0x228, 0x238, 0x2e8, 0x338, 0x3e8 };
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if(lpc_en & 0x0002) {
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UINT16 comb = com_pos[(lpc_if_com_range >> 4) & 7];
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logerror("%s: Warning: comb at %04x-%04x\n", tag(), comb, comb+7);
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}
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if(lpc_en & 0x0001) {
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UINT16 coma = com_pos[lpc_if_com_range & 7];
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logerror("%s: Warning: coma at %04x-%04x\n", tag(), coma, coma+7);
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}
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rtc->map_device(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
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if(rtc_conf & 4)
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||||
rtc->map_extdevice(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
|
||||
pit->map_device(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
|
||||
#endif
|
||||
}
|
||||
84
src/devices/machine/i82371sb.h
Normal file
84
src/devices/machine/i82371sb.h
Normal file
@ -0,0 +1,84 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
// Intel i82371sb southbridge (PIIX3)
|
||||
|
||||
#ifndef I82371SB_H
|
||||
#define I82371SB_H
|
||||
|
||||
#include "pci.h"
|
||||
|
||||
#define MCFG_I82371SB_ISA_ADD(_tag) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, I82371SB_ISA, 0x80867000, 0x03, 0x060100, 0x00000000)
|
||||
|
||||
#define MCFG_I82371SB_BOOT_STATE_HOOK(_devcb) \
|
||||
devcb = &i82371sb_isa_device::set_boot_state_hook(*device, DEVCB_##_devcb);
|
||||
|
||||
class i82371sb_isa_device : public pci_device {
|
||||
public:
|
||||
i82371sb_isa_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
template<class _Object> static devcb_base &set_boot_state_hook(device_t &device, _Object object) { return downcast<i82371sb_isa_device &>(device).m_boot_state_hook.set_callback(object); }
|
||||
|
||||
virtual void reset_all_mappings() override;
|
||||
virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
|
||||
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space) override;
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(config_map, 32) override;
|
||||
DECLARE_ADDRESS_MAP(internal_io_map, 32);
|
||||
|
||||
DECLARE_WRITE8_MEMBER (boot_state_w);
|
||||
DECLARE_WRITE8_MEMBER (nop_w);
|
||||
|
||||
DECLARE_READ8_MEMBER (iort_r);
|
||||
DECLARE_WRITE8_MEMBER (iort_w);
|
||||
DECLARE_READ16_MEMBER (xbcs_r);
|
||||
DECLARE_WRITE16_MEMBER(xbcs_w);
|
||||
DECLARE_READ8_MEMBER (pirqrc_r);
|
||||
DECLARE_WRITE8_MEMBER (pirqrc_w);
|
||||
DECLARE_READ8_MEMBER (tom_r);
|
||||
DECLARE_WRITE8_MEMBER (tom_w);
|
||||
DECLARE_READ16_MEMBER (mstat_r);
|
||||
DECLARE_WRITE16_MEMBER(mstat_w);
|
||||
DECLARE_READ8_MEMBER (mbirq0_r);
|
||||
DECLARE_WRITE8_MEMBER (mbirq0_w);
|
||||
DECLARE_READ8_MEMBER (mbdma_r);
|
||||
DECLARE_WRITE8_MEMBER (mbdma_w);
|
||||
DECLARE_READ16_MEMBER (pcsc_r);
|
||||
DECLARE_WRITE16_MEMBER(pcsc_w);
|
||||
DECLARE_READ8_MEMBER (apicbase_r);
|
||||
DECLARE_WRITE8_MEMBER (apicbase_w);
|
||||
DECLARE_READ8_MEMBER (dlc_r);
|
||||
DECLARE_WRITE8_MEMBER (dlc_w);
|
||||
DECLARE_READ8_MEMBER (smicntl_r);
|
||||
DECLARE_WRITE8_MEMBER (smicntl_w);
|
||||
DECLARE_READ16_MEMBER (smien_r);
|
||||
DECLARE_WRITE16_MEMBER(smien_w);
|
||||
DECLARE_READ32_MEMBER (see_r);
|
||||
DECLARE_WRITE32_MEMBER(see_w);
|
||||
DECLARE_READ8_MEMBER (ftmr_r);
|
||||
DECLARE_WRITE8_MEMBER (ftmr_w);
|
||||
DECLARE_READ16_MEMBER (smireq_r);
|
||||
DECLARE_WRITE16_MEMBER(smireq_w);
|
||||
DECLARE_READ8_MEMBER (ctltmr_r);
|
||||
DECLARE_WRITE8_MEMBER (ctltmr_w);
|
||||
DECLARE_READ8_MEMBER (cthtmr_r);
|
||||
DECLARE_WRITE8_MEMBER (cthtmr_w);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
private:
|
||||
devcb_write8 m_boot_state_hook;
|
||||
|
||||
UINT32 see;
|
||||
UINT16 xbcs, mstat, pcsc, smien, smireq;
|
||||
UINT8 iort, pirqrc[4], tom, mbirq0, mbdma[2], apicbase;
|
||||
UINT8 dlc, smicntl, ftmr, ctlmtr, cthmtr;
|
||||
|
||||
void map_bios(address_space *memory_space, UINT32 start, UINT32 end);
|
||||
};
|
||||
|
||||
extern const device_type I82371SB_ISA;
|
||||
|
||||
#endif
|
||||
308
src/devices/machine/i82439hx.cpp
Normal file
308
src/devices/machine/i82439hx.cpp
Normal file
@ -0,0 +1,308 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
#include "i82439hx.h"
|
||||
|
||||
const device_type I82439HX = &device_creator<i82439hx_host_device>;
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(config_map, 32, i82439hx_host_device)
|
||||
AM_RANGE(0x50, 0x53) AM_READWRITE8(pcon_r, pcon_w, 0x000000ff)
|
||||
AM_RANGE(0x50, 0x53) AM_READWRITE8(cc_r, cc_w, 0x00ff0000)
|
||||
AM_RANGE(0x54, 0x57) AM_READWRITE8(dramec_r, dramec_w, 0x00ff0000)
|
||||
AM_RANGE(0x54, 0x57) AM_READWRITE8(dramc_r, dramc_w, 0xff000000)
|
||||
AM_RANGE(0x58, 0x5b) AM_READWRITE8(dramt_r, dramt_w, 0x000000ff)
|
||||
AM_RANGE(0x58, 0x5b) AM_READWRITE8(pam0_r, pam0_w, 0xffffff00)
|
||||
AM_RANGE(0x5c, 0x5f) AM_READWRITE8(pam3_r, pam3_w, 0xffffffff)
|
||||
AM_RANGE(0x60, 0x67) AM_READWRITE8(drb_r, drb_w, 0xffffffff)
|
||||
AM_RANGE(0x68, 0x6b) AM_READWRITE8(drt_r, drt_w, 0x000000ff)
|
||||
AM_RANGE(0x68, 0x6b) AM_READWRITE8(drat_r, drat_w, 0x0000ff00)
|
||||
AM_RANGE(0x70, 0x73) AM_READWRITE8(smram_r, smram_w, 0x00ff0000)
|
||||
AM_RANGE(0x90, 0x93) AM_READWRITE8(errcmd_r, errcmd_w, 0x000000ff)
|
||||
AM_RANGE(0x90, 0x93) AM_READWRITE8(errsts_r, errsts_w, 0x0000ff00)
|
||||
AM_RANGE(0x90, 0x93) AM_READ8 (errsyn_r, 0x00ff0000)
|
||||
|
||||
|
||||
AM_INHERIT_FROM(pci_host_device::config_map)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
i82439hx_host_device::i82439hx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: pci_host_device(mconfig, I82439HX, "i82439hx northbridge", tag, owner, clock, "i82439hx", __FILE__)
|
||||
{
|
||||
}
|
||||
|
||||
void i82439hx_host_device::set_cpu_tag(const char *_cpu_tag)
|
||||
{
|
||||
cpu_tag = _cpu_tag;
|
||||
}
|
||||
|
||||
void i82439hx_host_device::set_ram_size(int _ram_size)
|
||||
{
|
||||
ram_size = _ram_size;
|
||||
}
|
||||
|
||||
void i82439hx_host_device::device_start()
|
||||
{
|
||||
pci_host_device::device_start();
|
||||
cpu = machine().device<cpu_device>(cpu_tag);
|
||||
memory_space = &cpu->space(AS_PROGRAM);
|
||||
io_space = &cpu->space(AS_IO);
|
||||
|
||||
memory_window_start = 0;
|
||||
memory_window_end = 0xffffffff;
|
||||
memory_offset = 0;
|
||||
io_window_start = 0;
|
||||
io_window_end = 0xffff;
|
||||
io_offset = 0;
|
||||
status = 0x0010;
|
||||
|
||||
ram.resize(ram_size/4);
|
||||
}
|
||||
|
||||
void i82439hx_host_device::reset_all_mappings()
|
||||
{
|
||||
pci_host_device::reset_all_mappings();
|
||||
}
|
||||
|
||||
void i82439hx_host_device::device_reset()
|
||||
{
|
||||
pci_host_device::device_reset();
|
||||
|
||||
pcon = 0x00;
|
||||
cc = 0xa2;
|
||||
dramec = 0x00;
|
||||
dramc = 0x01;
|
||||
dramt = 0x00;
|
||||
memset(pam, 0x00, sizeof(pam));
|
||||
memset(drb, 0x02, sizeof(drb));
|
||||
drt = 0x00;
|
||||
drat = 0x00;
|
||||
smram = 0x02;
|
||||
errcmd = 0x00;
|
||||
errsts = 0x00;
|
||||
errsyn = 0x00;
|
||||
}
|
||||
|
||||
void i82439hx_host_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
|
||||
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
|
||||
{
|
||||
io_space->install_device(0, 0xffff, *static_cast<pci_host_device *>(this), &pci_host_device::io_configuration_access_map);
|
||||
|
||||
if((dramc & 0xc0) == 0x40)
|
||||
memory_space->install_ram (0x00000000, 0x0007ffff, &ram[0x00000000/4]);
|
||||
else
|
||||
memory_space->install_ram (0x00000000, 0x0009ffff, &ram[0x00000000/4]);
|
||||
|
||||
if(smram & 0x40)
|
||||
memory_space->install_ram (0x000a0000, 0x000bffff, &ram[0x000a0000/4]);
|
||||
|
||||
if(pam[1] & 0x01)
|
||||
memory_space->install_rom (0x000c0000, 0x000c3fff, &ram[0x000c0000/4]);
|
||||
if(pam[1] & 0x02)
|
||||
memory_space->install_writeonly(0x000c0000, 0x000c3fff, &ram[0x000c0000/4]);
|
||||
if(pam[1] & 0x10)
|
||||
memory_space->install_rom (0x000c4000, 0x000c7fff, &ram[0x000c4000/4]);
|
||||
if(pam[1] & 0x20)
|
||||
memory_space->install_writeonly(0x000c4000, 0x000c7fff, &ram[0x000c4000/4]);
|
||||
if(pam[2] & 0x01)
|
||||
memory_space->install_rom (0x000c8000, 0x000cbfff, &ram[0x000c8000/4]);
|
||||
if(pam[2] & 0x02)
|
||||
memory_space->install_writeonly(0x000c8000, 0x000cbfff, &ram[0x000c8000/4]);
|
||||
if(pam[2] & 0x10)
|
||||
memory_space->install_rom (0x000cc000, 0x000cffff, &ram[0x000cc000/4]);
|
||||
if(pam[2] & 0x20)
|
||||
memory_space->install_writeonly(0x000cc000, 0x000cffff, &ram[0x000cc000/4]);
|
||||
if(pam[3] & 0x01)
|
||||
memory_space->install_rom (0x000d0000, 0x000d3fff, &ram[0x000d0000/4]);
|
||||
if(pam[3] & 0x02)
|
||||
memory_space->install_writeonly(0x000d0000, 0x000d3fff, &ram[0x000d0000/4]);
|
||||
if(pam[3] & 0x10)
|
||||
memory_space->install_rom (0x000d4000, 0x000d7fff, &ram[0x000d4000/4]);
|
||||
if(pam[3] & 0x20)
|
||||
memory_space->install_writeonly(0x000d4000, 0x000d7fff, &ram[0x000d4000/4]);
|
||||
if(pam[4] & 0x01)
|
||||
memory_space->install_rom (0x000d8000, 0x000dbfff, &ram[0x000d8000/4]);
|
||||
if(pam[4] & 0x02)
|
||||
memory_space->install_writeonly(0x000d8000, 0x000dbfff, &ram[0x000d8000/4]);
|
||||
if(pam[4] & 0x10)
|
||||
memory_space->install_rom (0x000dc000, 0x000dffff, &ram[0x000dc000/4]);
|
||||
if(pam[4] & 0x20)
|
||||
memory_space->install_writeonly(0x000dc000, 0x000dffff, &ram[0x000dc000/4]);
|
||||
if(pam[5] & 0x01)
|
||||
memory_space->install_rom (0x000e0000, 0x000e3fff, &ram[0x000e0000/4]);
|
||||
if(pam[5] & 0x02)
|
||||
memory_space->install_writeonly(0x000e0000, 0x000e3fff, &ram[0x000e0000/4]);
|
||||
if(pam[5] & 0x10)
|
||||
memory_space->install_rom (0x000e4000, 0x000e7fff, &ram[0x000e4000/4]);
|
||||
if(pam[5] & 0x20)
|
||||
memory_space->install_writeonly(0x000e4000, 0x000e7fff, &ram[0x000e4000/4]);
|
||||
if(pam[6] & 0x01)
|
||||
memory_space->install_rom (0x000e8000, 0x000ebfff, &ram[0x000e8000/4]);
|
||||
if(pam[6] & 0x02)
|
||||
memory_space->install_writeonly(0x000e8000, 0x000ebfff, &ram[0x000e8000/4]);
|
||||
if(pam[6] & 0x10)
|
||||
memory_space->install_rom (0x000ec000, 0x000effff, &ram[0x000ec000/4]);
|
||||
if(pam[6] & 0x20)
|
||||
memory_space->install_writeonly(0x000ec000, 0x000effff, &ram[0x000ec000/4]);
|
||||
if(pam[0] & 0x10)
|
||||
memory_space->install_rom (0x000f0000, 0x000fffff, &ram[0x000f0000/4]);
|
||||
if(pam[0] & 0x20)
|
||||
memory_space->install_writeonly(0x000f0000, 0x000fffff, &ram[0x000f0000/4]);
|
||||
|
||||
memory_space->install_ram (0x00100000, 0x00efffff, &ram[0x00100000/4]);
|
||||
if((dramc & 0xc0) != 0x80)
|
||||
memory_space->install_ram (0x00f00000, 0x00ffffff, &ram[0x00f00000/4]);
|
||||
|
||||
memory_space->install_ram (0x01000000, ram_size-1, &ram[0x01000000/4]);
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::pcon_r)
|
||||
{
|
||||
return pcon;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::pcon_w)
|
||||
{
|
||||
pcon = data;
|
||||
logerror("pcon = %02x\n", pcon);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::cc_r)
|
||||
{
|
||||
return cc;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::cc_w)
|
||||
{
|
||||
cc = data;
|
||||
logerror("cc = %02x\n", cc);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::dramec_r)
|
||||
{
|
||||
return dramec;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::dramec_w)
|
||||
{
|
||||
dramec = data;
|
||||
logerror("dramec = %02x\n", dramec);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::dramc_r)
|
||||
{
|
||||
return dramc;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::dramc_w)
|
||||
{
|
||||
dramc = data;
|
||||
logerror("dramc = %02x\n", dramc);
|
||||
remap_cb();
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::dramt_r)
|
||||
{
|
||||
return dramt;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::dramt_w)
|
||||
{
|
||||
dramt = data;
|
||||
logerror("dramt = %02x\n", dramt);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::pam0_r)
|
||||
{
|
||||
return pam[offset];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::pam0_w)
|
||||
{
|
||||
pam[offset] = data;
|
||||
logerror("pam[%d] = %02x\n", offset, pam[offset]);
|
||||
remap_cb();
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::pam3_r)
|
||||
{
|
||||
return pam[3+offset];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::pam3_w)
|
||||
{
|
||||
pam[3+offset] = data;
|
||||
logerror("pam[%d] = %02x\n", 3+offset, pam[3+offset]);
|
||||
remap_cb();
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::drb_r)
|
||||
{
|
||||
return drb[offset];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::drb_w)
|
||||
{
|
||||
drb[offset] = data;
|
||||
logerror("drb[%d] = %02x\n", offset, drb[offset]);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::drt_r)
|
||||
{
|
||||
return drt;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::drt_w)
|
||||
{
|
||||
drt = data;
|
||||
logerror("drt = %02x\n", drt);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::drat_r)
|
||||
{
|
||||
return drat;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::drat_w)
|
||||
{
|
||||
drat = data;
|
||||
logerror("drat = %02x\n", drat);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::smram_r)
|
||||
{
|
||||
return smram;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::smram_w)
|
||||
{
|
||||
smram = data;
|
||||
logerror("smram = %02x\n", smram);
|
||||
remap_cb();
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::errcmd_r)
|
||||
{
|
||||
return errcmd;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::errcmd_w)
|
||||
{
|
||||
errcmd = data;
|
||||
logerror("errcmd = %02x\n", errcmd);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::errsts_r)
|
||||
{
|
||||
return errsts;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(i82439hx_host_device::errsts_w)
|
||||
{
|
||||
errsts = data;
|
||||
logerror("errsts = %02x\n", errsts);
|
||||
}
|
||||
|
||||
READ8_MEMBER (i82439hx_host_device::errsyn_r)
|
||||
{
|
||||
return errsyn;
|
||||
}
|
||||
74
src/devices/machine/i82439hx.h
Normal file
74
src/devices/machine/i82439hx.h
Normal file
@ -0,0 +1,74 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
// Intel i82439hx northbridge (440hx)
|
||||
|
||||
#ifndef I82439HX_H
|
||||
#define I82439HX_H
|
||||
|
||||
#include "pci.h"
|
||||
|
||||
#define MCFG_I82439HX_ADD(_tag, _cpu_tag, _ram_size) \
|
||||
MCFG_PCI_HOST_ADD(_tag, I82439HX, 0x80861250, 0x03, 0x00000000) \
|
||||
downcast<i82439hx_host_device *>(device)->set_cpu_tag(_cpu_tag); \
|
||||
downcast<i82439hx_host_device *>(device)->set_ram_size(_ram_size);
|
||||
|
||||
class i82439hx_host_device : public pci_host_device {
|
||||
public:
|
||||
i82439hx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
void set_cpu_tag(const char *tag);
|
||||
void set_ram_size(int ram_size);
|
||||
|
||||
DECLARE_READ8_MEMBER (pcon_r);
|
||||
DECLARE_WRITE8_MEMBER(pcon_w);
|
||||
DECLARE_READ8_MEMBER (cc_r);
|
||||
DECLARE_WRITE8_MEMBER(cc_w);
|
||||
DECLARE_READ8_MEMBER (dramec_r);
|
||||
DECLARE_WRITE8_MEMBER(dramec_w);
|
||||
DECLARE_READ8_MEMBER (dramc_r);
|
||||
DECLARE_WRITE8_MEMBER(dramc_w);
|
||||
DECLARE_READ8_MEMBER (dramt_r);
|
||||
DECLARE_WRITE8_MEMBER(dramt_w);
|
||||
DECLARE_READ8_MEMBER (pam0_r);
|
||||
DECLARE_WRITE8_MEMBER(pam0_w);
|
||||
DECLARE_READ8_MEMBER (pam3_r);
|
||||
DECLARE_WRITE8_MEMBER(pam3_w);
|
||||
DECLARE_READ8_MEMBER (drb_r);
|
||||
DECLARE_WRITE8_MEMBER(drb_w);
|
||||
DECLARE_READ8_MEMBER (drt_r);
|
||||
DECLARE_WRITE8_MEMBER(drt_w);
|
||||
DECLARE_READ8_MEMBER (drat_r);
|
||||
DECLARE_WRITE8_MEMBER(drat_w);
|
||||
DECLARE_READ8_MEMBER (smram_r);
|
||||
DECLARE_WRITE8_MEMBER(smram_w);
|
||||
DECLARE_READ8_MEMBER (errcmd_r);
|
||||
DECLARE_WRITE8_MEMBER(errcmd_w);
|
||||
DECLARE_READ8_MEMBER (errsts_r);
|
||||
DECLARE_WRITE8_MEMBER(errsts_w);
|
||||
DECLARE_READ8_MEMBER (errsyn_r);
|
||||
|
||||
virtual void reset_all_mappings() override;
|
||||
|
||||
virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
|
||||
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space) override;
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(config_map, 32) override;
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
private:
|
||||
const char *cpu_tag;
|
||||
int ram_size;
|
||||
cpu_device *cpu;
|
||||
std::vector<UINT32> ram;
|
||||
|
||||
UINT8 pcon, cc, dramec, dramc, dramt;
|
||||
UINT8 pam[7], drb[8];
|
||||
UINT8 drt, drat, smram, errcmd, errsts, errsyn;
|
||||
};
|
||||
|
||||
extern const device_type I82439HX;
|
||||
|
||||
#endif
|
||||
@ -142,7 +142,7 @@ READ32_MEMBER(pci_device::address_base_r)
|
||||
WRITE32_MEMBER(pci_device::address_base_w)
|
||||
{
|
||||
if(bank_reg_infos[offset].bank == -1) {
|
||||
logerror("%s: write to address base (%d, %08x) not linked to any bank\n", tag(), offset, data);
|
||||
logerror("write to address base (%d, %08x) not linked to any bank\n", offset, data);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -174,7 +174,7 @@ WRITE16_MEMBER(pci_device::command_w)
|
||||
{
|
||||
mem_mask &= command_mask;
|
||||
COMBINE_DATA(&command);
|
||||
logerror("%s: command = %04x\n", tag(), command);
|
||||
logerror("command = %04x\n", command);
|
||||
}
|
||||
|
||||
READ16_MEMBER(pci_device::status_r)
|
||||
@ -285,14 +285,14 @@ void pci_device::map_device(UINT64 memory_window_start, UINT64 memory_window_end
|
||||
}
|
||||
|
||||
space->install_device_delegate(start, end, *this, bi.map);
|
||||
logerror("%s: map %s at %0*x-%0*x\n", tag(), bi.map.name(), bi.flags & M_IO ? 4 : 8, UINT32(start), bi.flags & M_IO ? 4 : 8, UINT32(end));
|
||||
logerror("map %s at %0*x-%0*x\n", bi.map.name(), bi.flags & M_IO ? 4 : 8, UINT32(start), bi.flags & M_IO ? 4 : 8, UINT32(end));
|
||||
}
|
||||
|
||||
map_extra(memory_window_start, memory_window_end, memory_offset, memory_space,
|
||||
io_window_start, io_window_end, io_offset, io_space);
|
||||
|
||||
if(expansion_rom_base & 1) {
|
||||
logerror("%s: map expansion rom at %08x-%08x\n", tag(), expansion_rom_base & ~1, (expansion_rom_base & ~1) + expansion_rom_size - 1);
|
||||
logerror("map expansion rom at %08x-%08x\n", expansion_rom_base & ~1, (expansion_rom_base & ~1) + expansion_rom_size - 1);
|
||||
UINT32 start = (expansion_rom_base & ~1) + memory_offset;
|
||||
UINT32 end = start + expansion_rom_size - 1;
|
||||
if(end > memory_window_end)
|
||||
@ -521,7 +521,7 @@ UINT32 pci_bridge_device::do_config_read(UINT8 bus, UINT8 device, UINT16 reg, UI
|
||||
{
|
||||
if(sub_devices[device]) {
|
||||
UINT32 data = space(AS_PROGRAM).read_dword((device << 12) | reg, mem_mask);
|
||||
logerror("%s: config_read %02x:%02x.%x:%02x %08x @ %08x\n", tag(), bus, device >> 3, device & 7, reg, data, mem_mask);
|
||||
logerror("config_read %02x:%02x.%x:%02x %08x @ %08x\n", bus, device >> 3, device & 7, reg, data, mem_mask);
|
||||
return data;
|
||||
} else
|
||||
return 0xffffffff;
|
||||
@ -550,7 +550,7 @@ void pci_bridge_device::do_config_write(UINT8 bus, UINT8 device, UINT16 reg, UIN
|
||||
{
|
||||
if(sub_devices[device]) {
|
||||
space(AS_PROGRAM).write_dword((device << 12) | reg, data, mem_mask);
|
||||
logerror("%s: config_write %02x:%02x.%x:%02x %08x @ %08x\n", tag(), bus, device >> 3, device & 7, reg, data, mem_mask);
|
||||
logerror("config_write %02x:%02x.%x:%02x %08x @ %08x\n", bus, device >> 3, device & 7, reg, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
@ -571,60 +571,60 @@ void pci_bridge_device::config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32
|
||||
|
||||
READ32_MEMBER (pci_bridge_device::b_address_base_r)
|
||||
{
|
||||
logerror("%s: b_address_base_r %d\n", tag(), offset);
|
||||
logerror("b_address_base_r %d\n", offset);
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(pci_bridge_device::b_address_base_w)
|
||||
{
|
||||
logerror("%s: b_address_base_w %d, %08x\n", tag(), offset, data);
|
||||
logerror("b_address_base_w %d, %08x\n", offset, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER (pci_bridge_device::primary_bus_r)
|
||||
{
|
||||
logerror("%s: primary_bus_r\n", tag());
|
||||
logerror("primary_bus_r\n");
|
||||
return primary_bus;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER (pci_bridge_device::primary_bus_w)
|
||||
{
|
||||
primary_bus = data;
|
||||
logerror("%s: primary_bus_w %02x\n", tag(), data);
|
||||
logerror("primary_bus_w %02x\n", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER (pci_bridge_device::secondary_bus_r)
|
||||
{
|
||||
logerror("%s: secondary_bus_r\n", tag());
|
||||
logerror("secondary_bus_r\n");
|
||||
return secondary_bus;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER (pci_bridge_device::secondary_bus_w)
|
||||
{
|
||||
secondary_bus = data;
|
||||
logerror("%s: secondary_bus_w %02x\n", tag(), data);
|
||||
logerror("secondary_bus_w %02x\n", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER (pci_bridge_device::subordinate_bus_r)
|
||||
{
|
||||
logerror("%s: subordinate_bus_r\n", tag());
|
||||
logerror("subordinate_bus_r\n");
|
||||
return subordinate_bus;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER (pci_bridge_device::subordinate_bus_w)
|
||||
{
|
||||
subordinate_bus = data;
|
||||
logerror("%s: subordinate_bus_w %02x\n", tag(), data);
|
||||
logerror("subordinate_bus_w %02x\n", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER (pci_bridge_device::secondary_latency_r)
|
||||
{
|
||||
logerror("%s: secondary_latency_r\n", tag());
|
||||
logerror("secondary_latency_r\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER (pci_bridge_device::secondary_latency_w)
|
||||
{
|
||||
logerror("%s: secondary_latency_w %02x\n", tag(), data);
|
||||
logerror("secondary_latency_w %02x\n", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER (pci_bridge_device::iobase_r)
|
||||
@ -635,7 +635,7 @@ READ8_MEMBER (pci_bridge_device::iobase_r)
|
||||
WRITE8_MEMBER (pci_bridge_device::iobase_w)
|
||||
{
|
||||
iobase = data;
|
||||
logerror("%s: iobase_w %02x\n", tag(), data);
|
||||
logerror("iobase_w %02x\n", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER (pci_bridge_device::iolimit_r)
|
||||
@ -646,18 +646,18 @@ READ8_MEMBER (pci_bridge_device::iolimit_r)
|
||||
WRITE8_MEMBER (pci_bridge_device::iolimit_w)
|
||||
{
|
||||
iolimit = data;
|
||||
logerror("%s: iolimit_w %02x\n", tag(), data);
|
||||
logerror("iolimit_w %02x\n", data);
|
||||
}
|
||||
|
||||
READ16_MEMBER (pci_bridge_device::secondary_status_r)
|
||||
{
|
||||
logerror("%s: secondary_status_r\n", tag());
|
||||
logerror("secondary_status_r\n");
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(pci_bridge_device::secondary_status_w)
|
||||
{
|
||||
logerror("%s: secondary_status_w %04x\n", tag(), data);
|
||||
logerror("secondary_status_w %04x\n", data);
|
||||
}
|
||||
|
||||
READ16_MEMBER (pci_bridge_device::memory_base_r)
|
||||
@ -668,7 +668,7 @@ READ16_MEMBER (pci_bridge_device::memory_base_r)
|
||||
WRITE16_MEMBER(pci_bridge_device::memory_base_w)
|
||||
{
|
||||
COMBINE_DATA(&memory_base);
|
||||
logerror("%s: memory_base_w %04x\n", tag(), memory_base);
|
||||
logerror("memory_base_w %04x\n", memory_base);
|
||||
}
|
||||
|
||||
READ16_MEMBER (pci_bridge_device::memory_limit_r)
|
||||
@ -679,7 +679,7 @@ READ16_MEMBER (pci_bridge_device::memory_limit_r)
|
||||
WRITE16_MEMBER(pci_bridge_device::memory_limit_w)
|
||||
{
|
||||
COMBINE_DATA(&memory_limit);
|
||||
logerror("%s: memory_limit_w %04x\n", tag(), memory_limit);
|
||||
logerror("memory_limit_w %04x\n", memory_limit);
|
||||
}
|
||||
|
||||
READ16_MEMBER (pci_bridge_device::prefetch_base_r)
|
||||
@ -690,7 +690,7 @@ READ16_MEMBER (pci_bridge_device::prefetch_base_r)
|
||||
WRITE16_MEMBER(pci_bridge_device::prefetch_base_w)
|
||||
{
|
||||
COMBINE_DATA(&prefetch_base);
|
||||
logerror("%s: prefetch_base_w %04x\n", tag(), prefetch_base);
|
||||
logerror("prefetch_base_w %04x\n", prefetch_base);
|
||||
}
|
||||
|
||||
READ16_MEMBER (pci_bridge_device::prefetch_limit_r)
|
||||
@ -701,7 +701,7 @@ READ16_MEMBER (pci_bridge_device::prefetch_limit_r)
|
||||
WRITE16_MEMBER(pci_bridge_device::prefetch_limit_w)
|
||||
{
|
||||
COMBINE_DATA(&prefetch_limit);
|
||||
logerror("%s: prefetch_limit_w %04x\n", tag(), prefetch_limit);
|
||||
logerror("prefetch_limit_w %04x\n", prefetch_limit);
|
||||
}
|
||||
|
||||
READ32_MEMBER (pci_bridge_device::prefetch_baseu_r)
|
||||
@ -712,7 +712,7 @@ READ32_MEMBER (pci_bridge_device::prefetch_baseu_r)
|
||||
WRITE32_MEMBER(pci_bridge_device::prefetch_baseu_w)
|
||||
{
|
||||
COMBINE_DATA(&prefetch_baseu);
|
||||
logerror("%s: prefetch_baseu_w %08x\n", tag(), prefetch_baseu);
|
||||
logerror("prefetch_baseu_w %08x\n", prefetch_baseu);
|
||||
}
|
||||
|
||||
READ32_MEMBER (pci_bridge_device::prefetch_limitu_r)
|
||||
@ -723,7 +723,7 @@ READ32_MEMBER (pci_bridge_device::prefetch_limitu_r)
|
||||
WRITE32_MEMBER(pci_bridge_device::prefetch_limitu_w)
|
||||
{
|
||||
COMBINE_DATA(&prefetch_limitu);
|
||||
logerror("%s: prefetch_limitu_w %08x\n", tag(), prefetch_limitu);
|
||||
logerror("prefetch_limitu_w %08x\n", prefetch_limitu);
|
||||
}
|
||||
|
||||
READ16_MEMBER (pci_bridge_device::iobaseu_r)
|
||||
@ -734,7 +734,7 @@ READ16_MEMBER (pci_bridge_device::iobaseu_r)
|
||||
WRITE16_MEMBER(pci_bridge_device::iobaseu_w)
|
||||
{
|
||||
COMBINE_DATA(&iobaseu);
|
||||
logerror("%s: iobaseu_w %04x\n", tag(), iobaseu);
|
||||
logerror("iobaseu_w %04x\n", iobaseu);
|
||||
}
|
||||
|
||||
READ16_MEMBER (pci_bridge_device::iolimitu_r)
|
||||
@ -745,29 +745,29 @@ READ16_MEMBER (pci_bridge_device::iolimitu_r)
|
||||
WRITE16_MEMBER(pci_bridge_device::iolimitu_w)
|
||||
{
|
||||
COMBINE_DATA(&iolimitu);
|
||||
logerror("%s: iolimitu_w %04x\n", tag(), iolimitu);
|
||||
logerror("iolimitu_w %04x\n", iolimitu);
|
||||
}
|
||||
|
||||
READ8_MEMBER (pci_bridge_device::interrupt_line_r)
|
||||
{
|
||||
logerror("%s: interrupt_line_r\n", tag());
|
||||
logerror("interrupt_line_r\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER (pci_bridge_device::interrupt_line_w)
|
||||
{
|
||||
logerror("%s: interrupt_line_w %02x\n", tag(), data);
|
||||
logerror("interrupt_line_w %02x\n", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER (pci_bridge_device::interrupt_pin_r)
|
||||
{
|
||||
logerror("%s: interrupt_pin_r\n", tag());
|
||||
logerror("interrupt_pin_r\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER (pci_bridge_device::interrupt_pin_w)
|
||||
{
|
||||
logerror("%s: interrupt_pin_w %02x\n", tag(), data);
|
||||
logerror("interrupt_pin_w %02x\n", data);
|
||||
}
|
||||
|
||||
READ16_MEMBER (pci_bridge_device::bridge_control_r)
|
||||
@ -778,7 +778,7 @@ READ16_MEMBER (pci_bridge_device::bridge_control_r)
|
||||
WRITE16_MEMBER(pci_bridge_device::bridge_control_w)
|
||||
{
|
||||
COMBINE_DATA(&bridge_control);
|
||||
logerror("%s: bridge_control_w %04x\n", tag(), bridge_control);
|
||||
logerror("bridge_control_w %04x\n", bridge_control);
|
||||
}
|
||||
|
||||
|
||||
|
||||
24
src/devices/video/mga2064w.cpp
Normal file
24
src/devices/video/mga2064w.cpp
Normal file
@ -0,0 +1,24 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
#include "mga2064w.h"
|
||||
|
||||
const device_type MGA2064W = &device_creator<mga2064w_device>;
|
||||
|
||||
mga2064w_device::mga2064w_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: pci_device(mconfig, MGA2064W, "Matrox Millenium", tag, owner, clock, "mga2064w", __FILE__)
|
||||
{
|
||||
}
|
||||
|
||||
void mga2064w_device::device_start()
|
||||
{
|
||||
pci_device::device_start();
|
||||
// add_map( 16*1024*1024, M_MEM, FUNC(mga2064w_device::map1));
|
||||
// add_map(256*1024*1024, M_MEM, FUNC(mga2064w_device::map2));
|
||||
// add_map( 16*1024*1024, M_MEM, FUNC(mga2064w_device::map3));
|
||||
// add_rom_from_region();
|
||||
}
|
||||
|
||||
void mga2064w_device::device_reset()
|
||||
{
|
||||
pci_device::device_reset();
|
||||
}
|
||||
24
src/devices/video/mga2064w.h
Normal file
24
src/devices/video/mga2064w.h
Normal file
@ -0,0 +1,24 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
#ifndef MGA2064W_H
|
||||
#define MGA2064W_H
|
||||
|
||||
#include "machine/pci.h"
|
||||
|
||||
#define MCFG_MGA2064W_ADD(_tag) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, MGA2064W, 0x102b0519, 0x01, 0x030000, 0x00000000)
|
||||
|
||||
class mga2064w_device : public pci_device {
|
||||
public:
|
||||
mga2064w_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
private:
|
||||
};
|
||||
|
||||
extern const device_type MGA2064W;
|
||||
|
||||
#endif
|
||||
219
src/mame/drivers/pcipc.cpp
Normal file
219
src/mame/drivers/pcipc.cpp
Normal file
@ -0,0 +1,219 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
|
||||
/*
|
||||
Sandbox experiment on a new-pci pc
|
||||
|
||||
Virtual hardware:
|
||||
- A pentium as main CPU
|
||||
- A Micronics M55HI-Plus PCI/ISA motherboard without integrated sound
|
||||
-> intel 430hx, aka 82439hx northbridge (pci, no agp)
|
||||
-> intel piix3, aka 82371sb southbridge (pci-isa bridge, ide, ioapic, timer, irq, dma, usb)
|
||||
-> smsc fdc37c93x superio (isa-connected, keyboard, rtc, fdc, rs232, ide)
|
||||
- A Matrox Millenium PCI video card
|
||||
|
||||
We'll see about sound, networking, etc later
|
||||
|
||||
*/
|
||||
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/i386/i386.h"
|
||||
#include "machine/pci.h"
|
||||
#include "machine/pci-ide.h"
|
||||
#include "machine/i82439hx.h"
|
||||
#include "machine/i82371sb.h"
|
||||
//#include "machine/fdc37c93x.h"
|
||||
#include "video/mga2064w.h"
|
||||
|
||||
class pcipc_state : public driver_device
|
||||
{
|
||||
public:
|
||||
struct boot_state_info {
|
||||
UINT8 val;
|
||||
const char *const message;
|
||||
};
|
||||
|
||||
static const boot_state_info boot_state_infos[];
|
||||
|
||||
DECLARE_WRITE8_MEMBER(boot_state_w);
|
||||
|
||||
pcipc_state(const machine_config &mconfig, device_type type, const char *tag);
|
||||
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
||||
|
||||
};
|
||||
|
||||
pcipc_state::pcipc_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag)
|
||||
{
|
||||
}
|
||||
|
||||
void pcipc_state::machine_start()
|
||||
{
|
||||
}
|
||||
|
||||
void pcipc_state::machine_reset()
|
||||
{
|
||||
}
|
||||
|
||||
const pcipc_state::boot_state_info pcipc_state::boot_state_infos[] = {
|
||||
{ 0x02, "Verify Real Mode." },
|
||||
{ 0x04, "Get CPU type." },
|
||||
{ 0x06, "Initialize system hardware." },
|
||||
{ 0x08, "Initialize chipset registers with initial POST values." },
|
||||
{ 0x09, "Get in POST Reg." },
|
||||
{ 0x0A, "Initialize CPU registers." },
|
||||
{ 0x0C, "Initialize cache initial POST values." },
|
||||
{ 0x0E, "Initialize I/O." },
|
||||
{ 0x0F, "Initialize the localbus IDE." },
|
||||
{ 0x10, "Initialize Power Management." },
|
||||
{ 0x11, "Load alternate registers with initial POST values." },
|
||||
{ 0x12, "Jump to UserPatch0." },
|
||||
{ 0x14, "Initialize keyboard controller." },
|
||||
{ 0x16, "BIOS ROM checksum." },
|
||||
{ 0x18, "8254 timer initialization." },
|
||||
{ 0x1A, "8237 DMA controller initialization." },
|
||||
{ 0x1C, "Reset Programmable Interrupt Controller." },
|
||||
{ 0x20, "Test DRAM refresh." },
|
||||
{ 0x22, "Test 8742 Keyboard Controller." },
|
||||
{ 0x24, "Set ES segment register to 4 GB." },
|
||||
{ 0x28, "Autosize DRAM." },
|
||||
{ 0x2A, "Clear 512K base RAM." },
|
||||
{ 0x2C, "Test 512K base address lines." },
|
||||
{ 0x2E, "Test 512K base memory." },
|
||||
{ 0x32, "Test CPU bus-clock frequency." },
|
||||
{ 0x34, "Test CMOS RAM." },
|
||||
{ 0x35, "Initialize alternate chipset registers." },
|
||||
{ 0x37, "Reinitialize the chipset (MB only)." },
|
||||
{ 0x38, "Shadow system BIOS ROM." },
|
||||
{ 0x39, "Reinitialize the cache (MB only)." },
|
||||
{ 0x3A, "Autosize cache." },
|
||||
{ 0x3C, "Configure advanced chipset registers." },
|
||||
{ 0x3D, "Load alternate registers with CMOS values." },
|
||||
{ 0x40, "Set initial CPU speed." },
|
||||
{ 0x42, "Initialize interrupt vectors." },
|
||||
{ 0x44, "Initialize BIOS interrupts." },
|
||||
{ 0x46, "Check ROM copyright notice." },
|
||||
{ 0x47, "Initialize manager for PCI Option ROMs." },
|
||||
{ 0x48, "Check video configuration against CMOS." },
|
||||
{ 0x49, "Initialize PCI bus and devices." },
|
||||
{ 0x4A, "Initialize all video adapters in system." },
|
||||
{ 0x4C, "Shadow video BIOS ROM." },
|
||||
{ 0x4E, "Display copyright notice." },
|
||||
{ 0x50, "Display CPU type and speed." },
|
||||
{ 0x51, "Initialize EISA board." },
|
||||
{ 0x52, "Test keyboard." },
|
||||
{ 0x54, "Set key click if enabled." },
|
||||
{ 0x56, "Enable keyboard." },
|
||||
{ 0x58, "Test for unexpected interrupts." },
|
||||
{ 0x5A, "Display prompt \"Press F2 to enter SETUP\"." },
|
||||
{ 0x5C, "Test RAM between 512 and 640k." },
|
||||
{ 0x60, "Test extended memory." },
|
||||
{ 0x62, "Test extended memory address lines." },
|
||||
{ 0x64, "Jump to UserPatch1." },
|
||||
{ 0x66, "Configure advanced cache registers." },
|
||||
{ 0x68, "Enable external and CPU caches." },
|
||||
{ 0x6A, "Display external cache size." },
|
||||
{ 0x6C, "Display shadow message." },
|
||||
{ 0x6E, "Display non-disposable segments." },
|
||||
{ 0x70, "Display error messages." },
|
||||
{ 0x72, "Check for configuration errors." },
|
||||
{ 0x74, "Test real-time clock." },
|
||||
{ 0x76, "Check for keyboard errors." },
|
||||
{ 0x7C, "Set up hardware interrupt vectors." },
|
||||
{ 0x7E, "Test coprocessor if present." },
|
||||
{ 0x80, "Disable onboard I/O ports." },
|
||||
{ 0x82, "Detect and install external RS232 ports." },
|
||||
{ 0x84, "Detect and install external parallel ports." },
|
||||
{ 0x86, "Re-initialize on-board I/O ports." },
|
||||
{ 0x88, "Initialize BIOSData Area." },
|
||||
{ 0x8A, "Initialize Extended BIOS Data Area." },
|
||||
{ 0x8C, "Initialize floppy controller." },
|
||||
{ 0x90, "Initialize hard-disk controller." },
|
||||
{ 0x91, "Initialize localbus hard-disk controller." },
|
||||
{ 0x92, "Jump to UserPatch2." },
|
||||
{ 0x93, "Build MPTABLE for multi-processor boards." },
|
||||
{ 0x94, "Disable A20 address line." },
|
||||
{ 0x96, "Clear huge ES segment register." },
|
||||
{ 0x98, "Search for option ROMs." },
|
||||
{ 0x9A, "Shadow option ROMs." },
|
||||
{ 0x9C, "Set up Power Management." },
|
||||
{ 0x9E, "Enable hardware interrupts." },
|
||||
{ 0xA0, "Set time of day." },
|
||||
{ 0xA2, "Check key lock." },
|
||||
{ 0xA4, "Initialize typematic rate." },
|
||||
{ 0xA8, "Erase F2 prompt." },
|
||||
{ 0xAA, "Scan for F2 keystroke." },
|
||||
{ 0xAC, "Enter SETUP." },
|
||||
{ 0xAE, "Clear in-POST flag." },
|
||||
{ 0xB0, "Check for errors." },
|
||||
{ 0xB2, "POST done - prepare to boot operating system." },
|
||||
{ 0xB4, "One beep." },
|
||||
{ 0xB6, "Check password (optional)." },
|
||||
{ 0xB8, "Clear global descriptor table." },
|
||||
{ 0xBC, "Clear parity checkers." },
|
||||
{ 0xBE, "Clear screen (optional)." },
|
||||
{ 0xBF, "Check virus and backup reminders." },
|
||||
{ 0xC0, "Try to boot with INT 19." },
|
||||
{ 0xD0, "Interrupt handler error." },
|
||||
{ 0xD2, "Unknown interrupt error." },
|
||||
{ 0xD4, "Pending Interrupt." },
|
||||
{ 0xD6, "Initialize option ROM error." },
|
||||
{ 0xD8, "Shutdown error." },
|
||||
{ 0xDA, "Extended Block Move." },
|
||||
{ 0xDC, "Shutdown 10 error." },
|
||||
{ 0xE2, "Initialize the chipset." },
|
||||
{ 0xE3, "Initialize refresh counter." },
|
||||
{ 0xE4, "Check for Forced Flash." },
|
||||
{ 0xE5, "Check HW status of ROM." },
|
||||
{ 0xE6, "BIOS ROM is OK." },
|
||||
{ 0xE7, "Do a complete RAM test." },
|
||||
{ 0xE8, "Do OEM initialization." },
|
||||
{ 0xE9, "Initialize interrupt controller." },
|
||||
{ 0xEA, "Read in the bootstrap code." },
|
||||
{ 0xEB, "Initialize all vectors." },
|
||||
{ 0xEC, "Boot the Flash program." },
|
||||
{ 0xED, "Initialize the boot device." },
|
||||
{ 0xEE, "Boot code was read OK." },
|
||||
{ 0, nullptr }
|
||||
};
|
||||
|
||||
WRITE8_MEMBER(pcipc_state::boot_state_w)
|
||||
{
|
||||
const char *desc = "";
|
||||
for(int i=0; boot_state_infos[i].message; i++)
|
||||
if(boot_state_infos[i].val == data) {
|
||||
desc = boot_state_infos[i].message;
|
||||
break;
|
||||
}
|
||||
logerror("Boot state %02x - %s\n", data, desc);
|
||||
|
||||
}
|
||||
|
||||
static MACHINE_CONFIG_START(pcipc, pcipc_state)
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 66000000)
|
||||
|
||||
MCFG_PCI_ROOT_ADD( ":pci")
|
||||
MCFG_I82439HX_ADD( ":pci:00.0", ":maincpu", 256*1024*1024)
|
||||
MCFG_I82371SB_ISA_ADD(":pci:07.0")
|
||||
MCFG_I82371SB_BOOT_STATE_HOOK(DEVWRITE8(":", pcipc_state, boot_state_w))
|
||||
// MCFG_IDE_PCI_ADD( ":pci:07.1", 0x80867010, 0x03, 0x00000000)
|
||||
MCFG_MGA2064W_ADD( ":pci:12.0")
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
ROM_START(pcipc)
|
||||
ROM_REGION32_LE(0x40000, ":pci:07.0", 0) /* PC bios */
|
||||
ROM_SYSTEM_BIOS(0, "n7ns04", "Version 21/01/98, without integrated sound") \
|
||||
ROMX_LOAD("m7ns04.rom", 0x00000, 0x40000, CRC(9c1f656b) SHA1(f4a0a522d8c47b6ddb6c01fe9a34ddf5b1977f8d), ROM_BIOS(1) ) \
|
||||
ROM_SYSTEM_BIOS(1, "n7s04", "Version 21/01/98, with integrated sound") \
|
||||
ROMX_LOAD("m7s04.rom", 0x00000, 0x40000, CRC(3689f5a9) SHA1(8daacdb0dc6783d2161680564ffe83ac2515f7ef), ROM_BIOS(2) ) \
|
||||
ROM_SYSTEM_BIOS(2, "crisis", "Version 07/01/98, for flash recovery") \
|
||||
ROMX_LOAD("crisis.rom", 0x00000, 0x40000, CRC(38a1458a) SHA1(8881ac336392cca79a772b4168f63efc31f953dd), ROM_BIOS(3) ) \
|
||||
ROM_END
|
||||
|
||||
static INPUT_PORTS_START(pcipc)
|
||||
INPUT_PORTS_END
|
||||
|
||||
COMP(1998, pcipc, 0, 0, pcipc, pcipc, driver_device, 0, "Hack Inc.", "Sandbox PCI PC", MACHINE_NO_SOUND)
|
||||
@ -29547,6 +29547,9 @@ pcg850v // Pocket Computer G850V
|
||||
pcfx // PC-FX NEC 1994
|
||||
pcfxga // PC-FX NEC 199? (PC-FX on a PC ISA Card)
|
||||
|
||||
@source:pcipc.cpp
|
||||
pcipc //
|
||||
|
||||
@source:pcktgal.cpp
|
||||
pcktgal // (c) 1987 Data East Corporation (Japan)
|
||||
pcktgal2 // (c) 1989 Data East Corporation (World?)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user