diff --git a/src/devices/machine/hd63450.h b/src/devices/machine/hd63450.h
index 8bda96bbcf6..8f0e6a654ad 100644
--- a/src/devices/machine/hd63450.h
+++ b/src/devices/machine/hd63450.h
@@ -95,24 +95,24 @@ protected:
 private:
 	struct hd63450_regs
 	{  // offsets in bytes
-		unsigned char csr;  // [00] Channel status register (R/W)
-		unsigned char cer;  // [01] Channel error register (R)
-		unsigned char dcr;  // [04] Device control register (R/W)
-		unsigned char ocr;  // [05] Operation control register (R/W)
-		unsigned char scr;  // [06] Sequence control register (R/W)
-		unsigned char ccr;  // [07] Channel control register (R/W)
-		unsigned short mtc;  // [0a,0b]  Memory Transfer Counter (R/W)
-		unsigned long mar;  // [0c-0f]  Memory Address Register (R/W)
-		unsigned long dar;  // [14-17]  Device Address Register (R/W)
-		unsigned short btc;  // [1a,1b]  Base Transfer Counter (R/W)
-		unsigned long bar;  // [1c-1f]  Base Address Register (R/W)
-		unsigned char niv;  // [25]  Normal Interrupt Vector (R/W)
-		unsigned char eiv;  // [27]  Error Interrupt Vector (R/W)
-		unsigned char mfc;  // [29]  Memory Function Code (R/W)
-		unsigned char cpr;  // [2d]  Channel Priority Register (R/W)
-		unsigned char dfc;  // [31]  Device Function Code (R/W)
-		unsigned char bfc;  // [39]  Base Function Code (R/W)
-		unsigned char gcr;  // [3f]  General Control Register (R/W)
+		uint8_t csr;  // [00] Channel status register (R/W)
+		uint8_t cer;  // [01] Channel error register (R)
+		uint8_t dcr;  // [04] Device control register (R/W)
+		uint8_t ocr;  // [05] Operation control register (R/W)
+		uint8_t scr;  // [06] Sequence control register (R/W)
+		uint8_t ccr;  // [07] Channel control register (R/W)
+		uint16_t mtc; // [0a,0b]  Memory Transfer Counter (R/W)
+		uint32_t mar; // [0c-0f]  Memory Address Register (R/W)
+		uint32_t dar; // [14-17]  Device Address Register (R/W)
+		uint16_t btc; // [1a,1b]  Base Transfer Counter (R/W)
+		uint32_t bar; // [1c-1f]  Base Address Register (R/W)
+		uint8_t niv;  // [25]  Normal Interrupt Vector (R/W)
+		uint8_t eiv;  // [27]  Error Interrupt Vector (R/W)
+		uint8_t mfc;  // [29]  Memory Function Code (R/W)
+		uint8_t cpr;  // [2d]  Channel Priority Register (R/W)
+		uint8_t dfc;  // [31]  Device Function Code (R/W)
+		uint8_t bfc;  // [39]  Base Function Code (R/W)
+		uint8_t gcr;  // [3f]  General Control Register (R/W)
 	};
 
 	devcb_write8 m_dma_end;
@@ -126,8 +126,8 @@ private:
 	// internal state
 	hd63450_regs m_reg[4];
 	emu_timer* m_timer[4];  // for timing data reading/writing each channel
-	int m_transfer_size[4];
-	int m_halted[4];  // non-zero if a channel has been halted, and can be continued later.
+	uint16_t m_transfer_size[4];
+	bool m_halted[4];  // non-zero if a channel has been halted, and can be continued later.
 	required_device<cpu_device> m_cpu;
 	bool m_drq_state[4];