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cpu/e132xs: Improved comment about model differences.
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@ -4,33 +4,31 @@
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Hyperstone cpu emulator
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written by Pierpaolo Prazzoli
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All the types are compatible, but they have different IRAM size and cycles
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Hyperstone models:
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Model Core IRAM Process Bus Package
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E1-16T E1 4 KiB DRAM 16-bit 100-pin TQFP
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E1-32T E1 4 KiB DRAM 32-bit 144-pin TQFP
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E1-32N E1 4 KiB DRAM 32-bit 160-pin PQFP
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E1-16XT E1-X 8 KiB DRAM 0.5 µm 16-bit 100-pin TQFP
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E1-32XT E1-X 8 KiB DRAM 0.5 µm 32-bit 144-pin TQFP
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E1-32XN E1-X 8 KiB DRAM 0.5 µm 32-bit 160-pin PQFP
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E1-16XS E1-XS 16 KiB SRAM 0.25 µm 16-bit 100-pin LQFP
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E1-16XSB E1-XS 16 KiB SRAM 0.25 µm 16-bit 100-pin TFBGA
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E1-32XS E1-XS 16 KiB SRAM 0.25 µm 32-bit 144-pin LQFP
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E1-16XSR E1-XSR 16 KiB SRAM 0.25 µm 16-bit 100-pin LQFP
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E1-32XSR E1-XSR 16 KiB SRAM 0.25 µm 32-bit 144-pin LQFP
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Model Core Bus IRAM Maximum core frequency Process Package
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E1-16T E1 16-bit 4 KiB DRAM 66 MHz @ 5.0 V 100-pin TQFP
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E1-32T E1 32-bit 4 KiB DRAM 66 MHz @ 5.0 V 144-pin TQFP
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E1-32N E1 32-bit 4 KiB DRAM 66 MHz @ 5.0 V 160-pin PQFP
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E1-16XT E1-X 16-bit 8 KiB DRAM 80 MHz @ 5.0 V, 53 MHz @ 3.3V 0.5 µm 100-pin TQFP
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E1-32XT E1-X 32-bit 8 KiB DRAM 80 MHz @ 5.0 V, 53 MHz @ 3.3V 0.5 µm 144-pin TQFP
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E1-32XN E1-X 32-bit 8 KiB DRAM 80 MHz @ 5.0 V, 53 MHz @ 3.3V 0.5 µm 160-pin PQFP
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E1-16XS E1-XS 16-bit 16 KiB SRAM 115 MHz 0.25 µm 100-pin LQFP
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E1-16XSB E1-XS 16-bit 16 KiB SRAM 115 MHz 0.25 µm 100-pin TFBGA
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E1-32XS E1-XS 32-bit 16 KiB SRAM 115 MHz 0.25 µm 144-pin LQFP
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E1-16XSR E1-XSR 16-bit 16 KiB SRAM 128 MHz 0.25 µm 100-pin LQFP
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E1-32XSR E1-XSR 32-bit 16 KiB SRAM 128 MHz 0.25 µm 144-pin LQFP
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Hynix models:
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Model Core IRAM Process Bus Package
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GMS30C2116 E1 4 KiB DRAM 0.6 µm 16-bit 100-pin TQFP
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GMS30C2132 E1 4 KiB DRAM 0.6 µm 32-bit 144-pin TQFP, 160-pin MQFP
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GMS30C2216 E1-X 8 KiB DRAM 0.35 µm 16-bit 100-pin TQFP
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GMS30C2232 E1-X 8 KiB DRAM 0.35 µm 32-bit 144-pin TQFP, 160-pin MQFP
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Model Core Bus IRAM Maximum core frequency Process Package
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GMS30C2116 E1 16-bit 4 KiB DRAM 66 MHz @ 5.0 V, 40 MHz @ 3.3 V 0.6 µm 100-pin TQFP
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GMS30C2132 E1 32-bit 4 KiB DRAM 66 MHz @ 5.0 V, 40 MHz @ 3.3 V 0.6 µm 144-pin TQFP, 160-pin MQFP
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GMS30C2216 E1-X 16-bit 8 KiB DRAM 108 MHz 0.35 µm 100-pin TQFP
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GMS30C2232 E1-X 32-bit 8 KiB DRAM 108 MHz 0.35 µm 144-pin TQFP, 160-pin MQFP
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E1-X changes:
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* Added PLL with up to 4* multiplication
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* Adds PLL with up to 4* multiplication
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* Increases IRAM to 8 KiB
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* Adds MEM0 EDO DRAM support
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* Adds MEM0/MEM1/MEM2/MEM3 parity support
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@ -40,6 +38,7 @@
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* Moves power down from MCR to an I/O address
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E-1XS changes:
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* Changes to 3.3 V I/O voltage and 2.5 V core voltage
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* Increases PLL options to up to 8* multiplication
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* Increases IRAM to 16 KiB
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* Changes IRAM to SRAM
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@ -51,6 +50,24 @@
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* Adds more DRAM clock configuration options
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* Removes MEM0/MEM1/MEM2 byte write strobe/byte enable selection
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The Hynix models are generally similar to the Hyperstone models
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based on the same core with minor differences:
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* Hynix models are fabricated with smaller feature sizes
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* The GMS30C2216 and GMS30C2232 support higher core frequencies
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* The GMS30C2216 and GMS30C2232 only support a 3.3 V power supply
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* The GMS30C2216 and GMS30C2232 lack bus output voltage and input
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threshold selection (inputs are 5 V tolerant)
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* Hynix offered a 160-pin MQFP package rather than LQFP
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Backwards compatibility is fairly good across models.
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Incompatibilities include:
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* Power supply and bus voltages changed
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* Additional memory types and features are supported on later models
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* Only the E1-X and E1-XS support memory byte write strobe signals
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* The E1-XSR changes the available DRAM timing options
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* PLL control bits added to the TPR register
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* The BCR, MCR and SDCR register formats change in incompatible ways
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TODO:
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- All instructions should clear the H flag (not just MOV/MOVI)
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- Fix behaviour of branches in delay slots for recompiler
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@ -576,7 +593,9 @@ void hyperstone_x_device::update_memory_control()
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{
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const uint32_t val = m_core->global_regs[MCR_REGISTER];
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// GMS30C22xx drops bus output voltage/input threshold selecting while E1-X apparently doesn't
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// GMS30C2216 and GMS30C2232 drop bus output voltage/input
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// threshold selection as they only support 3.3V power supply
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// and have 5V tolerant inputs.
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static char const *const entrymap[8] = { "MEM0", "MEM1", "MEM2", "IRAM", "reserved", "reserved", "reserved", "MEM3" };
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LOG("%s: Set MCR = 0x%08x, entry map in %s, %s output voltage, input threshold for VDD=%sV\n",
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@ -832,7 +832,7 @@ void gstream_state::machine_reset()
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void gstream_state::gstream(machine_config &config)
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{
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/* basic machine hardware */
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E132X(config, m_maincpu, 16000000*4); /* 4x internal multiplier */
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E132X(config, m_maincpu, 16'000'000*4); // E1-32XT (TQFP), 4x internal multiplier
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m_maincpu->set_addrmap(AS_PROGRAM, &gstream_state::gstream_32bit_map);
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m_maincpu->set_addrmap(AS_IO, &gstream_state::gstream_io);
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m_maincpu->set_vblank_int("screen", FUNC(gstream_state::irq0_line_hold));
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@ -861,7 +861,7 @@ void gstream_state::gstream(machine_config &config)
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void gstream_state::x2222(machine_config &config)
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{
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/* basic machine hardware */
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E132X(config, m_maincpu, 16000000*4); /* 4x internal multiplier */
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E132X(config, m_maincpu, 16'000'000*4); // E1-32XT (TQFP) 4x internal multiplier
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m_maincpu->set_addrmap(AS_PROGRAM, &gstream_state::x2222_32bit_map);
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m_maincpu->set_addrmap(AS_IO, &gstream_state::x2222_io);
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m_maincpu->set_vblank_int("screen", FUNC(gstream_state::irq0_line_hold));
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