Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-04 16:34:53 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

Created macro libraries for CD4XXX and 74XX chip families. Going

Browse Source 
forward, these will contain all devices which can be described using
truthtables and DIPPINS. [Couriersud]
This commit is contained in:
couriersud 2015-07-11 19:14:18 +02:00
parent 0aa5a8e5bb
commit d97724dfb6
15 changed files with 272 additions and 125 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

109
nl_examples/congoBongo.c
View File

@ -9,24 +9,12 @@
#ifndef __PLIB_PREPROCESSOR__
#define DM7416_GATE(_name) \
NET_REGISTER_DEV_X(DM7416_GATE, _name)
#define DM7416_DIP(_name) \
NET_REGISTER_DEV_X(DM7416_DIP, _name)
#define MB3614_DIP(_name) \
NET_REGISTER_DEV_X(MB3614_DIP, _name)
#define LM358_DIP(_name) \
NET_REGISTER_DEV_X(LM358_DIP, _name)
#define CD4001_NOR(_name) \
NET_REGISTER_DEV_X(CD4001_NOR, _name)
#define CD4001_DIP(_name) \
NET_REGISTER_DEV_X(CD4001_DIP, _name)
#define G501534_DIP(_name) \
NET_REGISTER_DEV_X(G501534_DIP, _name)
@ -90,7 +78,7 @@ NETLIST_START(dummy)
INCLUDE(CongoBongo_schematics)
OPTIMIZE_FRONTIER(C51.1, RES_K(50), 50)
OPTIMIZE_FRONTIER(C51.1, RES_K(20), 50)
OPTIMIZE_FRONTIER(R77.2, RES_K(20), 50)
OPTIMIZE_FRONTIER(C25.2, RES_K(240), 50)
@ -237,7 +225,7 @@ NETLIST_START(CongoBongo_schematics)
CD4001_DIP(XU18)
CD4538_DIP(XU19)
MM5837_DIP(XU20)
DM7416_DIP(XU6)
TTL_7416_DIP(XU6)
NET_C(D1.A, C21.2, R23.1)
NET_C(D1.K, C20.1, R22.1)
NET_C(XU13.1, C37.2, C36.1, R48.1)
@ -381,7 +369,7 @@ NETLIST_START(opamp_mod)
RES(RP1, 1e6)
CAP(CP1, 0.0318e-6)
#else
PARAM(G1.G, 0.0002)
PARAM(G1.G, 0.002)
PARAM(G1.CURLIM, 0.002)
RES(RP1, 9.5e6)
CAP(CP1, 0.0033e-6)
@ -423,7 +411,7 @@ NETLIST_START(opamp_mod)
NETLIST_END()
NETLIST_START(MB3614_DIP)
#if 1
#if 0
SUBMODEL(opamp_mod, op1)
SUBMODEL(opamp_mod, op2)
SUBMODEL(opamp_mod, op3)
@ -432,89 +420,37 @@ NETLIST_START(MB3614_DIP)
/* The opamp actually has an FPF of about 500k. This doesn't work here and causes oscillations.
* FPF here therefore about half the Solver clock.
*/
OPAMP(op1, ".model MB3614 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=11k SLEW=0.6M RI=1000k RO=50 DAB=0.002)")
OPAMP(op1, ".model MB3614 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=110k SLEW=0.6M RI=1000k RO=50 DAB=0.002)")
OPAMP(op2, ".model MB3614 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=11k SLEW=0.6M RI=1000k RO=50 DAB=0.002)")
OPAMP(op3, ".model MB3614 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=11k SLEW=0.6M RI=1000k RO=50 DAB=0.002)")
OPAMP(op4, ".model MB3614 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=11k SLEW=0.6M RI=1000k RO=50 DAB=0.002)")
OPAMP(op4, ".model MB3614 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=110k SLEW=0.6M RI=1000k RO=50 DAB=0.002)")
#endif
ALIAS( 1, op1.OUT)
ALIAS( 2, op1.MINUS)
ALIAS( 3, op1.PLUS)
ALIAS( 7, op2.OUT)
ALIAS( 6, op2.MINUS)
ALIAS( 4, op1.VCC)
ALIAS( 5, op2.PLUS)
ALIAS( 6, op2.MINUS)
ALIAS( 7, op2.OUT)
ALIAS( 8, op3.OUT)
ALIAS( 9, op3.MINUS)
ALIAS(10, op3.PLUS)
ALIAS(14, op4.OUT)
ALIAS(13, op4.MINUS)
ALIAS(11, op1.GND)
ALIAS(12, op4.PLUS)
ALIAS(13, op4.MINUS)
ALIAS(14, op4.OUT)
NET_C(op1.GND, op2.GND, op3.GND, op4.GND)
NET_C(op1.VCC, op2.VCC, op3.VCC, op4.VCC)
ALIAS(11, op1.GND)
ALIAS( 4, op1.VCC)
NETLIST_END()
NETLIST_START(DM7416_DIP)
DM7416_GATE(s1)
DM7416_GATE(s2)
DM7416_GATE(s3)
DM7416_GATE(s4)
DM7416_GATE(s5)
DM7416_GATE(s6)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
ALIAS( 1, s1.A)
ALIAS( 2, s1.Q)
ALIAS( 3, s2.A)
ALIAS( 4, s2.Q)
ALIAS( 5, s3.A)
ALIAS( 6, s3.Q)
ALIAS( 7, GND.I)
ALIAS( 8, s4.Q)
ALIAS( 9, s4.A)
ALIAS(10, s5.Q)
ALIAS(11, s5.A)
ALIAS(12, s6.Q)
ALIAS(13, s6.A)
ALIAS(14, VCC.I)
NETLIST_END()
NETLIST_START(CD4001_DIP)
CD4001_NOR(s1)
CD4001_NOR(s2)
CD4001_NOR(s3)
CD4001_NOR(s4)
DUMMY_INPUT(VSS)
DUMMY_INPUT(VDD)
ALIAS( 1, s1.A)
ALIAS( 2, s1.B)
ALIAS( 3, s1.Q)
ALIAS( 4, s2.Q)
ALIAS( 5, s2.A)
ALIAS( 6, s2.B)
ALIAS( 7, VDD.I)
ALIAS( 8, s3.A)
ALIAS( 9, s3.B)
ALIAS(10, s3.Q)
ALIAS(11, s4.Q)
ALIAS(12, s4.A)
ALIAS(13, s4.B)
ALIAS(14, VSS.I)
NETLIST_END()
NETLIST_START(G501534_DIP)
AFUNC(f, 2, "A0 A1 0.2 * *")
@ -545,26 +481,9 @@ NETLIST_START(G501534_DIP)
NETLIST_END()
NETLIST_START(congob_lib)
TRUTHTABLE_START(DM7416_GATE, 1, 1, 0, "")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |15")
TT_LINE(" 1 | 0 |23")
TT_FAMILY(".model DM7416 FAMILY(IVL=0.8 IVH=2.0 OVL=0.1 OVH=4.95 ORL=10.0 ORH=1.0e8)")
TRUTHTABLE_END()
TRUTHTABLE_START(CD4001_NOR, 2, 1, 0, "")
TT_HEAD("A , B | Q ")
TT_LINE("0,0|1|85")
TT_LINE("X,1|0|120")
TT_LINE("1,X|0|120")
TT_FAMILY(".model CD4000 FAMILY(TYPE=CD4000)")
TRUTHTABLE_END()
//LOCAL_LIB_ENTRY(LM324_DIP)
//LOCAL_LIB_ENTRY(LM358_DIP)
LOCAL_LIB_ENTRY(CD4001_DIP)
LOCAL_LIB_ENTRY(DM7416_DIP)
LOCAL_LIB_ENTRY(MB3614_DIP)
LOCAL_LIB_ENTRY(G501534_DIP)

4
scripts/src/netlist.lua
View File

@ -152,4 +152,8 @@ project "netlist"
MAME_DIR .. "src/emu/netlist/devices/nld_signal.h",
MAME_DIR .. "src/emu/netlist/devices/nld_truthtable.c",
MAME_DIR .. "src/emu/netlist/devices/nld_truthtable.h",
MAME_DIR .. "src/emu/netlist/macro/TTL74XX.c",
MAME_DIR .. "src/emu/netlist/macro/TTL74XX.h",
MAME_DIR .. "src/emu/netlist/macro/CD4XXX.c",
MAME_DIR .. "src/emu/netlist/macro/CD4XXX.h",
}

2
src/emu/netlist/analog/nld_twoterm.h
View File

@ -241,7 +241,7 @@ public:
else
{
#if 1
const nl_double a = std::max((nVd - m_Vd) * m_VtInv, NL_FCONST(1e-1) - NL_FCONST(1.0));
const nl_double a = std::max((nVd - m_Vd) * m_VtInv, NL_FCONST(0.5) - NL_FCONST(1.0));
m_Vd = m_Vd + nl_math::e_log1p(a) * m_Vt;
#else
m_Vd = m_Vd + 10.0 * m_Vt * std::tanh((nVd - m_Vd) / 10.0 / m_Vt);

5
src/emu/netlist/devices/net_lib.c
View File

@ -41,6 +41,11 @@ NETLIST_START(bjt_models)
NET_MODEL(".model BC817-25 NPN(IS=9.198E-14 NF=1.003 ISE=4.468E-16 NE=1.65 BF=338.8 IKF=0.4913 VAF=107.9 NR=1.002 ISC=5.109E-15 NC=1.071 BR=29.48 IKR=0.193 VAR=25 RB=1 IRB=1000 RBM=1 RE=0.2126 RC=0.143 XTB=0 EG=1.11 XTI=3 CJE=3.825E-11 VJE=0.7004 MJE=0.364 TF=5.229E-10 XTF=219.7 VTF=3.502 ITF=7.257 PTF=0 CJC=1.27E-11 VJC=0.4431 MJC=0.3983 XCJC=0.4555 TR=7E-11 CJS=0 VJS=0.75 MJS=0.333 FC=0.905 Vceo=45 Icrating=500m mfg=Philips)")
NETLIST_END()
NETLIST_START(family_models)
NET_MODEL(".model 74XXOC FAMILY(IVL=0.8 IVH=2.0 OVL=0.1 OVH=4.95 ORL=10.0 ORH=1.0e8)")
NET_MODEL(".model CD4000 FAMILY(TYPE=CD4000)")
NETLIST_END()
#define xstr(s) # s
#define ENTRY1(_nic, _name, _defparam) factory.register_device<_nic>( # _name, xstr(_nic), _defparam );

4
src/emu/netlist/devices/net_lib.h
View File

@ -56,6 +56,9 @@
#include "nld_log.h"
#include "../macro/TTL74XX.h"
#include "../macro/CD4XXX.h"
#include "../analog/nld_bjt.h"
#include "../analog/nld_fourterm.h"
#include "../analog/nld_switches.h"
@ -67,6 +70,7 @@
NETLIST_EXTERNAL(diode_models)
NETLIST_EXTERNAL(bjt_models)
NETLIST_EXTERNAL(family_models)
namespace netlist {
void initialize_factory(netlist::factory_list_t &factory);

2
src/emu/netlist/devices/nld_4020.h
View File

@ -3,7 +3,7 @@
/*
* nld_4020.h
*
* CD4020: CMOS Ripple-Carry Binary Counters/Dividers
* CD4020: 14-Stage Ripple Carry Binary Counters
*
* +--------------+
* Q12 |1 ++ 16| VDD

2
src/emu/netlist/devices/nld_truthtable.h
View File

@ -36,7 +36,7 @@
ttd->m_desc.add(_x);
#define TT_FAMILY(_x) \
ttd->m_family = netlist::logic_family_desc_t::from_model(_x);
ttd->m_family = netlist::logic_family_desc_t::from_model(setup.get_model_str(_x));
#define TRUTHTABLE_END() \
setup.factory().register_device(ttd); \

54
src/emu/netlist/macro/CD4XXX.c Normal file
View File

@ -0,0 +1,54 @@
#include "CD4XXX.h"
#include "devices/nld_truthtable.h"
#include "devices/nld_system.h"
/*
* CD4001BC: Quad 2-Input NOR Buffered B Series Gate
*
* +--------------+
* A1 |1 ++ 14| VCC
* B1 |2 13| A6
* A2 |3 12| Y6
* Y2 |4 4001 11| A5
* A3 |5 10| Y5
* Y3 |6 9| A4
* GND |7 8| Y4
* +--------------+
*
*/
NETLIST_START(CD4001_DIP)
CD4001_NOR(s1)
CD4001_NOR(s2)
CD4001_NOR(s3)
CD4001_NOR(s4)
DUMMY_INPUT(VSS)
DUMMY_INPUT(VDD)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VSS.I,
s1.B, /* B1 |2 13| A6 */ s4.B,
s1.Q, /* A2 |3 12| Y6 */ s4.A,
s2.Q, /* Y2 |4 4001 11| A5 */ s4.Q,
s2.A, /* A3 |5 10| Y5 */ s3.Q,
s2.B, /* Y3 |6 9| A4 */ s3.B,
VDD.I, /* GND |7 8| Y4 */ s3.A
/* +--------------+ */
)
NETLIST_END()
NETLIST_START(CD4XXX_lib)
TRUTHTABLE_START(CD4001_NOR, 2, 1, 0, "")
TT_HEAD("A , B | Q ")
TT_LINE("0,0|1|85")
TT_LINE("X,1|0|120")
TT_LINE("1,X|0|120")
TT_FAMILY("CD4000")
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(CD4001_DIP)
NETLIST_END()

26
src/emu/netlist/macro/CD4XXX.h Normal file
View File

@ -0,0 +1,26 @@
#ifndef NLD_CD4XXX_H_
#define NLD_CD4XXX_H_
#include "../nl_setup.h"
#ifndef __PLIB_PREPROCESSOR__
/* ----------------------------------------------------------------------------
* Netlist Macros
* ---------------------------------------------------------------------------*/
#define CD4001_NOR(_name) \
NET_REGISTER_DEV_X(CD4001_NOR, _name)
#define CD4001_DIP(_name) \
NET_REGISTER_DEV_X(CD4001_DIP, _name)
/* ----------------------------------------------------------------------------
* External declarations
* ---------------------------------------------------------------------------*/
NETLIST_EXTERNAL(CD4XXX_lib)
#endif
#endif

55
src/emu/netlist/macro/TTL74XX.c Normal file
View File

@ -0,0 +1,55 @@
#include "TTL74XX.h"
#include "devices/nld_truthtable.h"
#include "devices/nld_system.h"
/*
* DM7416: Hex Inverting Buffers with
* High Voltage Open-Collector Outputs
*
* +--------------+
* A1 |1 ++ 14| VCC
* Y1 |2 13| A6
* A2 |3 12| Y6
* Y2 |4 7416 11| A5
* A3 |5 10| Y5
* Y3 |6 9| A4
* GND |7 8| Y4
* +--------------+
*
*/
NETLIST_START(TTL_7416_DIP)
TTL_7416_GATE(s1)
TTL_7416_GATE(s2)
TTL_7416_GATE(s3)
TTL_7416_GATE(s4)
TTL_7416_GATE(s5)
TTL_7416_GATE(s6)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VCC.I,
s1.Q, /* Y1 |2 13| A6 */ s6.A,
s2.A, /* A2 |3 12| Y6 */ s6.Q,
s2.Q, /* Y2 |4 7416 11| A5 */ s5.A,
s3.A, /* A3 |5 10| Y5 */ s5.Q,
s3.Q, /* Y3 |6 9| A4 */ s4.A,
GND.I, /* GND |7 8| Y4 */ s4.Q
/* +--------------+ */
)
NETLIST_END()
NETLIST_START(TTL74XX_lib)
TRUTHTABLE_START(TTL_7416_GATE, 1, 1, 0, "")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |15")
TT_LINE(" 1 | 0 |23")
/* Open Collector */
TT_FAMILY("74XXOC")
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(TTL_7416_DIP)
NETLIST_END()

26
src/emu/netlist/macro/TTL74XX.h Normal file
View File

@ -0,0 +1,26 @@
#ifndef NLD_TTL74XX_H_
#define NLD_TTL74XX_H_
#include "../nl_setup.h"
#ifndef __PLIB_PREPROCESSOR__
/* ----------------------------------------------------------------------------
* Netlist Macros
* ---------------------------------------------------------------------------*/
#define TTL_7416_GATE(_name) \
NET_REGISTER_DEV_X(TTL_7416_GATE, _name)
#define TTL_7416_DIP(_name) \
NET_REGISTER_DEV_X(TTL7416_DIP, _name)
/* ----------------------------------------------------------------------------
* External declarations
* ---------------------------------------------------------------------------*/
NETLIST_EXTERNAL(TTL74XX_lib)
#endif
#endif

32
src/emu/netlist/nl_parser.c
View File

@ -50,6 +50,7 @@ bool parser_t::parse(const char *buf, const pstring nlname)
m_tok_comma = register_token(",");
m_tok_ALIAS = register_token("ALIAS");
m_tok_DIPPINS = register_token("DIPPINS");
m_tok_NET_C = register_token("NET_C");
m_tok_FRONTIER = register_token("OPTIMIZE_FRONTIER");
m_tok_PARAM = register_token("PARAM");
@ -120,6 +121,8 @@ void parser_t::parse_netlist(ATTR_UNUSED const pstring &nlname)
if (token.is(m_tok_ALIAS))
net_alias();
else if (token.is(m_tok_DIPPINS))
dippins();
else if (token.is(m_tok_NET_C))
net_c();
else if (token.is(m_tok_FRONTIER))
@ -186,7 +189,7 @@ void parser_t::net_truthtable_start()
else if (token.is(m_tok_TT_FAMILY))
{
require_token(m_tok_param_left);
ttd->m_family = netlist::logic_family_desc_t::from_model(get_string());
ttd->m_family = netlist::logic_family_desc_t::from_model(m_setup.get_model_str(get_string()));
require_token(m_tok_param_right);
}
else
@ -298,6 +301,33 @@ void parser_t::net_c()
}
void parser_t::dippins()
{
pstring_list_t pins;
pins.add(get_identifier());
require_token(m_tok_comma);
while (true)
{
pstring t1 = get_identifier();
pins.add(t1);
token_t n = get_token();
if (n.is(m_tok_param_right))
break;
if (!n.is(m_tok_comma))
error("expected a comma, found <%s>", n.str().cstr());
}
if ((pins.size() % 2) == 1)
error("You must pass an equal number of pins to DIPPINS");
unsigned n = pins.size();
for (unsigned i = 0; i < n / 2; i++)
{
m_setup.register_alias(pstring::sprintf("%d", i+1), pins[i*2]);
m_setup.register_alias(pstring::sprintf("%d", n-i), pins[i*2 + 1]);
}
}
void parser_t::netdev_param()
{
pstring param;

2
src/emu/netlist/nl_parser.h
View File

@ -25,6 +25,7 @@ namespace netlist
void parse_netlist(const pstring &nlname);
void net_alias();
void dippins();
void netdev_param();
void net_c();
void frontier();
@ -51,6 +52,7 @@ namespace netlist
token_id_t m_tok_comma;
token_id_t m_tok_ALIAS;
token_id_t m_tok_NET_C;
token_id_t m_tok_DIPPINS;
token_id_t m_tok_FRONTIER;
token_id_t m_tok_PARAM;
token_id_t m_tok_NET_MODEL;

67
src/emu/netlist/nl_setup.c
View File

@ -26,9 +26,15 @@ static NETLIST_START(base)
LOCAL_SOURCE(diode_models)
LOCAL_SOURCE(bjt_models)
LOCAL_SOURCE(family_models)
LOCAL_SOURCE(TTL74XX_lib)
LOCAL_SOURCE(CD4XXX_lib)
INCLUDE(diode_models);
INCLUDE(bjt_models);
INCLUDE(family_models);
INCLUDE(TTL74XX_lib);
INCLUDE(CD4XXX_lib);
NETLIST_END()
@ -167,6 +173,19 @@ void setup_t::register_alias(const pstring &alias, const pstring &out)
register_alias_nofqn(alias_fqn, out_fqn);
}
void setup_t::register_dippins_arr(const pstring &terms)
{
pstring_list_t list(terms,", ");
if (list.size() == 0 || (list.size() % 2) == 1)
netlist().error("You must pass an equal number of pins to DIPPINS");
unsigned n = list.size();
for (unsigned i = 0; i < n / 2; i++)
{
register_alias(pstring::sprintf("%d", i+1), list[i * 2]);
register_alias(pstring::sprintf("%d", n-i), list[i * 2 + 1]);
}
}
pstring setup_t::objtype_as_astr(object_t &in) const
{
switch (in.type())
@ -193,6 +212,26 @@ pstring setup_t::objtype_as_astr(object_t &in) const
return "Error";
}
const pstring setup_t::get_model_str(const pstring val) const
{
if (val.startsWith(".model ") || val.find("(") >= 0)
{
return val;
}
else
{
pstring search = (".model " + val + " ").ucase();
for (std::size_t i=0; i < m_models.size(); i++)
{
if (m_models[i].ucase().startsWith(search))
return m_models[i];
}
netlist().error("Model %s not found\n", val.cstr());
return ""; /* please compiler */
}
}
void setup_t::register_object(device_t &dev, const pstring &name, object_t &obj)
{
switch (obj.type())
@ -255,32 +294,8 @@ void setup_t::register_object(device_t &dev, const pstring &name, object_t &obj)
}
break;
case param_t::MODEL:
{
if (val.startsWith(".model "))
{
dynamic_cast<param_model_t &>(param).initial(val);
}
else
{
pstring search = (".model " + val + " ").ucase();
bool found = false;
for (std::size_t i=0; i < m_models.size(); i++)
{
if (m_models[i].ucase().startsWith(search))
{
//int pl=m_models[i].find("(");
//int pr=m_models[i].find(")");
//dynamic_cast<netlist_param_model_t &>(param).initial(m_models[i].substr(pl+1,pr-pl-1));
dynamic_cast<param_model_t &>(param).initial(m_models[i]);
found = true;
break;
}
}
if (!found)
netlist().error("Model %s not found\n", val.cstr());
}
}
break;
dynamic_cast<param_model_t &>(param).initial(get_model_str(val));
break;
default:
netlist().error("Parameter is not supported %s : %s\n", name.cstr(), val.cstr());
}

7
src/emu/netlist/nl_setup.h
View File

@ -22,6 +22,9 @@
#define ALIAS(_alias, _name) \
setup.register_alias(# _alias, # _name);
#define DIPPINS(_pin1, ...) \
setup.register_dippins_arr( #_pin1 ", " # __VA_ARGS__);
#define NET_REGISTER_DEV(_type, _name) \
setup.register_dev(NETLIB_NAME_STR(_type), # _name);
@ -153,6 +156,8 @@ namespace netlist
void register_model(const pstring &model);
void register_alias(const pstring &alias, const pstring &out);
void register_dippins_arr(const pstring &terms);
void register_alias_nofqn(const pstring &alias, const pstring &out);
void register_link_arr(const pstring &terms);
@ -165,6 +170,8 @@ namespace netlist
void register_frontier(const pstring attach, const double r_IN, const double r_OUT);
void remove_connections(const pstring attach);
const pstring get_model_str(const pstring val) const;
void register_object(device_t &dev, const pstring &name, object_t &obj);
bool connect(core_terminal_t &t1, core_terminal_t &t2);