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Taito G-NET support

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New games added:
Chaos Heat [Olivier Galibert]
Super Puzzle Bobble [Olivier Galibert]
This commit is contained in:
Aaron Giles 2009-03-12 08:22:50 +00:00
parent 510ea30d71
commit d98a6ba381
9 changed files with 1014 additions and 264 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitattributes vendored
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@ -2075,6 +2075,7 @@ src/mame/drivers/taito_l.c svneol=native#text/plain
src/mame/drivers/taito_x.c svneol=native#text/plain
src/mame/drivers/taito_z.c svneol=native#text/plain
src/mame/drivers/taitoair.c svneol=native#text/plain
src/mame/drivers/taitogn.c svneol=native#text/plain
src/mame/drivers/taitojc.c svneol=native#text/plain
src/mame/drivers/taitopjc.c svneol=native#text/plain
src/mame/drivers/taitosj.c svneol=native#text/plain

232
src/emu/machine/idectrl.c
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@ -47,20 +47,22 @@
#define IDE_CONFIG_REGISTERS 0x10
#define IDE_ADDR_CONFIG_UNK 0x034
#define IDE_ADDR_CONFIG_REGISTER 0x038
#define IDE_ADDR_CONFIG_DATA 0x03c
#define BANK(b, v) (((v) << 4) | (b))
#define IDE_ADDR_DATA 0x1f0
#define IDE_ADDR_ERROR 0x1f1
#define IDE_ADDR_SECTOR_COUNT 0x1f2
#define IDE_ADDR_SECTOR_NUMBER 0x1f3
#define IDE_ADDR_CYLINDER_LSB 0x1f4
#define IDE_ADDR_CYLINDER_MSB 0x1f5
#define IDE_ADDR_HEAD_NUMBER 0x1f6
#define IDE_ADDR_STATUS_COMMAND 0x1f7
#define IDE_BANK0_DATA BANK(0, 0)
#define IDE_BANK0_ERROR BANK(0, 1)
#define IDE_BANK0_SECTOR_COUNT BANK(0, 2)
#define IDE_BANK0_SECTOR_NUMBER BANK(0, 3)
#define IDE_BANK0_CYLINDER_LSB BANK(0, 4)
#define IDE_BANK0_CYLINDER_MSB BANK(0, 5)
#define IDE_BANK0_HEAD_NUMBER BANK(0, 6)
#define IDE_BANK0_STATUS_COMMAND BANK(0, 7)
#define IDE_ADDR_STATUS_CONTROL 0x3f6
#define IDE_BANK1_STATUS_CONTROL BANK(1, 6)
#define IDE_BANK2_CONFIG_UNK BANK(2, 4)
#define IDE_BANK2_CONFIG_REGISTER BANK(2, 8)
#define IDE_BANK2_CONFIG_DATA BANK(2, 0xc)
#define IDE_COMMAND_READ_MULTIPLE 0x20
#define IDE_COMMAND_READ_MULTIPLE_ONCE 0x21
@ -79,6 +81,8 @@
#define IDE_COMMAND_ATAPI_IDENTIFY 0xa1
#define IDE_COMMAND_RECALIBRATE 0x10
#define IDE_COMMAND_IDLE_IMMEDIATE 0xe1
#define IDE_COMMAND_TAITO_GNET_UNLOCK_1 0xfe
#define IDE_COMMAND_TAITO_GNET_UNLOCK_2 0xfc
#define IDE_ERROR_NONE 0x00
#define IDE_ERROR_DEFAULT 0x01
@ -144,6 +148,7 @@ struct _ide_state
UINT8 config_register[IDE_CONFIG_REGISTERS];
UINT8 config_register_num;
chd_file *handle;
hard_disk_file *disk;
emu_timer * last_status_timer;
emu_timer * reset_timer;
@ -170,8 +175,8 @@ static TIMER_CALLBACK( read_sector_done_callback );
static void read_first_sector(ide_state *ide);
static void read_next_sector(ide_state *ide);
static UINT32 ide_controller_read(const device_config *device, offs_t offset, int size);
static void ide_controller_write(const device_config *device, offs_t offset, int size, UINT32 data);
static UINT32 ide_controller_read(const device_config *device, int bank, offs_t offset, int size);
static void ide_controller_write(const device_config *device, int bank, offs_t offset, int size, UINT32 data);
@ -427,13 +432,11 @@ static void swap_strncpy(UINT8 *dst, const char *src, int field_size_in_words)
}
static void ide_build_features(ide_state *ide)
static void ide_generate_features(ide_state *ide)
{
int total_sectors = ide->num_cylinders * ide->num_heads * ide->num_sectors;
int sectors_per_track = ide->num_heads * ide->num_sectors;
memset(ide->buffer, 0, IDE_DISK_SECTOR_SIZE);
/* basic geometry */
ide->features[ 0*2+0] = 0x5a; /* 0: configuration bits */
ide->features[ 0*2+1] = 0x04;
@ -586,6 +589,12 @@ static void ide_build_features(ide_state *ide)
}
static void ide_build_features(ide_state *ide)
{
memset(ide->features, 0, IDE_DISK_SECTOR_SIZE);
if (chd_get_metadata (ide->handle, HARD_DISK_IDENT_METADATA_TAG, 0, ide->features, IDE_DISK_SECTOR_SIZE, 0, 0, 0) != CHDERR_NONE)
ide_generate_features (ide);
}
/*************************************
*
@ -1160,6 +1169,28 @@ static void handle_command(ide_state *ide, UINT8 command)
signal_interrupt(ide);
break;
case IDE_COMMAND_TAITO_GNET_UNLOCK_1:
LOGPRINT(("IDE GNET Unlock 1\n"));
ide->sector_count = 1;
ide->status |= IDE_STATUS_DRIVE_READY;
ide->status &= ~IDE_STATUS_ERROR;
signal_interrupt(ide);
break;
case IDE_COMMAND_TAITO_GNET_UNLOCK_2:
LOGPRINT(("IDE GNET Unlock 2\n"));
/* reset the buffer */
ide->buffer_offset = 0;
ide->sectors_until_int = 0;
ide->dma_active = 0;
/* mark the buffer ready */
ide->status |= IDE_STATUS_BUFFER_READY;
signal_interrupt(ide);
break;
default:
LOGPRINT(("IDE unknown command (%02X)\n", command));
debugger_break(ide->device->machine);
@ -1175,33 +1206,33 @@ static void handle_command(ide_state *ide, UINT8 command)
*
*************************************/
static UINT32 ide_controller_read(const device_config *device, offs_t offset, int size)
static UINT32 ide_controller_read(const device_config *device, int bank, offs_t offset, int size)
{
ide_state *ide = get_safe_token(device);
UINT32 result = 0;
/* logit */
// if (offset != IDE_ADDR_DATA && offset != IDE_ADDR_STATUS_COMMAND && offset != IDE_ADDR_STATUS_CONTROL)
LOG(("%s:IDE read at %03X, size=%d\n", cpuexec_describe_context(device->machine), offset, size));
// if (BANK(bank, offset) != IDE_BANK0_DATA && BANK(bank, offset) != IDE_BANK0_STATUS_COMMAND && BANK(bank, offset) != IDE_BANK1_STATUS_CONTROL)
LOG(("%s:IDE read at %d:%X, size=%d\n", cpuexec_describe_context(device->machine), bank, offset, size));
switch (offset)
switch (BANK(bank, offset))
{
/* unknown config register */
case IDE_ADDR_CONFIG_UNK:
case IDE_BANK2_CONFIG_UNK:
return ide->config_unknown;
/* active config register */
case IDE_ADDR_CONFIG_REGISTER:
case IDE_BANK2_CONFIG_REGISTER:
return ide->config_register_num;
/* data from active config register */
case IDE_ADDR_CONFIG_DATA:
case IDE_BANK2_CONFIG_DATA:
if (ide->config_register_num < IDE_CONFIG_REGISTERS)
return ide->config_register[ide->config_register_num];
return 0;
/* read data if there's data to be read */
case IDE_ADDR_DATA:
case IDE_BANK0_DATA:
if (ide->status & IDE_STATUS_BUFFER_READY)
{
/* fetch the correct amount of data */
@ -1224,33 +1255,33 @@ static UINT32 ide_controller_read(const device_config *device, offs_t offset, in
break;
/* return the current error */
case IDE_ADDR_ERROR:
case IDE_BANK0_ERROR:
return ide->error;
/* return the current sector count */
case IDE_ADDR_SECTOR_COUNT:
case IDE_BANK0_SECTOR_COUNT:
return ide->sector_count;
/* return the current sector */
case IDE_ADDR_SECTOR_NUMBER:
case IDE_BANK0_SECTOR_NUMBER:
return ide->cur_sector;
/* return the current cylinder LSB */
case IDE_ADDR_CYLINDER_LSB:
case IDE_BANK0_CYLINDER_LSB:
return ide->cur_cylinder & 0xff;
/* return the current cylinder MSB */
case IDE_ADDR_CYLINDER_MSB:
case IDE_BANK0_CYLINDER_MSB:
return ide->cur_cylinder >> 8;
/* return the current head */
case IDE_ADDR_HEAD_NUMBER:
case IDE_BANK0_HEAD_NUMBER:
return ide->cur_head_reg;
/* return the current status and clear any pending interrupts */
case IDE_ADDR_STATUS_COMMAND:
case IDE_BANK0_STATUS_COMMAND:
/* return the current status but don't clear interrupts */
case IDE_ADDR_STATUS_CONTROL:
case IDE_BANK1_STATUS_CONTROL:
result = ide->status;
if (attotime_compare(timer_timeelapsed(ide->last_status_timer), TIME_PER_ROTATION) > 0)
{
@ -1259,7 +1290,7 @@ static UINT32 ide_controller_read(const device_config *device, offs_t offset, in
}
/* clear interrutps only when reading the real status */
if (offset == IDE_ADDR_STATUS_COMMAND)
if (BANK(bank, offset) == IDE_BANK0_STATUS_COMMAND)
{
if (ide->interrupt_pending)
clear_interrupt(ide);
@ -1284,34 +1315,34 @@ static UINT32 ide_controller_read(const device_config *device, offs_t offset, in
*
*************************************/
static void ide_controller_write(const device_config *device, offs_t offset, int size, UINT32 data)
static void ide_controller_write(const device_config *device, int bank, offs_t offset, int size, UINT32 data)
{
ide_state *ide = get_safe_token(device);
/* logit */
if (offset != IDE_ADDR_DATA)
LOG(("%s:IDE write to %03X = %08X, size=%d\n", cpuexec_describe_context(device->machine), offset, data, size));
switch (offset)
if (BANK(bank, offset) != IDE_BANK0_DATA)
LOG(("%s:IDE write to %d:%X = %08X, size=%d\n", cpuexec_describe_context(device->machine), bank, offset, data, size));
// fprintf(stderr, "ide write %03x %02x size=%d\n", offset, data, size);
switch (BANK(bank, offset))
{
/* unknown config register */
case IDE_ADDR_CONFIG_UNK:
case IDE_BANK2_CONFIG_UNK:
ide->config_unknown = data;
break;
/* active config register */
case IDE_ADDR_CONFIG_REGISTER:
case IDE_BANK2_CONFIG_REGISTER:
ide->config_register_num = data;
break;
/* data from active config register */
case IDE_ADDR_CONFIG_DATA:
case IDE_BANK2_CONFIG_DATA:
if (ide->config_register_num < IDE_CONFIG_REGISTERS)
ide->config_register[ide->config_register_num] = data;
break;
/* write data */
case IDE_ADDR_DATA:
case IDE_BANK0_DATA:
if (ide->status & IDE_STATUS_BUFFER_READY)
{
/* store the correct amount of data */
@ -1328,9 +1359,7 @@ static void ide_controller_write(const device_config *device, offs_t offset, int
if (ide->buffer_offset >= IDE_DISK_SECTOR_SIZE)
{
LOG(("%s:IDE completed PIO write\n", cpuexec_describe_context(device->machine)));
if (ide->command != IDE_COMMAND_SECURITY_UNLOCK)
continue_write(ide);
else
if (ide->command == IDE_COMMAND_SECURITY_UNLOCK)
{
if (ide->user_password_enable && memcmp(ide->buffer, ide->user_password, 2 + 32) == 0)
{
@ -1357,7 +1386,7 @@ static void ide_controller_write(const device_config *device, offs_t offset, int
mame_printf_debug("\n");
}
/* clear the busy adn error flags */
/* clear the busy and error flags */
ide->status &= ~IDE_STATUS_ERROR;
ide->status &= ~IDE_STATUS_BUSY;
ide->status &= ~IDE_STATUS_BUFFER_READY;
@ -1367,37 +1396,56 @@ static void ide_controller_write(const device_config *device, offs_t offset, int
else
ide->status |= IDE_STATUS_DRIVE_READY;
}
else if (ide->command == IDE_COMMAND_TAITO_GNET_UNLOCK_2)
{
UINT8 key[5] = { 0, 0, 0, 0, 0 };
int i, bad = 0;
chd_get_metadata (ide->handle, HARD_DISK_KEY_METADATA_TAG, 0, key, 5, 0, 0, 0);
for (i=0; !bad && i<512; i++)
bad = ((i < 2 || i >= 7) && ide->buffer[i]) || ((i >= 2 && i < 7) && ide->buffer[i] != key[i-2]);
ide->status &= ~IDE_STATUS_BUSY;
ide->status &= ~IDE_STATUS_BUFFER_READY;
if (bad)
ide->status |= IDE_STATUS_ERROR;
else
ide->status &= ~IDE_STATUS_ERROR;
}
else
continue_write(ide);
}
}
break;
/* precompensation offset?? */
case IDE_ADDR_ERROR:
case IDE_BANK0_ERROR:
ide->precomp_offset = data;
break;
/* sector count */
case IDE_ADDR_SECTOR_COUNT:
case IDE_BANK0_SECTOR_COUNT:
ide->sector_count = data ? data : 256;
break;
/* current sector */
case IDE_ADDR_SECTOR_NUMBER:
case IDE_BANK0_SECTOR_NUMBER:
ide->cur_sector = data;
break;
/* current cylinder LSB */
case IDE_ADDR_CYLINDER_LSB:
case IDE_BANK0_CYLINDER_LSB:
ide->cur_cylinder = (ide->cur_cylinder & 0xff00) | (data & 0xff);
break;
/* current cylinder MSB */
case IDE_ADDR_CYLINDER_MSB:
case IDE_BANK0_CYLINDER_MSB:
ide->cur_cylinder = (ide->cur_cylinder & 0x00ff) | ((data & 0xff) << 8);
break;
/* current head */
case IDE_ADDR_HEAD_NUMBER:
case IDE_BANK0_HEAD_NUMBER:
ide->cur_head = data & 0x0f;
ide->cur_head_reg = data;
// drive index = data & 0x10
@ -1405,12 +1453,12 @@ static void ide_controller_write(const device_config *device, offs_t offset, int
break;
/* command */
case IDE_ADDR_STATUS_COMMAND:
case IDE_BANK0_STATUS_COMMAND:
handle_command(ide, data);
break;
/* adapter control */
case IDE_ADDR_STATUS_CONTROL:
case IDE_BANK1_STATUS_CONTROL:
ide->adapter_control = data;
/* handle controller reset */
@ -1539,8 +1587,7 @@ static void ide_bus_master_write(const device_config *device, offs_t offset, int
*/
int ide_bus_r(const device_config *device, int select, int offset)
{
offset += select ? 0x3f0 : 0x1f0;
return ide_controller_read(device, offset, (offset == 0x1f0) ? 2 : 1);
return ide_controller_read(device, select ? 1 : 0, offset, select == 0 && offset == 0 ? 2 : 1);
}
/*
@ -1554,21 +1601,31 @@ int ide_bus_r(const device_config *device, int select, int offset)
*/
void ide_bus_w(const device_config *device, int select, int offset, int data)
{
offset += select ? 0x3f0 : 0x1f0;
if (offset == 0x1f0)
ide_controller_write(device, offset, 2, data);
if (select == 0 && offset == 0)
ide_controller_write(device, 0, 0, 2, data);
else
ide_controller_write(device, offset, 1, data & 0xff);
ide_controller_write(device, select ? 1 : 0, offset, 1, data & 0xff);
}
int ide_controller_r(const device_config *device, int reg)
UINT32 ide_controller_r(const device_config *device, int reg, int size)
{
return ide_controller_read(device, reg, 1);
if (reg >= 0x1f0 && reg < 0x1f8)
return ide_controller_read(device, 0, reg & 7, size);
if (reg >= 0x3f0 && reg < 0x3f8)
return ide_controller_read(device, 1, reg & 7, size);
if (reg >= 0x030 && reg < 0x040)
return ide_controller_read(device, 2, reg & 0xf, size);
return 0xffffffff;
}
void ide_controller_w(const device_config *device, int reg, int data)
void ide_controller_w(const device_config *device, int reg, int size, UINT32 data)
{
ide_controller_write(device, reg, 1, data);
if (reg >= 0x1f0 && reg < 0x1f8)
ide_controller_write(device, 0, reg & 7, size, data);
if (reg >= 0x3f0 && reg < 0x3f8)
ide_controller_write(device, 1, reg & 7, size, data);
if (reg >= 0x030 && reg < 0x040)
ide_controller_write(device, 2, reg & 0xf, size, data);
}
@ -1585,7 +1642,7 @@ READ32_DEVICE_HANDLER( ide_controller32_r )
offset *= 4;
size = convert_to_offset_and_size32(&offset, mem_mask);
return ide_controller_read(device, offset, size) << ((offset & 3) * 8);
return ide_controller_r(device, offset, size) << ((offset & 3) * 8);
}
@ -1595,11 +1652,43 @@ WRITE32_DEVICE_HANDLER( ide_controller32_w )
offset *= 4;
size = convert_to_offset_and_size32(&offset, mem_mask);
data = data >> ((offset & 3) * 8);
ide_controller_write(device, offset, size, data >> ((offset & 3) * 8));
ide_controller_w(device, offset, size, data);
}
READ32_DEVICE_HANDLER( ide_controller32_pcmcia_r )
{
int size;
UINT32 res = 0xffffffff;
offset *= 4;
size = convert_to_offset_and_size32(&offset, mem_mask);
if (offset >= 0x000 && offset < 0x008)
res = ide_controller_read(device, 0, offset & 7, size);
if (offset >= 0x008 && offset < 0x010)
res = ide_controller_read(device, 1, offset & 7, size);
return res << ((offset & 3) * 8);
}
WRITE32_DEVICE_HANDLER( ide_controller32_pcmcia_w )
{
int size;
offset *= 4;
size = convert_to_offset_and_size32(&offset, mem_mask);
data = data >> ((offset & 3) * 8);
if (offset >= 0x000 && offset < 0x008)
ide_controller_write(device, 0, offset & 7, size, data);
if (offset >= 0x008 && offset < 0x010)
ide_controller_write(device, 1, offset & 7, size, data);
}
READ32_DEVICE_HANDLER( ide_bus_master32_r )
{
int size;
@ -1633,10 +1722,10 @@ READ16_DEVICE_HANDLER( ide_controller16_r )
{
int size;
offset *= 2;
offset *= 4;
size = convert_to_offset_and_size16(&offset, mem_mask);
return ide_controller_read(device, offset, size) << ((offset & 1) * 8);
return ide_controller_r(device, offset, size) << ((offset & 1) * 8);
}
@ -1647,7 +1736,7 @@ WRITE16_DEVICE_HANDLER( ide_controller16_w )
offset *= 2;
size = convert_to_offset_and_size16(&offset, mem_mask);
ide_controller_write(device, offset, size, data >> ((offset & 1) * 8));
ide_controller_w(device, offset, size, data >> ((offset & 1) * 8));
}
@ -1678,7 +1767,8 @@ static DEVICE_START( ide_controller )
/* set MAME harddisk handle */
config = (const ide_config *)device->inline_config;
ide->disk = hard_disk_open(get_disk_handle((config->master != NULL) ? config->master : device->tag));
ide->handle = get_disk_handle((config->master != NULL) ? config->master : device->tag);
ide->disk = hard_disk_open(ide->handle);
assert_always(config->slave == NULL, "IDE controller does not yet support slave drives\n");
/* find the bus master space */

6
src/emu/machine/idectrl.h
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@ -66,11 +66,13 @@ void ide_set_user_password(const device_config *device, const UINT8 *password);
int ide_bus_r(const device_config *config, int select, int offset);
void ide_bus_w(const device_config *config, int select, int offset, int data);
int ide_controller_r(const device_config *config, int reg);
void ide_controller_w(const device_config *config, int reg, int data);
UINT32 ide_controller_r(const device_config *config, int reg, int size);
void ide_controller_w(const device_config *config, int reg, int size, UINT32 data);
READ32_DEVICE_HANDLER( ide_controller32_r );
WRITE32_DEVICE_HANDLER( ide_controller32_w );
READ32_DEVICE_HANDLER( ide_controller32_pcmcia_r );
WRITE32_DEVICE_HANDLER( ide_controller32_pcmcia_w );
READ32_DEVICE_HANDLER( ide_bus_master32_r );
WRITE32_DEVICE_HANDLER( ide_bus_master32_w );

1
src/emu/machine/intelfsh.c
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@ -98,6 +98,7 @@ void intelflash_init(running_machine *machine, int chip, int type, void *data)
c->device_id = 0xaa;
break;
case FLASH_SHARP_LH28F400:
case FLASH_INTEL_E28F400:
c->bits = 16;
c->size = 0x80000;
c->maker_id = 0xb0;

1
src/emu/machine/intelfsh.h
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@ -13,6 +13,7 @@
#define FLASH_INTEL_E28F008SA ( 3 )
#define FLASH_INTEL_TE28F160 ( 4 )
#define FLASH_SHARP_LH28F016S ( 5 )
#define FLASH_INTEL_E28F400 ( 6 )
extern void intelflash_init( running_machine *machine, int chip, int type, void *data );
extern UINT32 intelflash_read( int chip, UINT32 address );

834
src/mame/drivers/taitogn.c Normal file
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@ -0,0 +1,834 @@
/*
GNET Motherboard
Taito, 1998
The Taito GNET System comprises the following main parts....
- Sony ZN-2 Motherboard (Main CPU/GPU/SPU, RAM, BIOS, EEPROM & peripheral interfaces)
- Taito FC PCB (Sound hardware & FLASHROMs for storage of PCMCIA cart contents)
- Taito CD PCB (PCMCIA cart interface)
Also available are...
- Optional Communication Interface PCB
- Optional Save PCB
On power-up, the system checks for a PCMCIA cart. If the cart matches the contents of the flashROMs,
the game boots immediately with no delay. If the cart doesn't match, it re-flashes the flashROMs with _some_
of the information contained in the cart, which takes approximately 2-3 minutes. The game then resets
and boots up.
If no cart is present on power-up, the Taito GNET logo is displayed, then a message 'SYSTEM ERROR'
Since the logo is shown on boot even without a cart, there must be another sub-BIOS for the initial booting,
which I suspect is one of the flashROMs that is acting like a standard ROM and is not flashed at all.
Upon inspecting the GNET top board, it appears flash.u30 is the sub-BIOS and perhaps U27 is something sound related.
The flashROMs at U55, U56 & U29 appear to be the ones that are re-flashed when swapping game carts.
PCB Layouts
-----------
(Standard ZN2 Motherboard)
ZN-2 COH-3000 (sticker says COH-3002T denoting Taito GNET BIOS version)
|--------------------------------------------------------|
| LA4705 |---------------------------| |
| |---------------------------| |
| AKM_AK4310VM AT28C16 |
| VOL |
| S301 COH3002T.353 |
| |
| |
|J |
| |
|A 814260 CXD2925Q EPM7064 |
| |
|M 67.73MHz |
| |
|M |
| S551 KM4132G271BQ-8 |
|A |
| CXD8654Q CXD8661R |
| KM4132G271BQ-8 |
|CN505 CN506 53.693MHz 100MHz |
| CAT702 |
| |
|CN504 CN503 |
| |
| MC44200FT |
| NEC_78081G503 KM416V1204BT-L5 KM416V1204BT-L5 |
| |
|CN651 CN652 * * |
| CN654 |
|--------------------------------------------------------|
Notes:
CN506 - Connector for optional 3rd player controls
CN505 - Connector for optional 4th player controls
CN503 - Connector for optional 15kHz external video output (R,G,B,Sync, GND)
CN504 - Connector for optional 2nd speaker (for stereo output)
CN652 - Connector for optional trackball
CN651 - Connector for optional analog controls
CN654 - Connector for optional memory card
S301 - Slide switch for stereo or mono sound output
S551 - Dip switch (4 position, defaults all OFF)
COH3002T.353 - GNET BIOS 4MBit MaskROM type M534002 (SOP40)
AT28C16 - Atmel AT28C16 2K x8 EEPROM
814260-70 - 256K x16 (4MBit) DRAM
KM4132G271BQ-8 - 128K x 32Bit x 2 Banks SGRAM
KM416V1204BT-L5- 1M x16 EDO DRAM
EPM7064 - Altera EPM7064QC100 CPLD (QFP100)
CAT702 - Protection chip labelled 'TT10' (DIP20)
* - Unpopulated position for additional KM416V1204BT-L5 RAMs
FC PCB K91X0721B M43X0337B
|--------------------------------------------|
| |---------------------------| |
| |---------------------------| |
| NJM2100 NJM2100 |
| MB87078 |
| *MB3773 XC95108 DIP40 CAT702 |
| *ADM708AR |
| *UPD6379GR |
| FLASH.U30 |
| |
| DIP24 |
| *RF5C296 |
| -------CD-PCB------- _ |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | |-| |
| -------------------- |
| M66220FP FLASH.U55 FLASH16.U29|
| FLASH.U27 FLASH.U56 |
|*LC321664 |
| TMS57002DPHA *ZSG-2 |
| LH52B256 25MHz |
| MN1020012A |
|--------------------------------------------|
Notes:
DIP40 - Unpopulated socket for 8MBit DIP40 EPROM type AM27C800
DIP24 - Unpopulated position for FM1208 DIP24 IC
FLASH.U30 - Intel TE28F160 16MBit FLASHROM (TSOP56)
FLASH.U29/55/56 - Intel TE28F160 16MBit FLASHROM (TSOP56)
FLASH.U27 - Intel E28F400 4MBit FLASHROM (TSOP48)
LH52B256 - Sharp 32K x8 SRAM (SOP28)
LC321664 - Sanyo 64K x16 EDO DRAM (SOP40)
XC95108 - XILINX XC95108 CPLD labelled 'E65-01' (QFP100)
MN1020012A - Panasonic MN1020012A Sound CPU (QFP128)
ZSG-2 - Zoom Corp ZSG-2 Sound DSP (QFP100)
TMS57002DPHA - Texas Instruments TMS57002DPHA Sound DSP (QFP80)
RF5C296 - Ricoh RF5C296 PCMCIA controller (TQFP144)
M66220FP - 256 x8bit Mail-Box (Inter-MPU data transfer)
CAT702 - Protection chip labelled 'TT16' (DIP20)
CD PCB - A PCMCIA cart slot connector mounted onto a small daughterboard
* - These parts located under the PCB
*/
#include "driver.h"
#include "cpu/mips/psx.h"
#include "includes/psx.h"
#include "machine/at28c16.h"
#include "machine/intelfsh.h"
#include "machine/znsec.h"
#include "machine/idectrl.h"
#include "sound/psx.h"
static unsigned char cis[512];
static int locked;
// rf5c296 is very inaccurate at that point, it hardcodes the gnet config
static unsigned char rf5c296_reg = 0;
static void rf5c296_reg_w(ATTR_UNUSED running_machine *machine, UINT8 reg, UINT8 data)
{
// fprintf(stderr, "rf5c296_reg_w %02x, %02x (%s)\n", reg, data, cpuexec_describe_context(machine));
}
static UINT8 rf5c296_reg_r(ATTR_UNUSED running_machine *machine, UINT8 reg)
{
// fprintf(stderr, "rf5c296_reg_r %02x (%s)\n", reg, cpuexec_describe_context(machine));
return 0x00;
}
static WRITE32_HANDLER(rf5c296_io_w)
{
if(offset < 2) {
ide_controller32_pcmcia_w(devtag_get_device(space->machine, "card"), offset, data, mem_mask);
return;
}
if(offset == 0x3e0/4) {
if(ACCESSING_BITS_0_7)
rf5c296_reg = data;
if(ACCESSING_BITS_8_15)
rf5c296_reg_w(space->machine, rf5c296_reg, data >> 8);
}
}
static READ32_HANDLER(rf5c296_io_r)
{
if(offset < 2)
return ide_controller32_pcmcia_r(devtag_get_device(space->machine, "card"), offset, mem_mask);
offset *= 4;
if(offset == 0x3e0/4) {
UINT32 res = 0xffff0000;
if(ACCESSING_BITS_0_7)
res |= rf5c296_reg;
if(ACCESSING_BITS_8_15)
res |= rf5c296_reg_r(space->machine, rf5c296_reg) << 8;
return res;
}
return 0xffffffff;
}
// Hardcoded to reach the pcmcia CIS
static READ32_HANDLER(rf5c296_mem_r)
{
if(offset < 0x80)
return (cis[offset*2+1] << 16) | cis[offset*2];
switch(offset) {
case 0x080: return 0x00800041;
case 0x081: return 0x0000002e;
case 0x100: return locked ? 0x00010000 : 0;
default:
return 0;
}
}
static WRITE32_HANDLER(rf5c296_mem_w)
{
if(offset >= 0x140 && offset <= 0x144) {
UINT8 key[5];
int pos = (offset - 0x140)*2;
UINT8 v, k;
if(ACCESSING_BITS_16_23) {
v = data >> 16;
pos++;
} else
v = data;
chd_get_metadata(get_disk_handle("card"), HARD_DISK_KEY_METADATA_TAG, 0, key, 5, 0, 0, 0);
k = pos < 5 ? key[pos] : 0;
if(v == k)
locked &= ~(1 << pos);
else
locked |= 1 << pos;
}
}
// Flash handling
static UINT32 gen_flash_r(running_machine *machine, int chip, offs_t offset, UINT32 mem_mask)
{
UINT32 res = 0;
offset *= 2;
if(ACCESSING_BITS_0_15)
res |= intelflash_read(chip, offset);
if(ACCESSING_BITS_16_31)
res |= intelflash_read(chip, offset+1) << 16;
return res;
}
static void gen_flash_w(running_machine *machine, int chip, offs_t offset, UINT32 data, UINT32 mem_mask)
{
offset *= 2;
if(ACCESSING_BITS_0_15)
intelflash_write(chip, offset, data);
if(ACCESSING_BITS_16_31)
intelflash_write(chip, offset+1, data >> 16);
}
static READ32_HANDLER(flash_subbios_r)
{
return gen_flash_r(space->machine, 0, offset, mem_mask);
}
static WRITE32_HANDLER(flash_subbios_w)
{
gen_flash_w(space->machine, 0, offset, data, mem_mask);
}
static READ32_HANDLER(flash_mn102_r)
{
return gen_flash_r(space->machine, 1, offset, mem_mask);
}
static WRITE32_HANDLER(flash_mn102_w)
{
gen_flash_w(space->machine, 1, offset, data, mem_mask);
}
static READ32_HANDLER(flash_s1_r)
{
return gen_flash_r(space->machine, 2, offset, mem_mask);
}
static WRITE32_HANDLER(flash_s1_w)
{
gen_flash_w(space->machine, 2, offset, data, mem_mask);
}
static READ32_HANDLER(flash_s2_r)
{
return gen_flash_r(space->machine, 3, offset, mem_mask);
}
static WRITE32_HANDLER(flash_s2_w)
{
gen_flash_w(space->machine, 3, offset, data, mem_mask);
}
static READ32_HANDLER(flash_s3_r)
{
return gen_flash_r(space->machine, 4, offset, mem_mask);
}
static WRITE32_HANDLER(flash_s3_w)
{
gen_flash_w(space->machine, 4, offset, data, mem_mask);
}
static void install_handlers(running_machine *machine, int mode)
{
const address_space *a = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
if(mode == 0) {
// Mode 0 has access to the subbios, the mn102 flash and the rf5c296 mem zone
memory_install_readwrite32_handler(a, 0x1f000000, 0x1f1fffff, 0, 0, flash_subbios_r, flash_subbios_w);
memory_install_readwrite32_handler(a, 0x1f200000, 0x1f2fffff, 0, 0, rf5c296_mem_r, rf5c296_mem_w);
memory_install_readwrite32_handler(a, 0x1f300000, 0x1f37ffff, 0, 0, flash_mn102_r, flash_mn102_w);
memory_install_readwrite32_handler(a, 0x1f380000, 0x1f5fffff, 0, 0, SMH_NOP, SMH_NOP);
} else {
// Mode 1 has access to the 3 samples flashes
memory_install_readwrite32_handler(a, 0x1f000000, 0x1f1fffff, 0, 0, flash_s1_r, flash_s1_w);
memory_install_readwrite32_handler(a, 0x1f200000, 0x1f3fffff, 0, 0, flash_s2_r, flash_s2_w);
memory_install_readwrite32_handler(a, 0x1f400000, 0x1f5fffff, 0, 0, flash_s3_r, flash_s3_w);
}
}
// Misc. controls
static UINT32 control = 0, control2 = 0, control3;
static READ32_HANDLER(control_r)
{
// fprintf(stderr, "gn_r %08x @ %08x (%s)\n", 0x1fb00000+4*offset, mem_mask, cpuexec_describe_context(space->machine));
return control;
}
static WRITE32_HANDLER(control_w)
{
// 20 = watchdog
// 04 = select bank
// According to the rom code, bits 1-0 may be part of the bank
// selection too, but they're always 0.
UINT32 p = control;
COMBINE_DATA(&control);
#if 0
if((p ^ control) & ~0x20)
fprintf(stderr, "control = %c%c.%c %c%c%c%c (%s)\n",
control & 0x80 ? '1' : '0',
control & 0x40 ? '1' : '0',
control & 0x10 ? '1' : '0',
control & 0x08 ? '1' : '0',
control & 0x04 ? 'f' : '-',
control & 0x02 ? '1' : '0',
control & 0x01 ? '1' : '0',
cpuexec_describe_context(space->machine));
#endif
if((p ^ control) & 0x04)
install_handlers(space->machine, control & 4 ? 1 : 0);
}
static WRITE32_HANDLER(control2_w)
{
COMBINE_DATA(&control2);
}
static READ32_HANDLER(control3_r)
{
return control3;
}
static WRITE32_HANDLER(control3_w)
{
COMBINE_DATA(&control3);
// card reset, maybe
if(control3 & 2) {
devtag_reset(space->machine, "card");
locked = 0x1ff;
}
}
static READ32_HANDLER(gn_1fb70000_r)
{
// (1328) 1348 tests mask 0002, 8 times.
// Called by 1434, exit at 143c
// f -> 4/1
// end with 4x1 -> ok
// end with 4x0 -> configid error
// so returning 2 always works, strange.
return 2;
}
static WRITE32_HANDLER(gn_1fb70000_w)
{
// Writes 0 or 1 all the time, it *may* have somthing to do with
// i/o port width, but then maybe not
}
static READ32_HANDLER(hack1_r)
{
static int v = 0;
v = v ^ 8;
// Probably something to do with sound
return v;
}
// Lifted from zn.c
static const UINT8 tt10[ 8 ] = { 0x80, 0x20, 0x38, 0x08, 0xf1, 0x03, 0xfe, 0xfc };
static const UINT8 tt16[ 8 ] = { 0xc0, 0x04, 0xf9, 0xe1, 0x60, 0x70, 0xf2, 0x02 };
static UINT32 m_n_znsecsel;
static UINT32 m_b_znsecport;
static int m_n_dip_bit;
static int m_b_lastclock;
static emu_timer *dip_timer;
static READ32_HANDLER( znsecsel_r )
{
return m_n_znsecsel;
}
static void sio_znsec0_handler( running_machine *machine, int n_data )
{
if( ( n_data & PSX_SIO_OUT_CLOCK ) == 0 )
{
if( m_b_lastclock )
psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( znsec_step( 0, ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
m_b_lastclock = 0;
}
else
{
m_b_lastclock = 1;
}
}
static void sio_znsec1_handler( running_machine *machine, int n_data )
{
if( ( n_data & PSX_SIO_OUT_CLOCK ) == 0 )
{
if( m_b_lastclock )
psx_sio_input( machine, 0, PSX_SIO_IN_DATA, ( znsec_step( 1, ( n_data & PSX_SIO_OUT_DATA ) != 0 ) != 0 ) * PSX_SIO_IN_DATA );
m_b_lastclock = 0;
}
else
{
m_b_lastclock = 1;
}
}
static void sio_pad_handler( running_machine *machine, int n_data )
{
if( ( n_data & PSX_SIO_OUT_DTR ) != 0 )
{
m_b_znsecport = 1;
}
else
{
m_b_znsecport = 0;
}
psx_sio_input( machine, 0, PSX_SIO_IN_DATA | PSX_SIO_IN_DSR, PSX_SIO_IN_DATA | PSX_SIO_IN_DSR );
}
static void sio_dip_handler( running_machine *machine, int n_data )
{
if( ( n_data & PSX_SIO_OUT_CLOCK ) == 0 )
{
if( m_b_lastclock )
{
int bit = ( ( input_port_read(machine, "DSW") >> m_n_dip_bit ) & 1 );
psx_sio_input( machine, 0, PSX_SIO_IN_DATA, bit * PSX_SIO_IN_DATA );
m_n_dip_bit++;
m_n_dip_bit &= 7;
}
m_b_lastclock = 0;
}
else
{
m_b_lastclock = 1;
}
}
static WRITE32_HANDLER( znsecsel_w )
{
COMBINE_DATA( &m_n_znsecsel );
if( ( m_n_znsecsel & 0x80 ) == 0 )
{
psx_sio_install_handler( 0, sio_pad_handler );
psx_sio_input( space->machine, 0, PSX_SIO_IN_DSR, 0 );
}
else if( ( m_n_znsecsel & 0x08 ) == 0 )
{
znsec_start( 1 );
psx_sio_install_handler( 0, sio_znsec1_handler );
psx_sio_input( space->machine, 0, PSX_SIO_IN_DSR, 0 );
}
else if( ( m_n_znsecsel & 0x04 ) == 0 )
{
znsec_start( 0 );
psx_sio_install_handler( 0, sio_znsec0_handler );
psx_sio_input( space->machine, 0, PSX_SIO_IN_DSR, 0 );
}
else
{
m_n_dip_bit = 0;
m_b_lastclock = 1;
psx_sio_install_handler( 0, sio_dip_handler );
psx_sio_input( space->machine, 0, PSX_SIO_IN_DSR, 0 );
timer_adjust_oneshot( dip_timer, cpu_clocks_to_attotime( space->cpu, 100 ), 1 );
}
}
static TIMER_CALLBACK( dip_timer_fired )
{
psx_sio_input( machine, 0, PSX_SIO_IN_DSR, param * PSX_SIO_IN_DSR );
if( param )
{
timer_adjust_oneshot( dip_timer, cpu_clocks_to_attotime( machine->cpu[0], 50 ), 0 );
}
}
static READ32_HANDLER( boardconfig_r )
{
/*
------00 mem=4M
------01 mem=4M
------10 mem=8M
------11 mem=16M
-----0-- smem=hM
-----1-- smem=2M
----0--- vmem=1M
----1--- vmem=2M
000----- rev=-2
001----- rev=-1
010----- rev=0
011----- rev=1
100----- rev=2
101----- rev=3
110----- rev=4
111----- rev=5
*/
return 64|32|8;
}
static UINT32 coin_info;
static WRITE32_HANDLER( coin_w )
{
/* 0x01=counter
0x02=coin lock 1
0x08=??
0x20=coin lock 2
0x80=??
*/
COMBINE_DATA (&coin_info);
}
static READ32_HANDLER( coin_r )
{
return coin_info;
}
// Init and reset
static NVRAM_HANDLER( coh3002t )
{
nvram_handler_intelflash(machine, 0, file, read_or_write);
nvram_handler_intelflash(machine, 1, file, read_or_write);
nvram_handler_intelflash(machine, 2, file, read_or_write);
nvram_handler_intelflash(machine, 3, file, read_or_write);
nvram_handler_intelflash(machine, 4, file, read_or_write);
if(!file) {
// Only the subbios needs to preexist for the board to work
// Of the subbios flash, only the range 000000-04ffff is the
// actual subbios, rest is flashed from the game
memcpy(intelflash_getmemptr(0), memory_region(machine, "subbios"), 0x200000);
memset((char *)intelflash_getmemptr(0)+0x50000, 0xff, 0x200000-0x50000);
}
}
static DRIVER_INIT( coh3002t )
{
// Sub-bios (u30)
intelflash_init(machine, 0, FLASH_INTEL_TE28F160, 0);
// mn102 program flash (u27)
intelflash_init(machine, 1, FLASH_INTEL_E28F400, 0);
// Samples (u29, u55, u56)
intelflash_init(machine, 2, FLASH_INTEL_TE28F160, 0);
intelflash_init(machine, 3, FLASH_INTEL_TE28F160, 0);
intelflash_init(machine, 4, FLASH_INTEL_TE28F160, 0);
psx_driver_init(machine);
znsec_init(0, tt10);
znsec_init(1, tt16);
psx_sio_install_handler(0, sio_pad_handler);
dip_timer = timer_alloc(machine, dip_timer_fired, NULL );
memset(cis, 0xff, 512);
chd_get_metadata(get_disk_handle("card"), PCMCIA_CIS_METADATA_TAG, 0, cis, 512, 0, 0, 0);
}
static MACHINE_RESET( coh3002t )
{
m_b_lastclock = 1;
locked = 0x1ff;
install_handlers(machine, 0);
control = 0;
psx_machine_init(machine);
devtag_reset(machine, "card");
}
static ADDRESS_MAP_START( zn_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_SHARE(1) AM_BASE(&g_p_n_psxram) AM_SIZE(&g_n_psxramsize) /*
ram */
AM_RANGE(0x00400000, 0x007fffff) AM_RAM AM_SHARE(1) /* ram mirror */
AM_RANGE(0x1f000000, 0x1f1fffff) AM_READWRITE(flash_s1_r, flash_s1_w)
AM_RANGE(0x1f200000, 0x1f3fffff) AM_READWRITE(flash_s2_r, flash_s2_w)
AM_RANGE(0x1f400000, 0x1f5fffff) AM_READWRITE(flash_s3_r, flash_s3_w)
AM_RANGE(0x1f800000, 0x1f8003ff) AM_RAM /* scratchpad */
AM_RANGE(0x1f801000, 0x1f80100f) AM_RAM /* ?? */
AM_RANGE(0x1f801014, 0x1f801017) AM_DEVREADWRITE("spu", psx_spu_delay_r, psx_spu_delay_w)
AM_RANGE(0x1f801020, 0x1f801023) AM_READWRITE(psx_com_delay_r, psx_com_delay_w)
AM_RANGE(0x1f801040, 0x1f80105f) AM_READWRITE(psx_sio_r, psx_sio_w)
AM_RANGE(0x1f801070, 0x1f801077) AM_READWRITE(psx_irq_r, psx_irq_w)
AM_RANGE(0x1f801080, 0x1f8010ff) AM_READWRITE(psx_dma_r, psx_dma_w)
AM_RANGE(0x1f801100, 0x1f80112f) AM_READWRITE(psx_counter_r, psx_counter_w)
AM_RANGE(0x1f801810, 0x1f801817) AM_READWRITE(psx_gpu_r, psx_gpu_w)
AM_RANGE(0x1f801820, 0x1f801827) AM_READWRITE(psx_mdec_r, psx_mdec_w)
AM_RANGE(0x1f801c00, 0x1f801dff) AM_DEVREADWRITE("spu", psx_spu_r, psx_spu_w)
AM_RANGE(0x1fa00000, 0x1fa00003) AM_READ_PORT("P1")
AM_RANGE(0x1fa00100, 0x1fa00103) AM_READ_PORT("P2")
AM_RANGE(0x1fa00200, 0x1fa00203) AM_READ_PORT("SERVICE")
AM_RANGE(0x1fa00300, 0x1fa00303) AM_READ_PORT("SYSTEM")
AM_RANGE(0x1fa10000, 0x1fa10003) AM_READ_PORT("P3")
AM_RANGE(0x1fa10100, 0x1fa10103) AM_READ_PORT("P4")
AM_RANGE(0x1fa10200, 0x1fa10203) AM_READ(boardconfig_r)
AM_RANGE(0x1fa10300, 0x1fa10303) AM_READWRITE(znsecsel_r, znsecsel_w)
AM_RANGE(0x1fa20000, 0x1fa20003) AM_READWRITE(coin_r, coin_w)
AM_RANGE(0x1fa30000, 0x1fa30003) AM_READWRITE(control3_r, control3_w)
AM_RANGE(0x1fa51c00, 0x1fa51dff) AM_DEVREADWRITE("spu", psx_spu_r, psx_spu_w) // systematic read at spu_address + 250000, result dropped, maybe other accesses
AM_RANGE(0x1fa60000, 0x1fa60003) AM_READ(hack1_r)
AM_RANGE(0x1faf0000, 0x1faf07ff) AM_DEVREADWRITE8("at28c16", at28c16_r, at28c16_w, 0xffffffff) /* eeprom */
AM_RANGE(0x1fb00000, 0x1fb0ffff) AM_READWRITE(rf5c296_io_r, rf5c296_io_w)
AM_RANGE(0x1fb40000, 0x1fb40003) AM_READWRITE(control_r, control_w)
AM_RANGE(0x1fb60000, 0x1fb60003) AM_WRITE(control2_w)
AM_RANGE(0x1fb70000, 0x1fb70003) AM_READWRITE(gn_1fb70000_r, gn_1fb70000_w)
AM_RANGE(0x1fbe0000, 0x1fbe01ff) AM_RAM // 256 bytes com zone with the mn102, low bytes of words only, with additional comm at 1fb80000
AM_RANGE(0x1fc00000, 0x1fc7ffff) AM_ROM AM_SHARE(2) AM_REGION("mainbios", 0) /* bios */
AM_RANGE(0x80000000, 0x803fffff) AM_RAM AM_SHARE(1) /* ram mirror */
AM_RANGE(0x80400000, 0x807fffff) AM_RAM AM_SHARE(1) /* ram mirror */
AM_RANGE(0x9fc00000, 0x9fc7ffff) AM_ROM AM_SHARE(2) /* bios mirror */
AM_RANGE(0xa0000000, 0xa03fffff) AM_RAM AM_SHARE(1) /* ram mirror */
AM_RANGE(0xbfc00000, 0xbfc7ffff) AM_WRITENOP AM_ROM AM_SHARE(2) /* bios mirror */
AM_RANGE(0xfffe0130, 0xfffe0133) AM_WRITENOP
ADDRESS_MAP_END
static void psx_spu_irq(const device_config *device, UINT32 data)
{
psx_irq_set(device->machine, data);
}
static const psx_spu_interface psxspu_interface =
{
&g_p_n_psxram,
psx_spu_irq,
psx_dma_install_read_handler,
psx_dma_install_write_handler
};
static MACHINE_DRIVER_START( coh3002t )
/* basic machine hardware */
MDRV_CPU_ADD( "maincpu", PSXCPU, XTAL_100MHz )
MDRV_CPU_PROGRAM_MAP( zn_map, 0 )
MDRV_CPU_VBLANK_INT("screen", psx_vblank)
/* video hardware */
MDRV_SCREEN_ADD("screen", RASTER)
MDRV_SCREEN_REFRESH_RATE( 60 )
MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
MDRV_SCREEN_SIZE( 1024, 1024 )
MDRV_SCREEN_VISIBLE_AREA( 0, 639, 0, 479 )
MDRV_PALETTE_LENGTH( 65536 )
MDRV_PALETTE_INIT( psx )
MDRV_VIDEO_START( psx_type2 )
MDRV_VIDEO_UPDATE( psx )
/* sound hardware */
MDRV_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MDRV_SOUND_ADD( "spu", PSXSPU, 0 )
MDRV_SOUND_CONFIG( psxspu_interface )
MDRV_SOUND_ROUTE(0, "lspeaker", 0.35)
MDRV_SOUND_ROUTE(1, "rspeaker", 0.35)
MDRV_MACHINE_RESET( coh3002t )
MDRV_AT28C16_ADD( "at28c16", 0 )
MDRV_IDE_CONTROLLER_ADD( "card", 0 )
MDRV_NVRAM_HANDLER( coh3002t )
MACHINE_DRIVER_END
static INPUT_PORTS_START( coh3002t )
PORT_START("P1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("P2")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("SERVICE")
PORT_SERVICE_NO_TOGGLE( 0x01, IP_ACTIVE_LOW )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("SYSTEM")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START4 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN3 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN4 )
PORT_START("P3")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("P4")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("DSW")
PORT_DIPNAME( 0x01, 0x01, "Freeze" )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Service_Mode ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
// ROM_LOAD( "flashv2.u30", 0x000000, 0x200000, CRC(f624ebf8) SHA1(be84ef1b083f819f3ab13c983c52bca97bb908ef) )
#define TAITOGNET_BIOS \
ROM_REGION32_LE( 0x080000, "mainbios", 0 ) \
ROM_LOAD( "coh-3002t.353", 0x0000000, 0x080000, CRC(03967fa7) SHA1(0e17fec2286e4e25deb23d40e41ce0986f373d49) ) \
\
ROM_REGION32_LE( 0x0200000, "subbios", 0 ) \
ROM_LOAD( "flash.u30", 0x000000, 0x200000, CRC(2d6740fc) SHA1(9a17411c1bd07b714227e84de23976ec900bdeed) ) \
ROM_REGION32_LE( 0x80000, "soundcpu", 0) \
ROM_FILL( 0, 0x80000, 0xff) \
ROM_REGION32_LE( 0x600000, "samples", 0) \
ROM_FILL( 0, 0x600000, 0xff)
ROM_START( taitogn )
TAITOGNET_BIOS
ROM_END
ROM_START(spuzbobl)
TAITOGNET_BIOS
DISK_REGION( "card" )
DISK_IMAGE( "spuzbobl", 0, SHA1(ed9d621cffa313813d7b45b0228bc15514fe7e36))
ROM_END
ROM_START(chaoshea)
TAITOGNET_BIOS
DISK_REGION( "card" )
DISK_IMAGE( "chaoshea", 0, SHA1(5b43c3597808792c3084367ed6bc3bf4bb8bc99e))
ROM_END
/* A dummy driver, so that the bios can be debugged, and to serve as */
/* parent for the coh-3002t.353 file, so that we do not have to include */
/* it in every zip file */
GAME( 1997, taitogn, 0, coh3002t, coh3002t, coh3002t, ROT0, "Sony/Taito", "Taito GNET", GAME_IS_BIOS_ROOT )
GAME( 1998, chaoshea, taitogn, coh3002t, coh3002t, coh3002t, ROT0, "Taito", "Chaos Heat", 0 )
GAME( 1999, spuzbobl, taitogn, coh3002t, coh3002t, coh3002t, ROT0, "Taito", "Super Puzzle Bobble", 0 )

200
src/mame/drivers/zn.c
View File

@ -1305,169 +1305,6 @@ MACHINE_DRIVER_END
/*
GNET Motherboard
Taito, 1998
The Taito GNET System comprises the following main parts....
- Sony ZN-2 Motherboard (Main CPU/GPU/SPU, RAM, BIOS, EEPROM & peripheral interfaces)
- Taito FC PCB (Sound hardware & FLASHROMs for storage of PCMCIA cart contents)
- Taito CD PCB (PCMCIA cart interface)
Also available are...
- Optional Communication Interface PCB
- Optional Save PCB
On power-up, the system checks for a PCMCIA cart. If the cart matches the contents of the flashROMs,
the game boots immediately with no delay. If the cart doesn't match, it re-flashes the flashROMs with _some_
of the information contained in the cart, which takes approximately 2-3 minutes. The game then resets
and boots up.
If no cart is present on power-up, the Taito GNET logo is displayed, then a message 'SYSTEM ERROR'
Since the logo is shown on boot even without a cart, there must be another sub-BIOS for the initial booting,
which I suspect is one of the flashROMs that is acting like a standard ROM and is not flashed at all.
Upon inspecting the GNET top board, it appears flash.u30 is the sub-BIOS and perhaps U27 is something sound related.
The flashROMs at U55, U56 & U29 appear to be the ones that are re-flashed when swapping game carts.
PCB Layouts
-----------
(Standard ZN2 Motherboard)
ZN-2 COH-3000 (sticker says COH-3002T denoting Taito GNET BIOS version)
|--------------------------------------------------------|
| LA4705 |---------------------------| |
| |---------------------------| |
| AKM_AK4310VM AT28C16 |
| VOL |
| S301 COH3002T.353 |
| |
| |
|J |
| |
|A 814260 CXD2925Q EPM7064 |
| |
|M 67.73MHz |
| |
|M |
| S551 KM4132G271BQ-8 |
|A |
| CXD8654Q CXD8661R |
| KM4132G271BQ-8 |
|CN505 CN506 53.693MHz 100MHz |
| CAT702 |
| |
|CN504 CN503 |
| |
| MC44200FT |
| NEC_78081G503 KM416V1204BT-L5 KM416V1204BT-L5 |
| |
|CN651 CN652 * * |
| CN654 |
|--------------------------------------------------------|
Notes:
CN506 - Connector for optional 3rd player controls
CN505 - Connector for optional 4th player controls
CN503 - Connector for optional 15kHz external video output (R,G,B,Sync, GND)
CN504 - Connector for optional 2nd speaker (for stereo output)
CN652 - Connector for optional trackball
CN651 - Connector for optional analog controls
CN654 - Connector for optional memory card
S301 - Slide switch for stereo or mono sound output
S551 - Dip switch (4 position, defaults all OFF)
COH3002T.353 - GNET BIOS 4MBit MaskROM type M534002 (SOP40)
AT28C16 - Atmel AT28C16 2K x8 EEPROM
814260-70 - 256K x16 (4MBit) DRAM
KM4132G271BQ-8 - 128K x 32Bit x 2 Banks SGRAM
KM416V1204BT-L5- 1M x16 EDO DRAM
EPM7064 - Altera EPM7064QC100 CPLD (QFP100)
CAT702 - Protection chip labelled 'TT10' (DIP20)
* - Unpopulated position for additional KM416V1204BT-L5 RAMs
FC PCB K91X0721B M43X0337B
|--------------------------------------------|
| |---------------------------| |
| |---------------------------| |
| NJM2100 NJM2100 |
| MB87078 |
| *MB3773 XC95108 DIP40 CAT702 |
| *ADM708AR |
| *UPD6379GR |
| FLASH.U30 |
| |
| DIP24 |
| *RF5C296 |
| -------CD-PCB------- _ |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | |-| |
| -------------------- |
| M66220FP FLASH.U55 FLASH16.U29|
| FLASH.U27 FLASH.U56 |
|*LC321664 |
| TMS57002DPHA *ZSG-2 |
| LH52B256 25MHz |
| MN1020012A |
|--------------------------------------------|
Notes:
DIP40 - Unpopulated socket for 8MBit DIP40 EPROM type AM27C800
DIP24 - Unpopulated position for FM1208 DIP24 IC
FLASH.U30 - Intel TE28F160 16MBit FLASHROM (TSOP56)
FLASH.U29/55/56 - Intel TE28F160 16MBit FLASHROM (TSOP56)
FLASH.U27 - Intel E28F400 4MBit FLASHROM (TSOP48)
LH52B256 - Sharp 32K x8 SRAM (SOP28)
LC321664 - Sanyo 64K x16 EDO DRAM (SOP40)
XC95108 - XILINX XC95108 CPLD labelled 'E65-01' (QFP100)
MN1020012A - Panasonic MN1020012A Sound CPU (QFP128)
ZSG-2 - Zoom Corp ZSG-2 Sound DSP (QFP100)
TMS57002DPHA - Texas Instruments TMS57002DPHA Sound DSP (QFP80)
RF5C296 - Ricoh RF5C296 PCMCIA controller (TQFP144)
M66220FP - 256 x8bit Mail-Box (Inter-MPU data transfer)
CAT702 - Protection chip labelled 'TT16' (DIP20)
CD PCB - A PCMCIA cart slot connector mounted onto a small daughterboard
* - These parts located under the PCB
*/
static UINT32 coh3002t_unknown;
static WRITE32_HANDLER( coh3002t_unknown_w )
{
COMBINE_DATA( &coh3002t_unknown );
}
static READ32_HANDLER( coh3002t_unknown_r )
{
return coh3002t_unknown;
}
static DRIVER_INIT( coh3002t )
{
memory_install_read32_handler ( cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x1f000000, 0x1f1fffff, 0, 0, SMH_BANK1 );
memory_install_readwrite32_handler( cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x1fb40000, 0x1fb40003, 0, 0, coh3002t_unknown_r, coh3002t_unknown_w );
zn_driver_init(machine);
}
static MACHINE_RESET( coh3002t )
{
memory_set_bankptr(machine, 1, memory_region( machine, "user2" ) ); /* GNET boot rom */
zn_machine_init(machine);
}
static MACHINE_DRIVER_START( coh3002t )
MDRV_IMPORT_FROM( zn2 )
MDRV_MACHINE_RESET( coh3002t )
MACHINE_DRIVER_END
/*
Primal Rage 2
Atari, 1996
@ -2159,7 +1996,7 @@ static void jdredd_ide_interrupt(const device_config *device, int state)
static READ32_DEVICE_HANDLER( jdredd_idestat_r )
{
return ide_controller_r( device, 0x1f7 );
return ide_controller_r( device, 0x1f7, 1 );
}
static READ32_DEVICE_HANDLER( jdredd_ide_r )
@ -2168,19 +2005,19 @@ static READ32_DEVICE_HANDLER( jdredd_ide_r )
if( ACCESSING_BITS_0_7 )
{
data |= ide_controller_r( device, 0x1f0 + ( offset * 2 ) ) << 0;
data |= ide_controller_r( device, 0x1f0 + ( offset * 2 ), 1 ) << 0;
}
if( ACCESSING_BITS_8_15 )
{
data |= ide_controller_r( device, 0x1f0 + ( offset * 2 ) ) << 8;
data |= ide_controller_r( device, 0x1f0 + ( offset * 2 ), 1 ) << 8;
}
if( ACCESSING_BITS_16_23 )
{
data |= ide_controller_r( device, 0x1f1 + ( offset * 2 ) ) << 16;
data |= ide_controller_r( device, 0x1f1 + ( offset * 2 ), 1 ) << 16;
}
if( ACCESSING_BITS_24_31 )
{
data |= ide_controller_r( device, 0x1f1 + ( offset * 2 ) ) << 24;
data |= ide_controller_r( device, 0x1f1 + ( offset * 2 ), 1 ) << 24;
}
return data;
@ -2190,19 +2027,19 @@ static WRITE32_DEVICE_HANDLER( jdredd_ide_w )
{
if( ACCESSING_BITS_0_7 )
{
ide_controller_w( device, 0x1f0 + ( offset * 2 ), data >> 0 );
ide_controller_w( device, 0x1f0 + ( offset * 2 ), 1, data >> 0 );
}
if( ACCESSING_BITS_8_15 )
{
ide_controller_w( device, 0x1f0 + ( offset * 2 ), data >> 8 );
ide_controller_w( device, 0x1f0 + ( offset * 2 ), 1, data >> 8 );
}
if( ACCESSING_BITS_16_23 )
{
ide_controller_w( device, 0x1f1 + ( offset * 2 ), data >> 16 );
ide_controller_w( device, 0x1f1 + ( offset * 2 ), 1, data >> 16 );
}
if( ACCESSING_BITS_24_31 )
{
ide_controller_w( device, 0x1f1 + ( offset * 2 ), data >> 24 );
ide_controller_w( device, 0x1f1 + ( offset * 2 ), 1, data >> 24 );
}
}
@ -4172,20 +4009,6 @@ ROM_START( sfchampj )
ROM_LOAD( "e18-01.15", 0x0000000, 0x200000, CRC(dbd1408c) SHA1(ef81064f2f95e5ae25eb1f10d1e78f27f9e294f5) )
ROM_END
#define TAITOGNET_BIOS \
ROM_REGION32_LE( 0x080000, "user1", 0 ) \
ROM_LOAD( "coh-3002t.353", 0x0000000, 0x080000, CRC(03967fa7) SHA1(0e17fec2286e4e25deb23d40e41ce0986f373d49) ) \
\
ROM_REGION32_LE( 0x0200000, "user2", 0 ) \
ROM_LOAD( "flash.u30", 0x000000, 0x200000, CRC(2d6740fc) SHA1(9a17411c1bd07b714227e84de23976ec900bdeed) ) \
\
ROM_REGION( 0x080000, "link", 0 ) \
ROM_LOAD( "flash.u27", 0x000000, 0x080000, CRC(75bd9c51) SHA1(e1eeab509faedb1ed815551fcc63a5a41e1cfdf0) ) \
ROM_START( taitogn )
TAITOGNET_BIOS
ROM_END
/* Eighteen Raizing */
#define PSARC95_BIOS \
@ -4532,11 +4355,6 @@ GAME( 1997, gdarius, gdarius2, coh1000tb,zn, coh1000tb, ROT0, "Taito", "G-Dariu
GAME( 1997, gdariusb, gdarius2, coh1000tb,zn, coh1000tb, ROT0, "Taito", "G-Darius (Ver 2.02A)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND )
GAME( 1997, gdarius2, taitofx1, coh1000tb,zn, coh1000tb, ROT0, "Taito", "G-Darius Ver.2 (Ver 2.03J)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND )
/* A dummy driver, so that the bios can be debugged, and to serve as */
/* parent for the coh-3002t.353 file, so that we do not have to include */
/* it in every zip file */
GAME( 1997, taitogn, 0, coh3002t, zn, coh3002t, ROT0, "Sony/Taito", "Taito GNET", GAME_IS_BIOS_ROOT )
/* Eighting/Raizing */
/* A dummy driver, so that the bios can be debugged, and to serve as */

1
src/mame/mame.mak
View File

@ -598,6 +598,7 @@ $(MAMEOBJ)/capcom.a: \
$(DRIVERS)/vulgus.o $(VIDEO)/vulgus.o \
$(DRIVERS)/tigeroad.o $(VIDEO)/tigeroad.o \
$(DRIVERS)/zn.o $(MACHINE)/znsec.o \
$(DRIVERS)/taitogn.o \
$(MACHINE)/cps2crpt.o \
$(MACHINE)/kabuki.o \

2
src/mame/mamedriv.c
View File

@ -2952,6 +2952,8 @@ V-V TP-027
/* Taito GNET */
DRIVER( taitogn )
DRIVER( spuzbobl )
DRIVER( chaoshea )
/* Namco System 11 */
DRIVER( tekken ) /* Tekken (TE4/VER.C) */