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h8 updates: [R. Belmont]

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- Preliminary H8S/2655 support
- Fixed so RTE doesn't allow the PC to go outside the address space
- Supported additional forms of BTST and BSET
- Removed incorrect halt on BVC/BVS instructions
This commit is contained in:
R. Belmont 2012-11-28 04:27:10 +00:00
parent e48b274801
commit d98bbeb929
6 changed files with 189 additions and 53 deletions
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22
src/emu/cpu/h83002/h8.h
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@ -1,13 +1,14 @@
/*************************************************************************** /***************************************************************************
h83002.h : Public constants and function defs for the H8/3002 emulator. h8.h : Public constants and function defs for the H8/300, H8/300H,
H8/2000S, and H8/2600S family emulators.
****************************************************************************/ ****************************************************************************/
#pragma once #pragma once
#ifndef __H83002_H__ #ifndef __H8SERIES_H__
#define __H83002_H__ #define __H8SERIES_H__
#define IFLAG 0x80 #define IFLAG 0x80
@ -121,6 +122,9 @@ enum
#define H8S_IO_ICRB H8S_IO(0xFEC1) #define H8S_IO_ICRB H8S_IO(0xFEC1)
#define H8S_IO_ICRC H8S_IO(0xFEC2) #define H8S_IO_ICRC H8S_IO(0xFEC2)
#define H8S_IO_ISCRH H8S_IO(0xFF2C)
#define H8S_IO_ISCRL H8S_IO(0xFF2D)
// for H8S/2394 // for H8S/2394
#define H8S_IO_IER H8S_IO(0xFF2E) #define H8S_IO_IER H8S_IO(0xFF2E)
#define H8S_IO_IFR H8S_IO(0xFF2F) #define H8S_IO_IFR H8S_IO(0xFF2F)
@ -133,6 +137,8 @@ enum
#define H8S_IO_DTCEE H8S_IO(0xFF34) #define H8S_IO_DTCEE H8S_IO(0xFF34)
#define H8S_IO_DTCEF H8S_IO(0xFF35) #define H8S_IO_DTCEF H8S_IO(0xFF35)
#define H8S_IO_SYSCR H8S_IO(0xFF39)
// port read registers // port read registers
#define H8S_IO_PORT1 H8S_IO(0xFF50) #define H8S_IO_PORT1 H8S_IO(0xFF50)
#define H8S_IO_PORT2 H8S_IO(0xFF51) #define H8S_IO_PORT2 H8S_IO(0xFF51)
@ -185,6 +191,11 @@ enum
#define H8S_IO_SSR2 H8S_IO(0xFF8C) #define H8S_IO_SSR2 H8S_IO(0xFF8C)
#define H8S_IO_RDR2 H8S_IO(0xFF8D) #define H8S_IO_RDR2 H8S_IO(0xFF8D)
#define H8S_IO_SCMR2 H8S_IO(0xFF8E) #define H8S_IO_SCMR2 H8S_IO(0xFF8E)
// ADC
#define H8S_IO_ADCSR H8S_IO(0xFFA0)
#define H8S_IO_ADCR H8S_IO(0xFFA1)
// 8-bit timer (channel 0 & 1) // 8-bit timer (channel 0 & 1)
#define H8S_IO_TCR0 H8S_IO(0xFFB0) #define H8S_IO_TCR0 H8S_IO(0xFFB0)
#define H8S_IO_TCR1 H8S_IO(0xFFB1) #define H8S_IO_TCR1 H8S_IO(0xFFB1)
@ -295,6 +306,8 @@ enum
#define H8S_IO_DMABCRH H8S_IO(0xFF06) #define H8S_IO_DMABCRH H8S_IO(0xFF06)
#define H8S_IO_DMABCRL H8S_IO(0xFF07) #define H8S_IO_DMABCRL H8S_IO(0xFF07)
#define H8S_IO_ADCSR H8S_IO(0xFFA0)
/////////// ///////////
// PORTS // // PORTS //
/////////// ///////////
@ -417,5 +430,6 @@ DECLARE_LEGACY_CPU_DEVICE(H8S2241, h8s_2241);
DECLARE_LEGACY_CPU_DEVICE(H8S2246, h8s_2246); DECLARE_LEGACY_CPU_DEVICE(H8S2246, h8s_2246);
DECLARE_LEGACY_CPU_DEVICE(H8S2323, h8s_2323); DECLARE_LEGACY_CPU_DEVICE(H8S2323, h8s_2323);
DECLARE_LEGACY_CPU_DEVICE(H8S2394, h8s_2394); DECLARE_LEGACY_CPU_DEVICE(H8S2394, h8s_2394);
DECLARE_LEGACY_CPU_DEVICE(H8S2655, h8s_2655);
#endif /* __H83002_H__ */ #endif /* __H8SERIES_H__ */

55
src/emu/cpu/h83002/h8_16.c
View File

@ -723,6 +723,23 @@ static WRITE16_HANDLER( h8s2394_per_regs_w )
} }
} }
static WRITE16_HANDLER( h8s2655_per_regs_w )
{
h83xx_state *h8 = get_safe_token(&space.device());
if (mem_mask == 0xffff)
{
h8s2655_per_regs_write_16(h8, (offset << 1), data);
}
else if (mem_mask & 0xff00)
{
h8s2655_per_regs_write_8(h8, (offset << 1), (data >> 8) & 0xff);
}
else if (mem_mask == 0x00ff)
{
h8s2655_per_regs_write_8(h8, (offset << 1) + 1, data & 0xff);
}
}
static READ16_HANDLER( h8s2241_per_regs_r ) static READ16_HANDLER( h8s2241_per_regs_r )
{ {
h83xx_state *h8 = get_safe_token(&space.device()); h83xx_state *h8 = get_safe_token(&space.device());
@ -795,6 +812,24 @@ static READ16_HANDLER( h8s2394_per_regs_r )
return 0; return 0;
} }
static READ16_HANDLER( h8s2655_per_regs_r )
{
h83xx_state *h8 = get_safe_token(&space.device());
if (mem_mask == 0xffff)
{
return h8s2655_per_regs_read_16(h8, (offset << 1));
}
else if (mem_mask == 0xff00)
{
return h8s2655_per_regs_read_8(h8, (offset << 1)) << 8;
}
else if (mem_mask == 0x00ff)
{
return h8s2655_per_regs_read_8(h8, (offset << 1) + 1);
}
return 0;
}
// On-board RAM and peripherals // On-board RAM and peripherals
static ADDRESS_MAP_START( h8_3002_internal_map, AS_PROGRAM, 16, legacy_cpu_device ) static ADDRESS_MAP_START( h8_3002_internal_map, AS_PROGRAM, 16, legacy_cpu_device )
// 512B RAM // 512B RAM
@ -835,6 +870,11 @@ static ADDRESS_MAP_START( h8s_2394_internal_map, AS_PROGRAM, 16, legacy_cpu_devi
AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE_LEGACY( h8s2394_per_regs_r, h8s2394_per_regs_w ) // internal i/o registers AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE_LEGACY( h8s2394_per_regs_r, h8s2394_per_regs_w ) // internal i/o registers
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( h8s_2655_internal_map, AS_PROGRAM, 16, legacy_cpu_device )
AM_RANGE( 0xFFEC00, 0xFFFBFF ) AM_RAM // on-chip ram
AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE_LEGACY( h8s2655_per_regs_r, h8s2655_per_regs_w ) // internal i/o registers
ADDRESS_MAP_END
CPU_GET_INFO( h8_3002 ) CPU_GET_INFO( h8_3002 )
{ {
h83xx_state *h8 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; h83xx_state *h8 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
@ -989,6 +1029,20 @@ CPU_GET_INFO( h8s_2394 )
} }
} }
CPU_GET_INFO( h8s_2655 )
{
switch (state)
{
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8s_2655_internal_map); break;
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8s_2394); break;
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break;
case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break;
case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2655"); break;
default:
CPU_GET_INFO_CALL(h8_3002);
}
}
DEFINE_LEGACY_CPU_DEVICE(H83002, h8_3002); DEFINE_LEGACY_CPU_DEVICE(H83002, h8_3002);
DEFINE_LEGACY_CPU_DEVICE(H83007, h8_3007); DEFINE_LEGACY_CPU_DEVICE(H83007, h8_3007);
DEFINE_LEGACY_CPU_DEVICE(H83044, h8_3044); DEFINE_LEGACY_CPU_DEVICE(H83044, h8_3044);
@ -997,4 +1051,5 @@ DEFINE_LEGACY_CPU_DEVICE(H8S2241, h8s_2241);
DEFINE_LEGACY_CPU_DEVICE(H8S2246, h8s_2246); DEFINE_LEGACY_CPU_DEVICE(H8S2246, h8s_2246);
DEFINE_LEGACY_CPU_DEVICE(H8S2323, h8s_2323); DEFINE_LEGACY_CPU_DEVICE(H8S2323, h8s_2323);
DEFINE_LEGACY_CPU_DEVICE(H8S2394, h8s_2394); DEFINE_LEGACY_CPU_DEVICE(H8S2394, h8s_2394);
DEFINE_LEGACY_CPU_DEVICE(H8S2655, h8s_2655);

29
src/emu/cpu/h83002/h8disasm.c
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@ -1275,6 +1275,35 @@ static UINT32 h8disasm_6(UINT32 address, UINT32 opcode, char *buffer, const UINT
sprintf(buffer, "%4.4x mov.b @%x, %s", opcode, data16, reg_names8[opcode & 0xf]); sprintf(buffer, "%4.4x mov.b @%x, %s", opcode, data16, reg_names8[opcode & 0xf]);
size = 4; size = 4;
break; break;
case 0x1:
data32=h8_mem_read16(2);
if (data32 & 0x8000)
{
data32 |= 0xffff0000;
}
data16=h8_mem_read16(4);
if ((data16 & 0xff00) == 0x7300)
{
sprintf(buffer, "%4.4x btst #%d, @%8.8x", opcode, (data16 >> 4) & 7, data32 & addr_mask);
}
else if ((data16 & 0xff0f) == 0x7000)
{
sprintf(buffer, "%4.4x bset #%d, @%8.8x", opcode, (data16 >> 4) & 7, data32 & addr_mask);
}
else if ((data16 & 0xff00) == 0x6300)
{
sprintf(buffer, "%4.4x btst %s, @%8.8x", opcode, reg_names8[(data16 >> 4) & 0xf], data32 & addr_mask);
}
else if ((data16 & 0xff0f) == 0x6000)
{
sprintf(buffer, "%4.4x bset %s, @%8.8x", opcode, reg_names8[(data16 >> 4) & 0xf], data32 & addr_mask);
}
else
{
sprintf(buffer, "%4.4x ???", opcode);
}
size = 6;
break;
case 0x2: case 0x2:
data32=h8_mem_read32(2); data32=h8_mem_read32(2);
sprintf(buffer, "%4.4x mov.b @%8.8x, %s", opcode, data32&addr_mask, reg_names8[opcode & 0xf]); sprintf(buffer, "%4.4x mov.b @%8.8x, %s", opcode, data32&addr_mask, reg_names8[opcode & 0xf]);

57
src/emu/cpu/h83002/h8ops.h
View File

@ -1,22 +1,3 @@
/*
H8/3xx: Unknown opcode (PC=1c966) 10f - not a valid H8 or H8S opcode, either bad dump or banked ROM
maygayep.c ep_cfallc
H8/3xx: Unknown opcode (PC=6bfffefe) 230 - STMAC
coinmvga.c cmkenosp
H8/3xx: Unknown opcode (PC=67fffefe) 230 - STMAC
coinmvga.c cmkenospa
H8/3xx: Unknown opcode (PC=8f91) aeb - ADD.L ERs, ERd
maygayep.c ep_hogmnc
H8/3xx: Unknown opcode (PC=20000) 6b6e - MOV.B @ERs, Rd
maygayep.c ep_wordf
*/
static UINT32 udata32, address24; static UINT32 udata32, address24;
static INT32 sdata32; static INT32 sdata32;
static UINT16 udata16, ext16; static UINT16 udata16, ext16;
@ -1690,7 +1671,7 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)+4); h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)+4);
// extended mode // extended mode
h8->pc = udata32; h8->pc = udata32 & H8_ADDR_MASK;
} }
// must do this last, because set_ccr() does a check_irq() // must do this last, because set_ccr() does a check_irq()
h8_set_ccr(h8, udata8); h8_set_ccr(h8, udata8);
@ -1910,6 +1891,40 @@ static void h8_group6(h83xx_state *h8, UINT16 opcode)
H8_IFETCH_TIMING(1); H8_IFETCH_TIMING(1);
H8_BYTE_TIMING(1, address24); H8_BYTE_TIMING(1, address24);
break; break;
case 0x1: // btst #xx, @aa:16 or btst Rn, @aa:16
sdata16 = h8_mem_read16(h8, h8->pc);
h8->pc += 2;
address24 = sdata16 & H8_ADDR_MASK;
udata16 = h8_mem_read16(h8, h8->pc);
h8->pc += 2;
udata8 = h8_mem_read8(address24);
if ((udata16 & 0xff00) == 0x7300)
{
h8_btst8(h8, (udata16 >> 4) & 0x7, udata8);
h8_mem_write8(address24, udata8);
}
else if ((udata16 & 0xff0f) == 0x7000)
{
h8_bset8(h8, (udata16 >> 4) & 0x7, udata8);
h8_mem_write8(address24, udata8);
}
else if ((udata16 & 0xff00) == 0x6300)
{
h8_btst8(h8, h8_getreg8(h8, (udata16 >> 4) & 0xf), udata8);
h8_mem_write8(address24, udata8);
}
else if ((udata16 & 0xff0f) == 0x6000)
{
h8_bset8(h8, h8_getreg8(h8, (udata16 >> 4) & 0xf), udata8);
h8_mem_write8(address24, udata8);
}
else
{
h8->h8err = 1;
}
H8_IFETCH_TIMING(3);
H8_BYTE_TIMING(1, address24);
break;
case 0x2: case 0x2:
address24=h8_mem_read32(h8, h8->pc); address24=h8_mem_read32(h8, h8->pc);
h8->pc += 4; h8->pc += 4;
@ -4219,11 +4234,9 @@ static int h8_branch(h83xx_state *h8, UINT8 condition)
if(h8->h8zflag == 1)taken = 1; if(h8->h8zflag == 1)taken = 1;
break; break;
case 8: // bvc V = 0 case 8: // bvc V = 0
h8->h8err = 1;
if(h8->h8vflag == 0)taken = 1; if(h8->h8vflag == 0)taken = 1;
break; break;
case 9: // bvs V = 1 case 9: // bvs V = 1
h8->h8err = 1;
if(h8->h8vflag == 1)taken = 1; if(h8->h8vflag == 1)taken = 1;
break; break;
case 0xa: // bpl N = 0 case 0xa: // bpl N = 0

6
src/emu/cpu/h83002/h8priv.h
View File

@ -76,6 +76,8 @@ struct h83xx_state
H8S2XXX_TPU tpu[6]; H8S2XXX_TPU tpu[6];
H8S2XXX_SCI sci[3]; H8S2XXX_SCI sci[3];
int tpu_max;
UINT8 ddrs[H8_MAX_PORTS], drs[H8_MAX_PORTS], pcrs[H8_MAX_PORTS], odrs[H8_MAX_PORTS]; UINT8 ddrs[H8_MAX_PORTS], drs[H8_MAX_PORTS], pcrs[H8_MAX_PORTS], odrs[H8_MAX_PORTS];
int mode_8bit; int mode_8bit;
@ -122,20 +124,24 @@ UINT8 h8s2241_per_regs_read_8(h83xx_state *h8, int offset);
UINT8 h8s2246_per_regs_read_8(h83xx_state *h8, int offset); UINT8 h8s2246_per_regs_read_8(h83xx_state *h8, int offset);
UINT8 h8s2323_per_regs_read_8(h83xx_state *h8, int offset); UINT8 h8s2323_per_regs_read_8(h83xx_state *h8, int offset);
UINT8 h8s2394_per_regs_read_8(h83xx_state *h8, int offset); UINT8 h8s2394_per_regs_read_8(h83xx_state *h8, int offset);
UINT8 h8s2655_per_regs_read_8(h83xx_state *h8, int offset);
UINT16 h8s2241_per_regs_read_16(h83xx_state *h8, int offset); UINT16 h8s2241_per_regs_read_16(h83xx_state *h8, int offset);
UINT16 h8s2246_per_regs_read_16(h83xx_state *h8, int offset); UINT16 h8s2246_per_regs_read_16(h83xx_state *h8, int offset);
UINT16 h8s2323_per_regs_read_16(h83xx_state *h8, int offset); UINT16 h8s2323_per_regs_read_16(h83xx_state *h8, int offset);
UINT16 h8s2394_per_regs_read_16(h83xx_state *h8, int offset); UINT16 h8s2394_per_regs_read_16(h83xx_state *h8, int offset);
UINT16 h8s2655_per_regs_read_16(h83xx_state *h8, int offset);
void h8s2241_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data); void h8s2241_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
void h8s2246_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data); void h8s2246_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
void h8s2323_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data); void h8s2323_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
void h8s2394_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data); void h8s2394_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
void h8s2655_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
void h8s2241_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data); void h8s2241_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
void h8s2246_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data); void h8s2246_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
void h8s2323_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data); void h8s2323_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
void h8s2394_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data); void h8s2394_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
void h8s2655_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
#endif /* __H8PRIV_H__ */ #endif /* __H8PRIV_H__ */

73
src/emu/cpu/h83002/h8speriph.c
View File

@ -8,6 +8,7 @@
H8S/2246 H8S/2246
H8S/2323 H8S/2323
H8S/2394 H8S/2394
H8S/2655
*/ */
#include "emu.h" #include "emu.h"
@ -404,17 +405,18 @@ void h8s_dtce_check(h83xx_state *h8, int vecnum)
void h8s_periph_reset(h83xx_state *h8) void h8s_periph_reset(h83xx_state *h8)
{ {
const int tpu_max = ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) ? 6 : 3; int tpu_max = h8->tpu_max;
h8->tpu_max = tpu_max;
if ((h8->device->type() == H8S2241) || (h8->device->type() == H8S2246)) if ((h8->device->type() == H8S2241) || (h8->device->type() == H8S2246))
{ {
memcpy( h8->per_regs, H8S_RESET_H8S_IO_224x, sizeof( h8->per_regs)); memcpy( h8->per_regs, H8S_RESET_H8S_IO_224x, sizeof( h8->per_regs));
} }
else if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) else if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394) || (h8->device->type() == H8S2655))
{ {
memcpy( h8->per_regs, H8S_RESET_H8S_IO_2323, sizeof( h8->per_regs)); memcpy( h8->per_regs, H8S_RESET_H8S_IO_2323, sizeof( h8->per_regs));
} }
for (int i = 0; i < 2; i++) h8s_tmr_x_reset( h8, i); for (int i = 0; i < 2; i++) h8s_tmr_x_reset( h8, i);
for (int i = 0; i < tpu_max; i++) h8s_tpu_x_reset( h8, i); for (int i = 0; i < tpu_max; i++) h8s_tpu_x_reset( h8, i );
} }
///////////////// /////////////////
@ -659,7 +661,7 @@ static TIMER_CALLBACK( h8s_tmr_callback)
void h8s_tpu_init(h83xx_state *h8) void h8s_tpu_init(h83xx_state *h8)
{ {
const int tpu_max = ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) ? 6 : 3; const int tpu_max = ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394) || (h8->device->type() == H8S2655)) ? 6 : 3;
for (int i = 0; i < tpu_max; i++) for (int i = 0; i < tpu_max; i++)
{ {
h8->tpu[i].timer = h8->device->machine().scheduler().timer_alloc(FUNC(h8s_tpu_callback), h8); h8->tpu[i].timer = h8->device->machine().scheduler().timer_alloc(FUNC(h8s_tpu_callback), h8);
@ -1128,7 +1130,7 @@ void h8s_tpu_5_write_tior( h83xx_state *h8, UINT8 data)
void h8s_tpu_write_tstr( h83xx_state *h8, UINT8 data) void h8s_tpu_write_tstr( h83xx_state *h8, UINT8 data)
{ {
const int tpu_max = ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) ? 6 : 3; const int tpu_max = h8->tpu_max;
UINT8 old_data = h8->per_regs[H8S_IO_TSTR]; UINT8 old_data = h8->per_regs[H8S_IO_TSTR];
int i; int i;
h8->per_regs[H8S_IO_TSTR] = data; h8->per_regs[H8S_IO_TSTR] = data;
@ -1345,7 +1347,7 @@ void h8s_onchip_reg_write_8(h83xx_state *h8, int offset, UINT8 data)
case H8S_IO_DMABCRL : case H8S_IO_DMABCRL :
{ {
h8->per_regs[offset] = data; h8->per_regs[offset] = data;
if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394) || (h8->device->type() == H8S2655))
{ {
if ((data & 0x40) && (data & 0x80)) if ((data & 0x40) && (data & 0x80))
{ {
@ -1428,14 +1430,13 @@ void h8s_onchip_reg_write_8_ddr(h83xx_state *h8, int offset, UINT8 data)
break; break;
// ... // ...
#if 0
// TPU // TPU
case H8S_IO_TSTR : h8s_tpu_write_tstr( h8, data); break; case H8S_IO_TSTR : h8s_tpu_write_tstr( h8, data); break;
// DMA // DMA
case H8S_IO_DMABCRL : case H8S_IO_DMABCRL :
{ {
h8->per_regs[offset] = data; h8->per_regs[offset] = data;
if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394) || (h8->device->type() == H8S2655))
{ {
if ((data & 0x40) && (data & 0x80)) if ((data & 0x40) && (data & 0x80))
{ {
@ -1458,11 +1459,9 @@ void h8s_onchip_reg_write_8_ddr(h83xx_state *h8, int offset, UINT8 data)
} }
} }
break; break;
#endif
// ... // ...
default : default :
{ {
logerror("H8S: Unknown write %02x to I/O %x\n", data, offset);
h8->per_regs[offset] = data; h8->per_regs[offset] = data;
} }
break; break;
@ -1489,19 +1488,19 @@ void h8s_onchip_reg_write_16(h83xx_state *h8, int offset, UINT16 data)
case H8S_IO_TGR2A_H : h8s_tpu_x_write_tgra( h8, 2, data); break; case H8S_IO_TGR2A_H : h8s_tpu_x_write_tgra( h8, 2, data); break;
case H8S_IO_TGR2B_H : h8s_tpu_x_write_tgrb( h8, 2, data); break; case H8S_IO_TGR2B_H : h8s_tpu_x_write_tgrb( h8, 2, data); break;
// TPU 3 // TPU 3
case H8S_IO_TCNT3_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tcnt( h8, 3, data); break; case H8S_IO_TCNT3_H : if (h8->tpu_max == 6) h8s_tpu_x_write_tcnt( h8, 3, data); break;
case H8S_IO_TGR3A_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgra( h8, 3, data); break; case H8S_IO_TGR3A_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgra( h8, 3, data); break;
case H8S_IO_TGR3B_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrb( h8, 3, data); break; case H8S_IO_TGR3B_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrb( h8, 3, data); break;
case H8S_IO_TGR3C_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrc( h8, 3, data); break; case H8S_IO_TGR3C_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrc( h8, 3, data); break;
case H8S_IO_TGR3D_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrd( h8, 3, data); break; case H8S_IO_TGR3D_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrd( h8, 3, data); break;
// TPU 4 // TPU 4
case H8S_IO_TCNT4_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tcnt( h8, 4, data); break; case H8S_IO_TCNT4_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tcnt( h8, 4, data); break;
case H8S_IO_TGR4A_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgra( h8, 4, data); break; case H8S_IO_TGR4A_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgra( h8, 4, data); break;
case H8S_IO_TGR4B_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrb( h8, 4, data); break; case H8S_IO_TGR4B_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrb( h8, 4, data); break;
// TPU 5 // TPU 5
case H8S_IO_TCNT5_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tcnt( h8, 5, data); break; case H8S_IO_TCNT5_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tcnt( h8, 5, data); break;
case H8S_IO_TGR5A_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgra( h8, 5, data); break; case H8S_IO_TGR5A_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgra( h8, 5, data); break;
case H8S_IO_TGR5B_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrb( h8, 5, data); break; case H8S_IO_TGR5B_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrb( h8, 5, data); break;
// ... // ...
default : default :
{ {
@ -1595,15 +1594,16 @@ UINT8 h8s_onchip_reg_read_8_ddr(h83xx_state *h8, int offset)
} }
break; break;
#if 0 // ADCSR
case H8S_IO_ADCSR: data = ADCSR_ADF; break;
// TMR 0 // TMR 0
case H8S_IO_TCNT0 : data = h8s_tmr_x_read_tcnt( h8, 0); break; case H8S_IO_TCNT0 : data = h8s_tmr_x_read_tcnt( h8, 0); break;
// TMR 1 // TMR 1
case H8S_IO_TCNT1 : data = h8s_tmr_x_read_tcnt( h8, 1); break; case H8S_IO_TCNT1 : data = h8s_tmr_x_read_tcnt( h8, 1); break;
#endif
// ... // ...
// default // default
default : data = h8->per_regs[offset]; logerror("H8S: unhandled I/O read at %x\n", offset); break; default : data = h8->per_regs[offset]; logerror("H8S: possibly unhandled I/O read at %x (PC=%x)\n", offset, h8->ppc); break;
} }
verboselog( h8->device->machine(), 9, "%08X | %08X -> %02X\n", h8->ppc, H8S_IO_ADDR(offset), data); verboselog( h8->device->machine(), 9, "%08X | %08X -> %02X\n", h8->ppc, H8S_IO_ADDR(offset), data);
return data; return data;
@ -1617,9 +1617,9 @@ UINT16 h8s_onchip_reg_read_16(h83xx_state *h8, int offset)
case H8S_IO_TCNT0_H : data = h8s_tpu_x_read_tcnt( h8, 0); break; case H8S_IO_TCNT0_H : data = h8s_tpu_x_read_tcnt( h8, 0); break;
case H8S_IO_TCNT1_H : data = h8s_tpu_x_read_tcnt( h8, 1); break; case H8S_IO_TCNT1_H : data = h8s_tpu_x_read_tcnt( h8, 1); break;
case H8S_IO_TCNT2_H : data = h8s_tpu_x_read_tcnt( h8, 2); break; case H8S_IO_TCNT2_H : data = h8s_tpu_x_read_tcnt( h8, 2); break;
case H8S_IO_TCNT3_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) data = h8s_tpu_x_read_tcnt( h8, 3); break; case H8S_IO_TCNT3_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 3); break;
case H8S_IO_TCNT4_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) data = h8s_tpu_x_read_tcnt( h8, 4); break; case H8S_IO_TCNT4_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 4); break;
case H8S_IO_TCNT5_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) data = h8s_tpu_x_read_tcnt( h8, 5); break; case H8S_IO_TCNT5_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 5); break;
default : default :
{ {
UINT8 b[2]; UINT8 b[2];
@ -1713,4 +1713,23 @@ UINT16 h8s2394_per_regs_read_16(h83xx_state *h8, int offset)
return h8s_onchip_reg_read_16(h8, offset); return h8s_onchip_reg_read_16(h8, offset);
} }
void h8s2655_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data)
{
h8s_onchip_reg_write_8_ddr(h8, offset, data);
}
UINT8 h8s2655_per_regs_read_8(h83xx_state *h8, int offset)
{
return h8s_onchip_reg_read_8_ddr(h8, offset);
}
void h8s2655_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data)
{
h8s_onchip_reg_write_16(h8, offset, data);
}
UINT16 h8s2655_per_regs_read_16(h83xx_state *h8, int offset)
{
return h8s_onchip_reg_read_16(h8, offset);
}