Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-05 08:41:31 +03:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

Use the same mcpx_isalpc device in both nforcepc and xbox (nw)

Browse Source 
Also use new smbus_logger device in nforcepc to log smbus accesses
This commit is contained in:
yz70s 2019-01-06 21:34:17 +01:00
parent 01f78f3440
commit d9e580c6df
6 changed files with 121 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

94
src/mame/drivers/nforcepc.cpp
View File

@ -24,13 +24,16 @@
#include "cpu/i386/i386.h"
#include "machine/pci.h"
#include "machine/pci-ide.h"
#include "includes/xbox_pci.h"
#include "includes/nforcepc.h"
/*
Pci devices
*/
DEFINE_DEVICE_TYPE(CRUSH11, crush11_host_device, "crush11", "NVIDIA Corporation nForce CPU bridge")
// NVIDIA Corporation nForce CPU bridge
DEFINE_DEVICE_TYPE(CRUSH11, crush11_host_device, "CRUSH11", "NVIDIA Corporation nForce CPU bridge")
void crush11_host_device::config_map(address_map &map)
{
@ -98,6 +101,36 @@ WRITE8_MEMBER(crush11_host_device::test_w)
logerror("test = %02x\n", data);
}
// device connected to SMBus
DEFINE_DEVICE_TYPE(SMBUS_LOGGER, smbus_logger_device, "smbus_logger", "SMBUS LOGGER")
smbus_logger_device::smbus_logger_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SMBUS_LOGGER, tag, owner, clock)
{
}
int smbus_logger_device::execute_command(int command, int rw, int data)
{
if (rw == 1) // read
{
logerror("smbus read %02x %d %02x\n", command, rw, buffer[command]);
return buffer[command];
}
buffer[command] = (uint8_t)data;
logerror("smbus write %02x %d %02d\n", command, rw, data);
return 0;
}
void smbus_logger_device::device_start()
{
memset(buffer, 0, sizeof(buffer));
}
void smbus_logger_device::device_reset()
{
}
/*
Machine state
*/
@ -105,7 +138,8 @@ WRITE8_MEMBER(crush11_host_device::test_w)
class nforcepc_state : public driver_device
{
public:
struct boot_state_info {
struct boot_state_info
{
uint8_t val;
const char *const message;
};
@ -120,12 +154,20 @@ private:
void nforce_map(address_map &map);
void nforce_map_io(address_map &map);
DECLARE_WRITE8_MEMBER(boot_state_award_w);
IRQ_CALLBACK_MEMBER(irq_callback);
DECLARE_WRITE_LINE_MEMBER(maincpu_interrupt);
virtual void machine_start() override;
virtual void machine_reset() override;
required_device<cpu_device> m_maincpu;
required_device<mcpx_isalpc_device> isalpc;
};
nforcepc_state::nforcepc_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag)
nforcepc_state::nforcepc_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
isalpc(*this, ":pci:01.0")
{
}
@ -138,14 +180,16 @@ void nforcepc_state::machine_reset()
}
const nforcepc_state::boot_state_info nforcepc_state::boot_state_infos_award[] = {
{ 0xC0, "Turn off chipset cache" },
{ 0, nullptr }
};
WRITE8_MEMBER(nforcepc_state::boot_state_award_w)
{
const char *desc = "";
for(int i=0; boot_state_infos_award[i].message; i++)
if(boot_state_infos_award[i].val == data) {
for (int i = 0; boot_state_infos_award[i].message; i++)
if (boot_state_infos_award[i].val == data)
{
desc = boot_state_infos_award[i].message;
break;
}
@ -153,6 +197,16 @@ WRITE8_MEMBER(nforcepc_state::boot_state_award_w)
}
IRQ_CALLBACK_MEMBER(nforcepc_state::irq_callback)
{
return isalpc->acknowledge();
}
WRITE_LINE_MEMBER(nforcepc_state::maincpu_interrupt)
{
m_maincpu->set_input_line(0, state ? HOLD_LINE : CLEAR_LINE);
}
void nforcepc_state::nforce_map(address_map &map)
{
map.unmap_value_high();
@ -172,14 +226,30 @@ void nforcepc_state::nforcepc(machine_config &config)
athlonxp_device &maincpu(ATHLONXP(config, "maincpu", 90000000));
maincpu.set_addrmap(AS_PROGRAM, &nforcepc_state::nforce_map);
maincpu.set_addrmap(AS_IO, &nforcepc_state::nforce_map_io);
PCI_ROOT(config, ":pci", 0);
CRUSH11(config, ":pci:00.0", 0, "maincpu", 2 * 1024 * 1024);
/* maincpu.set_irq_acknowledge_callback("pci:07.0:pic8259_master", FUNC(pic8259_device::inta_cb));
maincpu.smiact().set("pci:00.0", FUNC(i82439hx_host_device::smi_act_w));
maincpu.set_irq_acknowledge_callback(FUNC(nforcepc_state::irq_callback));
i82371sb_isa_device &isa(I82371SB_ISA(config, ":pci:07.0", 0));
isa.boot_state_hook().set(FUNC(nforcepc_state::boot_state_phoenix_ver40_rev6_w));
isa.smi().set_inputline(":maincpu", INPUT_LINE_SMI);
PCI_ROOT(config, ":pci", 0);
CRUSH11(config, ":pci:00.0", 0, "maincpu", 2 * 1024 * 1024); /* 10de:01a4 NVIDIA Corporation nForce CPU bridge
10de:01ac NVIDIA Corporation nForce 220/420 Memory Controller
10de:01ad NVIDIA Corporation nForce 220/420 Memory Controller
10de:01ab NVIDIA Corporation nForce 420 Memory Controller (DDR)*/
mcpx_isalpc_device &isa(MCPX_ISALPC(config, ":pci:01.0", 0, 0x10430c11)); // 10de:01b2 NVIDIA Corporation nForce ISA Bridge (LPC bus)
isa.boot_state_hook().set(FUNC(nforcepc_state::boot_state_award_w));
isa.interrupt_output().set(FUNC(nforcepc_state::maincpu_interrupt));
MCPX_SMBUS(config, ":pci:01.1", 0); // 10de:01b4 NVIDIA Corporation nForce PCI System Management (SMBus)
SMBUS_LOGGER(config, ":pci:01.1:08", 0);
SMBUS_LOGGER(config, ":pci:01.1:2d", 0);
SMBUS_LOGGER(config, ":pci:01.1:48", 0);
SMBUS_LOGGER(config, ":pci:01.1:49", 0);
/*10de:01c2 NVIDIA Corporation nForce USB Controller
10de:01c2 NVIDIA Corporation nForce USB Controller
10de:01b0 NVIDIA Corporation nForce Audio Processing Unit
10de:01b1 NVIDIA Corporation nForce AC'97 Audio Controller
10de:01b8 NVIDIA Corporation nForce PCI-to-PCI bridge
10de:01bc NVIDIA Corporation nForce IDE
10de:01b7 NVIDIA Corporation nForce AGP to PCI Bridge
*/
/* maincpu.smiact().set("pci:00.0", FUNC(i82439hx_host_device::smi_act_w));
i82371sb_ide_device &ide(I82371SB_IDE(config, ":pci:07.1", 0));
ide.irq_pri().set(":pci:07.0", FUNC(i82371sb_isa_device::pc_irq14_w));

18
src/mame/includes/nforcepc.h
View File

@ -44,4 +44,22 @@ private:
DECLARE_DEVICE_TYPE(CRUSH11, crush11_host_device)
// device connected to SMBus
class smbus_logger_device : public device_t, public smbus_interface
{
public:
smbus_logger_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual int execute_command(int command, int rw, int data) override;
protected:
virtual void device_start() override;
virtual void device_reset() override;
private:
uint8_t buffer[0xff];
};
DECLARE_DEVICE_TYPE(SMBUS_LOGGER, smbus_logger_device)
#endif

3
src/mame/includes/xbox.h
View File

@ -108,9 +108,6 @@ protected:
virtual void machine_start() override;
DECLARE_WRITE_LINE_MEMBER(maincpu_interrupt);
DECLARE_READ8_MEMBER(get_slave_ack);
DECLARE_WRITE_LINE_MEMBER(pit8254_out0_changed);
DECLARE_WRITE_LINE_MEMBER(pit8254_out2_changed);
DECLARE_WRITE_LINE_MEMBER(ohci_usb_interrupt_changed);
DECLARE_WRITE_LINE_MEMBER(smbus_interrupt_changed);
DECLARE_WRITE_LINE_MEMBER(ide_interrupt_changed);

4
src/mame/includes/xbox_pci.h
View File

@ -60,15 +60,18 @@ DECLARE_DEVICE_TYPE(NV2A_RAM, nv2a_ram_device)
class mcpx_isalpc_device : public pci_device {
public:
mcpx_isalpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subsystem_id);
mcpx_isalpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
auto interrupt_output() { return m_interrupt_output.bind(); }
auto boot_state_hook() { return m_boot_state_hook.bind(); }
uint32_t acknowledge();
void debug_generate_irq(int irq, int state);
DECLARE_READ32_MEMBER(lpc_r);
DECLARE_WRITE32_MEMBER(lpc_w);
DECLARE_WRITE8_MEMBER(boot_state_w);
DECLARE_WRITE_LINE_MEMBER(irq1);
DECLARE_WRITE_LINE_MEMBER(irq3);
@ -93,6 +96,7 @@ private:
void lpc_io(address_map &map);
devcb_write_line m_interrupt_output;
devcb_write8 m_boot_state_hook;
required_device<pic8259_device> pic8259_1;
required_device<pic8259_device> pic8259_2;
required_device<pit8254_device> pit8254;

2
src/mame/machine/xbox.cpp
View File

@ -850,7 +850,7 @@ MACHINE_CONFIG_START(xbox_base_state::xbox_base)
PCI_ROOT(config, ":pci", 0);
NV2A_HOST(config, ":pci:00.0", 0, m_maincpu);
NV2A_RAM(config, ":pci:00.3", 0);
MCPX_ISALPC(config, ":pci:01.0", 0).interrupt_output().set(FUNC(xbox_base_state::maincpu_interrupt));
MCPX_ISALPC(config, ":pci:01.0", 0, 0).interrupt_output().set(FUNC(xbox_base_state::maincpu_interrupt));
MCPX_SMBUS(config, ":pci:01.1", 0).interrupt_handler().set(FUNC(xbox_base_state::smbus_interrupt_changed));
XBOX_PIC16LC(config, ":pci:01.1:10", 0);
XBOX_CX25871(config, ":pci:01.1:45", 0);

18
src/mame/machine/xbox_pci.cpp
View File

@ -21,7 +21,7 @@ nv2a_host_device::nv2a_host_device(const machine_config &mconfig, const char *ta
pci_host_device(mconfig, NV2A_HOST, tag, owner, clock),
cpu(*this, finder_base::DUMMY_TAG)
{
set_ids(0x10de01b0, 0, 0, 0);
set_ids_host(0x10de02a5, 0, 0);
}
void nv2a_host_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
@ -94,6 +94,7 @@ void mcpx_isalpc_device::internal_io_map(address_map &map)
map(0x0020, 0x0023).rw("pic8259_1", FUNC(pic8259_device::read), FUNC(pic8259_device::write));
map(0x0040, 0x0043).rw("pit8254", FUNC(pit8254_device::read), FUNC(pit8254_device::write));
map(0x0070, 0x0073).rw("rtc", FUNC(ds12885ext_device::read), FUNC(ds12885ext_device::write));
map(0x0080, 0x0080).w(FUNC(mcpx_isalpc_device::boot_state_w));
map(0x00a0, 0x00a3).rw("pic8259_2", FUNC(pic8259_device::read), FUNC(pic8259_device::write));
}
@ -103,20 +104,27 @@ void mcpx_isalpc_device::map_extra(uint64_t memory_window_start, uint64_t memory
io_space->install_device(0, 0xffff, *this, &mcpx_isalpc_device::internal_io_map);
}
mcpx_isalpc_device::mcpx_isalpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subsystem_id)
: mcpx_isalpc_device(mconfig, tag, owner, clock)
{
set_ids(0x10de01b2, 0xb4, 0, subsystem_id); // revision id must be at least 0xb4, otherwise usb will require a hub
}
mcpx_isalpc_device::mcpx_isalpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, MCPX_ISALPC, tag, owner, clock),
m_interrupt_output(*this),
m_boot_state_hook(*this),
pic8259_1(*this, "pic8259_1"),
pic8259_2(*this, "pic8259_2"),
pit8254(*this, "pit8254")
{
set_ids(0x10de01b2, 0xb4, 0, 0); // revision id must be at least 0xb4, otherwise usb will require a hub
}
void mcpx_isalpc_device::device_start()
{
pci_device::device_start();
m_interrupt_output.resolve_safe();
m_boot_state_hook.resolve_safe();
add_map(0x00000100, M_IO, FUNC(mcpx_isalpc_device::lpc_io));
bank_infos[0].adr = 0x8000;
}
@ -163,6 +171,12 @@ WRITE32_MEMBER(mcpx_isalpc_device::lpc_w)
{
}
WRITE8_MEMBER(mcpx_isalpc_device::boot_state_w)
{
if (m_boot_state_hook)
m_boot_state_hook((offs_t)0, data);
}
WRITE_LINE_MEMBER(mcpx_isalpc_device::interrupt_ouptut_changed)
{
m_interrupt_output(state);