mirror of
https://github.com/holub/mame
synced 2025-05-30 17:41:47 +03:00
xbox/chihiro/nforcepc: share pci devices between xbox and nforcepc (nw)
Add separate device for xbox debug serial port Pci ide device starts supporting both channels and pci ide specification native-pci and compatibility modes
This commit is contained in:
yz70s
parent
f2fa042761
commit
da26956ec1
@ -622,7 +622,7 @@ class chihiro_state : public xbox_base_state
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public:
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chihiro_state(const machine_config &mconfig, device_type type, const char *tag)
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: xbox_base_state(mconfig, type, tag)
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, m_ide(*this, "ide")
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, m_ide(*this, "ide1")
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, m_dimmboard(*this, "rom_board")
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, m_hack_index(-1)
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, m_hack_counter(0)
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@ -1763,13 +1763,11 @@ WRITE32_MEMBER(chihiro_state::mediaboard_w)
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void chihiro_state::chihiro_map(address_map &map)
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{
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xbox_base_map(map);
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map(0xff000000, 0xff07ffff).rom().region("bios", 0).mirror(0x00f80000);
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}
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void chihiro_state::chihiro_map_io(address_map &map)
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{
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xbox_base_map_io(map);
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map(0x4000, 0x40ff).rw(FUNC(chihiro_state::mediaboard_r), FUNC(chihiro_state::mediaboard_w));
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}
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@ -1915,7 +1913,7 @@ void chihiro_state::chihiro_base(machine_config &config)
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m_maincpu->set_addrmap(AS_PROGRAM, &chihiro_state::chihiro_map);
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m_maincpu->set_addrmap(AS_IO, &chihiro_state::chihiro_map_io);
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subdevice<ide_controller_32_device>(":pci:09.0:ide")->options(ide_baseboard, nullptr, "bb", true);
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subdevice<ide_controller_32_device>(":pci:09.0:ide1")->options(ide_baseboard, nullptr, "bb", true);
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OHCI_USB_CONNECTOR(config, ":pci:02.0:port1", usb_baseboard, "an2131qc", true).set_option_machine_config("an2131qc", an2131qc_configuration);
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OHCI_USB_CONNECTOR(config, ":pci:02.0:port2", usb_baseboard, "an2131sc", true).set_option_machine_config("an2131sc", an2131sc_configuration);
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@ -26,6 +26,8 @@
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#include "machine/pci.h"
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#include "machine/pci-ide.h"
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#include "machine/intelfsh.h"
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#include "machine/atapicdr.h"
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#include "machine/idehd.h"
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#include "includes/xbox_pci.h"
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#include "includes/nforcepc.h"
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@ -53,6 +55,12 @@ static const uint8_t test_spd_data[] = {
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};
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#endif
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void nforcepc_ata_devices(device_slot_interface &device)
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{
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device.option_add("hdd", IDE_HARDDISK);
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device.option_add("cdrom", ATAPI_CDROM);
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}
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/*
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Pci devices
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*/
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@ -64,10 +72,16 @@ DEFINE_DEVICE_TYPE(CRUSH11, crush11_host_device, "crush11", "NVIDIA Corporation
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void crush11_host_device::config_map(address_map &map)
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{
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pci_host_device::config_map(map);
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map(0x10, 0x27).rw(FUNC(pci_device::address_base_r), FUNC(pci_device::address_base_w));
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map(0x84, 0x87).rw(FUNC(crush11_host_device::ram_size_r), FUNC(crush11_host_device::ram_size_w));
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map(0xf0, 0xf0).rw(FUNC(crush11_host_device::unknown_r), FUNC(crush11_host_device::unknown_w));
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}
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READ8_MEMBER(crush11_host_device::header_type_r)
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{
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return 0x80; // from lspci dump
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}
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crush11_host_device::crush11_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pci_host_device(mconfig, CRUSH11, tag, owner, clock)
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, cpu(*this, finder_base::DUMMY_TAG)
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@ -79,6 +93,7 @@ crush11_host_device::crush11_host_device(const machine_config &mconfig, const ch
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void crush11_host_device::device_start()
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{
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pci_host_device::device_start();
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set_multifunction_device(true);
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memory_space = &cpu->space(AS_DATA);
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io_space = &cpu->space(AS_IO);
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@ -88,7 +103,7 @@ void crush11_host_device::device_start()
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io_window_start = 0;
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io_window_end = 0xffff;
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io_offset = 0;
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status = 0x0010;
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status = 0x00b0;
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}
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void crush11_host_device::reset_all_mappings()
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@ -172,9 +187,11 @@ void crush11_memory_device::device_start()
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device_t *r = owner()->subdevice("00.0");
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pci_device::device_start();
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set_multifunction_device(true);
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ram.resize(ddr_ram_size * 1024 * 1024 / 4);
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host = dynamic_cast<crush11_host_device *>(r);
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ram_space = host->get_cpu_space(AS_PROGRAM);
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status = 0x0020;
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}
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void crush11_memory_device::device_reset()
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@ -703,13 +720,13 @@ void nforcepc_state::nforcepc(machine_config &config)
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maincpu.set_addrmap(AS_PROGRAM, &nforcepc_state::nforce_map);
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maincpu.set_addrmap(AS_IO, &nforcepc_state::nforce_map_io);
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maincpu.set_irq_acknowledge_callback(FUNC(nforcepc_state::irq_callback));
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//maincpu.smiact().set("pci:01.0", FUNC(i82439hx_host_device::smi_act_w));
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//maincpu.smiact().set("pci:01.0", FUNC(???_host_device::smi_act_w));
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PCI_ROOT(config, ":pci", 0);
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CRUSH11(config, ":pci:00.0", 0, "maincpu", "bios"); // 10de:01a4 NVIDIA Corporation nForce CPU bridge
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CRUSH11_MEMORY(config, ":pci:00.1", 0, 2); /* 10de:01ac NVIDIA Corporation nForce 220/420 Memory Controller
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10de:01ad NVIDIA Corporation nForce 220/420 Memory Controller
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10de:01ab NVIDIA Corporation nForce 420 Memory Controller (DDR)*/
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CRUSH11_MEMORY(config, ":pci:00.1", 0, 2); // 10de:01ac NVIDIA Corporation nForce 220/420 Memory Controller
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// 10de:01ad NVIDIA Corporation nForce 220/420 Memory Controller
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// 10de:01ab NVIDIA Corporation nForce 420 Memory Controller (DDR)
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mcpx_isalpc_device &isa(MCPX_ISALPC(config, ":pci:01.0", 0, 0x10430c11)); // 10de:01b2 NVIDIA Corporation nForce ISA Bridge (LPC bus)
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isa.smi().set_inputline(":maincpu", INPUT_LINE_SMI);
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isa.boot_state_hook().set(FUNC(nforcepc_state::boot_state_award_w));
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@ -725,20 +742,21 @@ void nforcepc_state::nforcepc(machine_config &config)
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AS99127F(config, ":pci:01.1:12d", 0);
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AS99127F_SENSOR2(config, ":pci:01.1:148", 0);
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AS99127F_SENSOR3(config, ":pci:01.1:149", 0);
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MCPX_OHCI(config, ":pci:02.0", 0); // 10de:01c2 NVIDIA Corporation nForce USB Controller
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// .interrupt_handler().set(FUNC(nforcepc_state::ohci_usb_interrupt_changed));
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MCPX_OHCI(config, ":pci:03.0", 0); // 10de:01c2 NVIDIA Corporation nForce USB Controller
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MCPX_ETH(config, ":pci:04.0", 0); // 10de:01c3 NVIDIA Corporation nForce Ethernet Controller
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MCPX_APU(config, ":pci:05.0", 0, m_maincpu); // 10de:01b0 NVIDIA Corporation nForce Audio Processing Unit
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MCPX_AC97_AUDIO(config, ":pci:06.0", 0); // 10de:01b1 NVIDIA Corporation nForce AC'97 Audio Controller
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PCI_BRIDGE(config, ":pci:08.0", 0, 0x10de01b8, 0); // 10de:01b8 NVIDIA Corporation nForce PCI-to-PCI bridge
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// 10ec:8139 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (behind bridge)
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MCPX_IDE(config, ":pci:09.0", 0); // 10de:01bc NVIDIA Corporation nForce IDE
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/* subdevice<ide_controller_32_device>(":pci:09.0:ide")->options(nforcepc_ata_devices, "hdd", "cdrom", true);
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.interrupt_handler().set(FUNC(nforcepc_state::ide_interrupt_changed));
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ide.irq_pri().set(":pci:01.0", FUNC(mcpx_isalpc_device::pc_irq14_w));
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ide.irq_sec().set(":pci:01.0", FUNC(mcpx_isalpc_device::pc_irq15_w));*/
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NV2A_AGP(config, ":pci:1e.0", 0, 0x10de01b7, 0); // 10de:01b7 NVIDIA Corporation nForce AGP to PCI Bridge
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SST_49LF020(config, "bios", 0);
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/*10de:01c2 NVIDIA Corporation nForce USB Controller
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10de:01c2 NVIDIA Corporation nForce USB Controller
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10de:01b0 NVIDIA Corporation nForce Audio Processing Unit
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10de:01b1 NVIDIA Corporation nForce AC'97 Audio Controller
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10de:01b8 NVIDIA Corporation nForce PCI-to-PCI bridge
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10de:01bc NVIDIA Corporation nForce IDE
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10de:01b7 NVIDIA Corporation nForce AGP to PCI Bridge
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*/
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/* maincpu.smiact().set("pci:00.0", FUNC(i82439hx_host_device::smi_act_w));
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i82371sb_ide_device &ide(I82371SB_IDE(config, ":pci:07.1", 0));
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ide.irq_pri().set(":pci:07.0", FUNC(i82371sb_isa_device::pc_irq14_w));
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ide.irq_sec().set(":pci:07.0", FUNC(i82371sb_isa_device::pc_irq15_w));*/
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}
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ROM_START(nforcepc)
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@ -4,8 +4,6 @@
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XBOX (c) 2001 Microsoft
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Skeleton driver
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***************************************************************************/
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@ -33,15 +31,14 @@ class xbox_state : public xbox_base_state
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public:
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xbox_state(const machine_config &mconfig, device_type type, const char *tag)
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: xbox_base_state(mconfig, type, tag)
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, m_ide(*this, "pci:09.0:ide")
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, m_devh(*this, "pci:09.0:ide:0:hdd")
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, m_devc(*this, "pci:09.0:ide:1:cdrom")
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, m_ide(*this, "pci:09.0:ide1")
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, m_devh(*this, "pci:09.0:ide1:0:hdd")
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, m_devc(*this, "pci:09.0:ide1:1:cdrom")
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{ }
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void xbox(machine_config &config);
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protected:
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void xbox_map(address_map &map);
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void xbox_map_io(address_map &map);
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// driver_device overrides
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virtual void machine_start() override;
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@ -62,15 +59,9 @@ void xbox_state::video_start()
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void xbox_state::xbox_map(address_map &map)
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{
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xbox_base_map(map);
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map(0xff000000, 0xff0fffff).rom().region("bios", 0).mirror(0x00f00000);
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}
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void xbox_state::xbox_map_io(address_map &map)
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{
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xbox_base_map_io(map);
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}
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static INPUT_PORTS_START( xbox )
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/* dummy active high structure */
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PORT_START("SYSA")
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@ -174,9 +165,8 @@ void xbox_state::xbox(machine_config &config)
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{
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xbox_base(config);
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m_maincpu->set_addrmap(AS_PROGRAM, &xbox_state::xbox_map);
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m_maincpu->set_addrmap(AS_IO, &xbox_state::xbox_map_io);
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subdevice<ide_controller_32_device>(":pci:09.0:ide")->options(xbox_ata_devices, "hdd", "cdrom", true);
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subdevice<ide_controller_32_device>(":pci:09.0:ide1")->options(xbox_ata_devices, "hdd", "cdrom", true);
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OHCI_USB_CONNECTOR(config, ":pci:02.0:port1", usb_xbox, nullptr, false);
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OHCI_USB_CONNECTOR(config, ":pci:02.0:port2", usb_xbox, nullptr, false);
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@ -43,6 +43,7 @@ private:
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required_device<intelfsh8_device> biosrom;
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uint32_t ram_size;
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virtual DECLARE_READ8_MEMBER(header_type_r) override;
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DECLARE_READ8_MEMBER(unknown_r);
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DECLARE_WRITE8_MEMBER(unknown_w);
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DECLARE_READ32_MEMBER(ram_size_r);
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@ -71,6 +71,40 @@ private:
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DECLARE_DEVICE_TYPE(XBOX_EEPROM, xbox_eeprom_device)
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/*
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* Super-io connected to lpc bus used as a rs232 debug port
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*/
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class xbox_superio_device : public device_t, public lpcbus_device_interface
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{
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public:
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xbox_superio_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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virtual void map_extra(address_space *memory_space, address_space *io_space) override;
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virtual void set_host(int index, lpcbus_host_interface *host) override;
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DECLARE_READ8_MEMBER(read);
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DECLARE_WRITE8_MEMBER(write);
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DECLARE_READ8_MEMBER(read_rs232);
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DECLARE_WRITE8_MEMBER(write_rs232);
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protected:
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virtual void device_start() override;
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private:
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void internal_io_map(address_map &map);
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lpcbus_host_interface *lpchost;
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int lpcindex;
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address_space *memspace;
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address_space *iospace;
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bool configuration_mode;
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int index;
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int selected;
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uint8_t registers[16][256]; // 256 registers for up to 16 devices, registers 0-0x2f common to all
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};
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DECLARE_DEVICE_TYPE(XBOX_SUPERIO, xbox_superio_device)
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/*
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* Base
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*/
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@ -85,20 +119,12 @@ public:
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debug_irq_number(0),
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m_maincpu(*this, "maincpu"),
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mcpxlpc(*this, ":pci:01.0"),
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ide(*this, ":pci:09.0:ide"),
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ide(*this, ":pci:09.0:ide1"),
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debugc_bios(nullptr) { }
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void xbox_base(machine_config &config);
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protected:
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DECLARE_READ8_MEMBER(superio_read);
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DECLARE_WRITE8_MEMBER(superio_write);
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DECLARE_READ8_MEMBER(superiors232_read);
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DECLARE_WRITE8_MEMBER(superiors232_write);
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int smbus_pic16lc(int command, int rw, int data);
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int smbus_cx25871(int command, int rw, int data);
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int smbus_eeprom(int command, int rw, int data);
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void debug_generate_irq(int irq, bool active);
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virtual void hack_eeprom() {};
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virtual void hack_usb() {};
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@ -114,13 +140,6 @@ protected:
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DECLARE_WRITE_LINE_MEMBER(nv2a_interrupt_changed);
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IRQ_CALLBACK_MEMBER(irq_callback);
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struct superio_state
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{
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bool configuration_mode;
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int index;
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int selected;
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uint8_t registers[16][256]; // 256 registers for up to 16 devices, registers 0-0x2f common to all
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} superiost;
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nv2a_renderer *nvidia_nv2a;
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bool debug_irq_active;
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int debug_irq_number;
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@ -134,9 +153,6 @@ protected:
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} debugp[];
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const debugger_constants *debugc_bios;
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void xbox_base_map(address_map &map);
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void xbox_base_map_io(address_map &map);
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private:
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void dump_string_command(int ref, const std::vector<std::string> ¶ms);
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void dump_process_command(int ref, const std::vector<std::string> ¶ms);
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@ -503,6 +503,7 @@ public:
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void debug_grab_texture(int type, const char *filename);
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void debug_grab_vertex_program_slot(int slot, uint32_t *instruction);
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void start(address_space *cpu_space);
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void set_ram_base(void *base);
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void savestate_items();
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void compute_supersample_factors(float &horizontal, float &vertical);
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void compute_limits_rendertarget(uint32_t chanel, uint32_t subchannel);
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@ -43,13 +43,27 @@ DECLARE_DEVICE_TYPE(NV2A_HOST, nv2a_host_device)
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class nv2a_ram_device : public pci_device {
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public:
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nv2a_ram_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, int memory_size)
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: nv2a_ram_device(mconfig, tag, owner, clock)
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{
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ram_size = memory_size;
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}
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nv2a_ram_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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virtual void config_map(address_map &map) override;
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virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
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uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
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protected:
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virtual void device_start() override;
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DECLARE_READ32_MEMBER(config_register_r);
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DECLARE_WRITE32_MEMBER(config_register_w);
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private:
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int ram_size;
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std::vector<uint32_t> ram;
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};
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DECLARE_DEVICE_TYPE(NV2A_RAM, nv2a_ram_device)
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@ -117,6 +131,12 @@ private:
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required_device<pic8259_device> pic8259_2;
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required_device<pit8254_device> pit8254;
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uint16_t m_pm1_status;
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uint16_t m_pm1_enable;
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uint16_t m_pm1_control;
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uint16_t m_pm1_timer;
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uint16_t m_gpe0_status;
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uint16_t m_gpe0_enable;
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uint16_t m_global_smi_control;
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uint8_t m_smi_command_port;
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lpcbus_device_interface *lpcdevices[16];
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@ -332,17 +352,30 @@ class mcpx_ide_device : public pci_device {
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public:
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mcpx_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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auto interrupt_handler() { return m_interrupt_handler.bind(); }
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auto pri_interrupt_handler() { return m_pri_interrupt_handler.bind(); }
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auto sec_interrupt_handler() { return m_sec_interrupt_handler.bind(); }
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virtual void config_map(address_map &map) override;
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|
||||
DECLARE_WRITE32_MEMBER(class_rev_w);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
|
||||
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
|
||||
|
||||
private:
|
||||
devcb_write_line m_interrupt_handler;
|
||||
void mcpx_ide_io(address_map &map);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
devcb_write_line m_pri_interrupt_handler;
|
||||
devcb_write_line m_sec_interrupt_handler;
|
||||
void ide_pri_command(address_map &map);
|
||||
void ide_pri_control(address_map &map);
|
||||
void ide_sec_command(address_map &map);
|
||||
void ide_sec_control(address_map &map);
|
||||
void ide_io(address_map &map);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_pri_interrupt);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_sec_interrupt);
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(MCPX_IDE, mcpx_ide_device)
|
||||
|
||||
@ -573,77 +573,6 @@ WRITE_LINE_MEMBER(xbox_base_state::ide_interrupt_changed)
|
||||
mcpxlpc->irq14(state);
|
||||
}
|
||||
|
||||
/*
|
||||
* SuperIO
|
||||
*/
|
||||
|
||||
READ8_MEMBER(xbox_base_state::superio_read)
|
||||
{
|
||||
if (superiost.configuration_mode == false)
|
||||
return 0;
|
||||
if (offset == 0) // index port 0x2e
|
||||
return superiost.index;
|
||||
if (offset == 1)
|
||||
{
|
||||
// data port 0x2f
|
||||
if (superiost.index < 0x30)
|
||||
return superiost.registers[0][superiost.index];
|
||||
return superiost.registers[superiost.selected][superiost.index];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(xbox_base_state::superio_write)
|
||||
{
|
||||
if (superiost.configuration_mode == false)
|
||||
{
|
||||
// config port 0x2e
|
||||
if ((offset == 0) && (data == 0x55))
|
||||
superiost.configuration_mode = true;
|
||||
return;
|
||||
}
|
||||
if ((offset == 0) && (data == 0xaa))
|
||||
{
|
||||
// config port 0x2e
|
||||
superiost.configuration_mode = false;
|
||||
return;
|
||||
}
|
||||
if (offset == 0)
|
||||
{
|
||||
// index port 0x2e
|
||||
superiost.index = data;
|
||||
}
|
||||
if (offset == 1)
|
||||
{
|
||||
// data port 0x2f
|
||||
if (superiost.index < 0x30)
|
||||
{
|
||||
superiost.registers[0][superiost.index] = data;
|
||||
superiost.selected = superiost.registers[0][7];
|
||||
} else
|
||||
{
|
||||
superiost.registers[superiost.selected][superiost.index] = data;
|
||||
//if ((superiost.selected == 4) && (superiost.index == 0x30) && (data != 0))
|
||||
// ; // add handlers 0x3f8- +7
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(xbox_base_state::superiors232_read)
|
||||
{
|
||||
if (offset == 5)
|
||||
return 0x20;
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(xbox_base_state::superiors232_write)
|
||||
{
|
||||
if (offset == 0)
|
||||
{
|
||||
printf("%c", data);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* SMbus devices
|
||||
*/
|
||||
@ -778,6 +707,114 @@ void xbox_eeprom_device::device_reset()
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Super-io connected to lpc bus
|
||||
*/
|
||||
|
||||
DEFINE_DEVICE_TYPE(XBOX_SUPERIO, xbox_superio_device, "superio_device", "XBOX debug SuperIO")
|
||||
|
||||
xbox_superio_device::xbox_superio_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
|
||||
: device_t(mconfig, XBOX_SUPERIO, tag, owner, clock)
|
||||
, configuration_mode(false)
|
||||
, index(0)
|
||||
, selected(0)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void xbox_superio_device::internal_io_map(address_map &map)
|
||||
{
|
||||
map(0x002e, 0x002f).rw(FUNC(xbox_superio_device::read), FUNC(xbox_superio_device::write));
|
||||
map(0x03f8, 0x03ff).rw(FUNC(xbox_superio_device::read_rs232), FUNC(xbox_superio_device::write_rs232));
|
||||
}
|
||||
|
||||
void xbox_superio_device::map_extra(address_space *memory_space, address_space *io_space)
|
||||
{
|
||||
memspace = memory_space;
|
||||
iospace = io_space;
|
||||
io_space->install_device(0, 0xffff, *this, &xbox_superio_device::internal_io_map);
|
||||
}
|
||||
|
||||
void xbox_superio_device::set_host(int index, lpcbus_host_interface *host)
|
||||
{
|
||||
lpchost = host;
|
||||
lpcindex = index;
|
||||
}
|
||||
|
||||
void xbox_superio_device::device_start()
|
||||
{
|
||||
memset(registers, 0, sizeof(registers));
|
||||
registers[0][0x26] = 0x2e; // Configuration port address byte 0
|
||||
}
|
||||
|
||||
READ8_MEMBER(xbox_superio_device::read)
|
||||
{
|
||||
if (configuration_mode == false)
|
||||
return 0;
|
||||
if (offset == 0) // index port 0x2e
|
||||
return index;
|
||||
if (offset == 1)
|
||||
{
|
||||
// data port 0x2f
|
||||
if (index < 0x30)
|
||||
return registers[0][index];
|
||||
return registers[selected][index];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(xbox_superio_device::write)
|
||||
{
|
||||
if (configuration_mode == false)
|
||||
{
|
||||
// config port 0x2e
|
||||
if ((offset == 0) && (data == 0x55))
|
||||
configuration_mode = true;
|
||||
return;
|
||||
}
|
||||
if ((offset == 0) && (data == 0xaa))
|
||||
{
|
||||
// config port 0x2e
|
||||
configuration_mode = false;
|
||||
return;
|
||||
}
|
||||
if (offset == 0)
|
||||
{
|
||||
// index port 0x2e
|
||||
index = data;
|
||||
}
|
||||
if (offset == 1)
|
||||
{
|
||||
// data port 0x2f
|
||||
if (index < 0x30)
|
||||
{
|
||||
registers[0][index] = data;
|
||||
selected = registers[0][7];
|
||||
}
|
||||
else
|
||||
{
|
||||
registers[selected][index] = data;
|
||||
//if ((superiost.selected == 4) && (superiost.index == 0x30) && (data != 0))
|
||||
// ; // add handlers 0x3f8- +7
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(xbox_superio_device::read_rs232)
|
||||
{
|
||||
if (offset == 5)
|
||||
return 0x20;
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(xbox_superio_device::write_rs232)
|
||||
{
|
||||
if (offset == 0)
|
||||
{
|
||||
printf("%c", data);
|
||||
}
|
||||
}
|
||||
|
||||
void xbox_base_state::machine_start()
|
||||
{
|
||||
find_debug_params();
|
||||
@ -798,19 +835,15 @@ void xbox_base_state::machine_start()
|
||||
hack_usb();
|
||||
}
|
||||
);
|
||||
// super-io
|
||||
memset(&superiost, 0, sizeof(superiost));
|
||||
superiost.configuration_mode = false;
|
||||
superiost.registers[0][0x26] = 0x2e; // Configuration port address byte 0
|
||||
// savestates
|
||||
save_item(NAME(debug_irq_active));
|
||||
save_item(NAME(debug_irq_number));
|
||||
}
|
||||
|
||||
#if 0
|
||||
void xbox_base_state::xbox_base_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0x07ffffff).ram(); // 128 megabytes
|
||||
#if 0
|
||||
map(0xf0000000, 0xf7ffffff).ram().share("nv2a_share"); // 3d accelerator wants this
|
||||
map(0xfd000000, 0xfdffffff).ram().rw(FUNC(xbox_base_state::geforce_r), FUNC(xbox_base_state::geforce_w));
|
||||
map(0xfed00000, 0xfed003ff).rw(FUNC(xbox_base_state::ohci_usb_r), FUNC(xbox_base_state::ohci_usb_w));
|
||||
@ -818,15 +851,13 @@ void xbox_base_state::xbox_base_map(address_map &map)
|
||||
map(0xfe800000, 0xfe87ffff).rw(FUNC(xbox_base_state::audio_apu_r), FUNC(xbox_base_state::audio_apu_w));
|
||||
map(0xfec00000, 0xfec00fff).rw(FUNC(xbox_base_state::audio_ac93_r), FUNC(xbox_base_state::audio_ac93_w));
|
||||
map(0xfef00000, 0xfef003ff).rw(FUNC(xbox_base_state::network_r), FUNC(xbox_base_state::network_w));
|
||||
#endif
|
||||
}
|
||||
|
||||
void xbox_base_state::xbox_base_map_io(address_map &map)
|
||||
{
|
||||
map(0x01f0, 0x01f7).rw(":pci:09.0:ide1", FUNC(bus_master_ide_controller_device::cs0_r), FUNC(bus_master_ide_controller_device::cs0_w));
|
||||
map(0x002e, 0x002f).rw(FUNC(xbox_base_state::superio_read), FUNC(xbox_base_state::superio_write));
|
||||
map(0x01f0, 0x01f7).rw(":pci:09.0:ide", FUNC(bus_master_ide_controller_device::cs0_r), FUNC(bus_master_ide_controller_device::cs0_w));
|
||||
map(0x03f8, 0x03ff).rw(FUNC(xbox_base_state::superiors232_read), FUNC(xbox_base_state::superiors232_write));
|
||||
#if 0
|
||||
map(0x0cf8, 0x0cff).rw("pcibus", FUNC(pci_bus_legacy_device::read), FUNC(pci_bus_legacy_device::write));
|
||||
map(0x8000, 0x80ff).rw(FUNC(xbox_base_state::dummy_r), FUNC(xbox_base_state::dummy_w)); // lpc bridge
|
||||
map(0xc000, 0xc00f).rw(FUNC(xbox_base_state::smbus_r), FUNC(xbox_base_state::smbus_w));
|
||||
@ -835,23 +866,22 @@ void xbox_base_state::xbox_base_map_io(address_map &map)
|
||||
map(0xd200, 0xd27f).noprw(); // ac97
|
||||
map(0xe000, 0xe007).rw(FUNC(xbox_base_state::networkio_r), FUNC(xbox_base_state::networkio_w));
|
||||
map(0xff60, 0xff6f).rw("ide", FUNC(bus_master_ide_controller_device::bmdma_r), FUNC(bus_master_ide_controller_device::bmdma_w));
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
void xbox_base_state::xbox_base(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
PENTIUM3(config, m_maincpu, 733333333); /* Wrong! family 6 model 8 stepping 10 */
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &xbox_base_state::xbox_base_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &xbox_base_state::xbox_base_map_io);
|
||||
m_maincpu->set_irq_acknowledge_callback(FUNC(xbox_base_state::irq_callback));
|
||||
|
||||
config.m_minimum_quantum = attotime::from_hz(6000);
|
||||
|
||||
PCI_ROOT(config, ":pci", 0);
|
||||
NV2A_HOST(config, ":pci:00.0", 0, m_maincpu);
|
||||
NV2A_RAM(config, ":pci:00.3", 0);
|
||||
NV2A_RAM(config, ":pci:00.3", 0, 128); // 128 megabytes
|
||||
MCPX_ISALPC(config, ":pci:01.0", 0, 0).interrupt_output().set(FUNC(xbox_base_state::maincpu_interrupt));
|
||||
XBOX_SUPERIO(config, ":pci:01.0:0", 0);
|
||||
MCPX_SMBUS(config, ":pci:01.1", 0).interrupt_handler().set(FUNC(xbox_base_state::smbus_interrupt_changed));
|
||||
XBOX_PIC16LC(config, ":pci:01.1:110", 0); // these 3 are on smbus number 1
|
||||
XBOX_CX25871(config, ":pci:01.1:145", 0);
|
||||
@ -863,7 +893,7 @@ void xbox_base_state::xbox_base(machine_config &config)
|
||||
MCPX_AC97_AUDIO(config, ":pci:06.0", 0);
|
||||
MCPX_AC97_MODEM(config, ":pci:06.1", 0);
|
||||
PCI_BRIDGE(config, ":pci:08.0", 0, 0x10de01b8, 0);
|
||||
MCPX_IDE(config, ":pci:09.0", 0).interrupt_handler().set(FUNC(xbox_base_state::ide_interrupt_changed));
|
||||
MCPX_IDE(config, ":pci:09.0", 0).pri_interrupt_handler().set(FUNC(xbox_base_state::ide_interrupt_changed));
|
||||
NV2A_AGP(config, ":pci:1e.0", 0, 0x10de01b7, 0);
|
||||
NV2A_GPU(config, ":pci:1e.0:00.0", 0, m_maincpu).interrupt_handler().set(FUNC(xbox_base_state::nv2a_interrupt_changed));
|
||||
|
||||
|
||||
@ -69,6 +69,12 @@ nv2a_ram_device::nv2a_ram_device(const machine_config &mconfig, const char *tag,
|
||||
set_ids(0x10de02a6, 0, 0, 0);
|
||||
}
|
||||
|
||||
void nv2a_ram_device::device_start()
|
||||
{
|
||||
pci_device::device_start();
|
||||
ram.resize(ram_size * 1024 * 1024 / 4);
|
||||
}
|
||||
|
||||
READ32_MEMBER(nv2a_ram_device::config_register_r)
|
||||
{
|
||||
return 0x08800044;
|
||||
@ -78,6 +84,12 @@ WRITE32_MEMBER(nv2a_ram_device::config_register_w)
|
||||
{
|
||||
}
|
||||
|
||||
void nv2a_ram_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
|
||||
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
|
||||
{
|
||||
memory_space->install_ram(0x00000000, ram_size * 1024 * 1024 - 1, &ram[0]);
|
||||
}
|
||||
|
||||
/*
|
||||
* LPC Bus
|
||||
*/
|
||||
@ -121,6 +133,12 @@ mcpx_isalpc_device::mcpx_isalpc_device(const machine_config &mconfig, const char
|
||||
pic8259_1(*this, "pic8259_1"),
|
||||
pic8259_2(*this, "pic8259_2"),
|
||||
pit8254(*this, "pit8254"),
|
||||
m_pm1_status(0),
|
||||
m_pm1_enable(0),
|
||||
m_pm1_control(0),
|
||||
m_pm1_timer(0),
|
||||
m_gpe0_status(0),
|
||||
m_gpe0_enable(0),
|
||||
m_global_smi_control(0),
|
||||
m_smi_command_port(0)
|
||||
{
|
||||
@ -129,11 +147,15 @@ mcpx_isalpc_device::mcpx_isalpc_device(const machine_config &mconfig, const char
|
||||
void mcpx_isalpc_device::device_start()
|
||||
{
|
||||
pci_device::device_start();
|
||||
set_multifunction_device(true);
|
||||
m_smi_callback.resolve_safe();
|
||||
m_interrupt_output.resolve_safe();
|
||||
m_boot_state_hook.resolve_safe();
|
||||
add_map(0x00000100, M_IO, FUNC(mcpx_isalpc_device::lpc_io));
|
||||
bank_infos[0].adr = 0x8000;
|
||||
status = 0x00b0;
|
||||
command = 0x0081;
|
||||
command_mask = 0x01be;
|
||||
for (int a = 0; a < 16; a++)
|
||||
lpcdevices[a] = nullptr;
|
||||
for (device_t &d : subdevices())
|
||||
@ -203,7 +225,7 @@ void mcpx_isalpc_device::update_smi_line()
|
||||
|
||||
READ32_MEMBER(mcpx_isalpc_device::acpi_r)
|
||||
{
|
||||
logerror("Acpi read from %04X mask %08X\n", bank_infos[0].adr + offset * 4, mem_mask);
|
||||
logerror("Acpi read from %04X mask %08X\n", (bank_infos[0].adr & 0xfffffffe) + offset * 4, mem_mask);
|
||||
if ((offset == 0xa) && ACCESSING_BITS_0_15)
|
||||
return m_global_smi_control;
|
||||
if ((offset == 0xb) && ACCESSING_BITS_16_23)
|
||||
@ -213,15 +235,35 @@ READ32_MEMBER(mcpx_isalpc_device::acpi_r)
|
||||
|
||||
WRITE32_MEMBER(mcpx_isalpc_device::acpi_w)
|
||||
{
|
||||
// Seen using word registers at the following offsets
|
||||
logerror("Acpi write %08X to %04X mask %08X\n", data, (bank_infos[0].adr & 0xfffffffe) + offset * 4, mem_mask);
|
||||
// Seen using word registers at offsets
|
||||
// 0x00 0x02 0x04 0x08 0x20 0x22 0x28 0xa0 0xa2 0xc0-0xd8
|
||||
if ((offset == 0xa) && ACCESSING_BITS_0_15)
|
||||
// Byte access at 0x2e
|
||||
if ((offset == 0) && ACCESSING_BITS_0_15)
|
||||
// pm1 status register
|
||||
m_pm1_status = data & 0xffff;
|
||||
else if ((offset == 0) && ACCESSING_BITS_16_31)
|
||||
// pm1 enable register
|
||||
m_pm1_enable = data >> 16;
|
||||
else if ((offset == 1) && ACCESSING_BITS_0_15)
|
||||
// pm1 control register
|
||||
m_pm1_control = data & 0xffff;
|
||||
else if ((offset == 2) && ACCESSING_BITS_0_15)
|
||||
// pm1 timer register
|
||||
m_pm1_timer = data & 0xffff;
|
||||
else if ((offset == 8) && ACCESSING_BITS_0_15)
|
||||
// gpe0 status register
|
||||
m_gpe0_status = data & 0xffff;
|
||||
else if ((offset == 8) && ACCESSING_BITS_16_31)
|
||||
// gpe0 enable register
|
||||
m_gpe0_enable = data >> 16;
|
||||
else if ((offset == 0xa) && ACCESSING_BITS_0_15)
|
||||
{
|
||||
// Global SMI Control
|
||||
m_global_smi_control = m_global_smi_control & (~data & 0xffff);
|
||||
update_smi_line();
|
||||
}
|
||||
if ((offset == 0xb) && ACCESSING_BITS_16_23)
|
||||
else if ((offset == 0xb) && ACCESSING_BITS_16_23)
|
||||
{
|
||||
// SMI Command Port
|
||||
// write to byte 0x2e must generate a SMI interrupt
|
||||
@ -230,7 +272,8 @@ WRITE32_MEMBER(mcpx_isalpc_device::acpi_w)
|
||||
update_smi_line();
|
||||
logerror("Generate software SMI with value %02X\n", m_smi_command_port);
|
||||
}
|
||||
logerror("Acpi write %08X to %04X mask %08X\n", data, bank_infos[0].adr + offset * 4, mem_mask);
|
||||
else
|
||||
logerror("Acpi write not recognized\n");
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(mcpx_isalpc_device::boot_state_w)
|
||||
@ -384,6 +427,7 @@ mcpx_smbus_device::mcpx_smbus_device(const machine_config &mconfig, const char *
|
||||
void mcpx_smbus_device::device_start()
|
||||
{
|
||||
pci_device::device_start();
|
||||
set_multifunction_device(true);
|
||||
m_interrupt_handler.resolve_safe();
|
||||
add_map(0x00000010, M_IO, FUNC(mcpx_smbus_device::smbus_io0));
|
||||
bank_infos[0].adr = 0x1000;
|
||||
@ -391,6 +435,7 @@ void mcpx_smbus_device::device_start()
|
||||
bank_infos[1].adr = 0xc000;
|
||||
add_map(0x00000020, M_IO, FUNC(mcpx_smbus_device::smbus_io2));
|
||||
bank_infos[2].adr = 0xc200;
|
||||
status = 0x00b0;
|
||||
memset(&smbusst, 0, sizeof(smbusst));
|
||||
for (int b = 0; b < 2; b++)
|
||||
for (int a = 0; a < 128; a++)
|
||||
@ -547,6 +592,7 @@ void mcpx_ohci_device::device_start()
|
||||
m_interrupt_handler.resolve_safe();
|
||||
add_map(0x00001000, M_MEM, FUNC(mcpx_ohci_device::ohci_mmio));
|
||||
bank_infos[0].adr = 0xfed00000;
|
||||
status = 0x00b0;
|
||||
ohci_usb = new ohci_usb_controller();
|
||||
ohci_usb->set_cpu(maincpu.target());
|
||||
ohci_usb->set_irq_callbaclk(
|
||||
@ -689,6 +735,7 @@ void mcpx_apu_device::device_start()
|
||||
pci_device::device_start();
|
||||
add_map(0x00080000, M_MEM, FUNC(mcpx_apu_device::apu_mmio));
|
||||
bank_infos[0].adr = 0xfe800000;
|
||||
status = 0x00b0;
|
||||
memset(apust.memory, 0, sizeof(apust.memory));
|
||||
memset(apust.voices_heap_blockaddr, 0, sizeof(apust.voices_heap_blockaddr));
|
||||
memset(apust.voices_active, 0, sizeof(apust.voices_active));
|
||||
@ -884,12 +931,14 @@ mcpx_ac97_audio_device::mcpx_ac97_audio_device(const machine_config &mconfig, co
|
||||
void mcpx_ac97_audio_device::device_start()
|
||||
{
|
||||
pci_device::device_start();
|
||||
set_multifunction_device(true);
|
||||
add_map(0x00000100, M_IO, FUNC(mcpx_ac97_audio_device::ac97_io0));
|
||||
bank_infos[0].adr = 0xd000;
|
||||
add_map(0x00000080, M_IO, FUNC(mcpx_ac97_audio_device::ac97_io1));
|
||||
bank_infos[1].adr = 0xd200;
|
||||
add_map(0x00001000, M_MEM, FUNC(mcpx_ac97_audio_device::ac97_mmio));
|
||||
bank_infos[2].adr = 0xfec00000;
|
||||
status = 0x00b0;
|
||||
memset(&ac97st, 0, sizeof(ac97st));
|
||||
}
|
||||
|
||||
@ -981,24 +1030,56 @@ mcpx_ac97_modem_device::mcpx_ac97_modem_device(const machine_config &mconfig, co
|
||||
|
||||
DEFINE_DEVICE_TYPE(MCPX_IDE, mcpx_ide_device, "mcpx_ide", "MCPX IDE Controller")
|
||||
|
||||
void mcpx_ide_device::mcpx_ide_io(address_map &map)
|
||||
void mcpx_ide_device::config_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x000f).rw("ide", FUNC(bus_master_ide_controller_device::bmdma_r), FUNC(bus_master_ide_controller_device::bmdma_w));
|
||||
pci_device::config_map(map);
|
||||
map(0x08, 0x0b).rw(FUNC(pci_device::class_rev_r), FUNC(mcpx_ide_device::class_rev_w));
|
||||
}
|
||||
|
||||
void mcpx_ide_device::ide_pri_command(address_map &map)
|
||||
{
|
||||
map(0, 7).rw("ide1", FUNC(bus_master_ide_controller_device::cs0_r), FUNC(bus_master_ide_controller_device::cs0_w));
|
||||
}
|
||||
|
||||
void mcpx_ide_device::ide_pri_control(address_map &map)
|
||||
{
|
||||
}
|
||||
|
||||
void mcpx_ide_device::ide_sec_command(address_map &map)
|
||||
{
|
||||
map(0, 7).rw("ide2", FUNC(bus_master_ide_controller_device::cs0_r), FUNC(bus_master_ide_controller_device::cs0_w));
|
||||
}
|
||||
|
||||
void mcpx_ide_device::ide_sec_control(address_map &map)
|
||||
{
|
||||
}
|
||||
|
||||
void mcpx_ide_device::ide_io(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x0007).rw("ide1", FUNC(bus_master_ide_controller_device::bmdma_r), FUNC(bus_master_ide_controller_device::bmdma_w));
|
||||
map(0x0008, 0x000f).rw("ide2", FUNC(bus_master_ide_controller_device::bmdma_r), FUNC(bus_master_ide_controller_device::bmdma_w));
|
||||
}
|
||||
|
||||
mcpx_ide_device::mcpx_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
|
||||
: pci_device(mconfig, MCPX_IDE, tag, owner, clock),
|
||||
m_interrupt_handler(*this)
|
||||
m_pri_interrupt_handler(*this),
|
||||
m_sec_interrupt_handler(*this)
|
||||
{
|
||||
set_ids(0x10de01bc, 0, 0, 0);
|
||||
set_ids(0x10de01bc, 0, 0x01018a, 0);
|
||||
}
|
||||
|
||||
void mcpx_ide_device::device_start()
|
||||
{
|
||||
pci_device::device_start();
|
||||
add_map(0x00000010, M_IO, FUNC(mcpx_ide_device::mcpx_ide_io));
|
||||
bank_infos[0].adr = 0xff60;
|
||||
m_interrupt_handler.resolve_safe();
|
||||
add_map(0x00000008, M_IO | M_DISABLED, FUNC(mcpx_ide_device::ide_pri_command)); // primary command block
|
||||
add_map(0x00000004, M_IO | M_DISABLED, FUNC(mcpx_ide_device::ide_pri_control)); // primary control block
|
||||
add_map(0x00000008, M_IO | M_DISABLED, FUNC(mcpx_ide_device::ide_sec_command)); // secondary command block
|
||||
add_map(0x00000004, M_IO | M_DISABLED, FUNC(mcpx_ide_device::ide_sec_control)); // secondary control block
|
||||
add_map(0x00000010, M_IO, FUNC(mcpx_ide_device::ide_io));
|
||||
bank_infos[4].adr = 0xff60;
|
||||
status = 0x00b0;
|
||||
m_pri_interrupt_handler.resolve_safe();
|
||||
m_sec_interrupt_handler.resolve_safe();
|
||||
}
|
||||
|
||||
void mcpx_ide_device::device_reset()
|
||||
@ -1008,14 +1089,42 @@ void mcpx_ide_device::device_reset()
|
||||
|
||||
void mcpx_ide_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
bus_master_ide_controller_device &ide(BUS_MASTER_IDE_CONTROLLER(config, "ide", 0));
|
||||
ide.irq_handler().set(FUNC(mcpx_ide_device::ide_interrupt));
|
||||
ide.set_bus_master_space(":maincpu", AS_PROGRAM);
|
||||
bus_master_ide_controller_device &ide1(BUS_MASTER_IDE_CONTROLLER(config, "ide1", 0));
|
||||
ide1.irq_handler().set(FUNC(mcpx_ide_device::ide_pri_interrupt));
|
||||
ide1.set_bus_master_space(":maincpu", AS_PROGRAM);
|
||||
|
||||
bus_master_ide_controller_device &ide2(BUS_MASTER_IDE_CONTROLLER(config, "ide2", 0));
|
||||
ide2.irq_handler().set(FUNC(mcpx_ide_device::ide_sec_interrupt));
|
||||
ide2.set_bus_master_space(":maincpu", AS_PROGRAM);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(mcpx_ide_device::ide_interrupt)
|
||||
void mcpx_ide_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
|
||||
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
|
||||
{
|
||||
m_interrupt_handler(state);
|
||||
if (~pclass & 1)
|
||||
io_space->install_device(0x1f0, 0x1f7, *this, &mcpx_ide_device::ide_pri_command);
|
||||
/*if (~pclass & 4)
|
||||
io_space->install_device(0x3f0, 0x3f7, *this, &mcpx_ide_device::ide_sec_command);*/
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(mcpx_ide_device::class_rev_w)
|
||||
{
|
||||
if (ACCESSING_BITS_8_15)
|
||||
{
|
||||
// bit 0 specifies if the primary channel is in compatibility or native-pci mode
|
||||
// bit 2 specifies if the secondary channel is in compatibility or native-pci mode
|
||||
pclass = (pclass & 0xfffffffa) | ((data >> 8) & 5);
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(mcpx_ide_device::ide_pri_interrupt)
|
||||
{
|
||||
m_pri_interrupt_handler(state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(mcpx_ide_device::ide_sec_interrupt)
|
||||
{
|
||||
m_sec_interrupt_handler(state);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1088,6 +1197,7 @@ void nv2a_gpu_device::device_start()
|
||||
void nv2a_gpu_device::device_reset()
|
||||
{
|
||||
pci_device::device_reset();
|
||||
nvidia_nv2a->set_ram_base(m_program->get_read_ptr(0));
|
||||
}
|
||||
|
||||
READ32_MEMBER(nv2a_gpu_device::geforce_r)
|
||||
|
||||
@ -4852,10 +4852,14 @@ void nv2a_renderer::savestate_items()
|
||||
{
|
||||
}
|
||||
|
||||
void nv2a_renderer::set_ram_base(void *base)
|
||||
{
|
||||
basemempointer = (uint8_t*)base;
|
||||
topmempointer = basemempointer + 512 * 1024 * 1024 - 1;
|
||||
}
|
||||
|
||||
void nv2a_renderer::start(address_space *cpu_space)
|
||||
{
|
||||
basemempointer = (uint8_t *)cpu_space->get_read_ptr(0);
|
||||
topmempointer = basemempointer + 512 * 1024 * 1024 - 1;
|
||||
puller_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(nv2a_renderer::puller_timer_work), this), (void *)"NV2A Puller Timer");
|
||||
puller_timer->enable(false);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user