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GCC 4.6 "Variable assigned but not used" for 6502 family (no whatsnew)

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This commit is contained in:
R. Belmont 2011-05-30 03:50:06 +00:00
parent 601301fc95
commit da488dc93c
8 changed files with 68 additions and 60 deletions
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5
src/emu/cpu/m6502/ops02.h
View File

@ -257,13 +257,18 @@
RD_ZPI/WR_ZPI 5
*/
#define RD_IMM tmp = RDOPARG()
#define RD_IMM_DISCARD RDOPARG()
#define RD_DUM RDMEM(PCW)
#define RD_ACC tmp = A
#define RD_ZPG EA_ZPG; tmp = RDMEM(EAD)
#define RD_ZPG_DISCARD EA_ZPG; RDMEM(EAD)
#define RD_ZPX EA_ZPX; tmp = RDMEM(EAD)
#define RD_ZPX_DISCARD EA_ZPX; RDMEM(EAD)
#define RD_ZPY EA_ZPY; tmp = RDMEM(EAD)
#define RD_ABS EA_ABS; tmp = RDMEM(EAD)
#define RD_ABS_DISCARD EA_ABS; RDMEM(EAD)
#define RD_ABX_P EA_ABX_P; tmp = RDMEM(EAD)
#define RD_ABX_P_DISCARD EA_ABX_P; RDMEM(EAD);
#define RD_ABX_NP EA_ABX_NP; tmp = RDMEM(EAD)
#define RD_ABY_P EA_ABY_P; tmp = RDMEM(EAD)
#define RD_ABY_NP EA_ABY_NP; tmp = RDMEM(EAD)

1
src/emu/cpu/m6502/opsc02.h
View File

@ -127,6 +127,7 @@
*/
#define RD_ABX_C02_P EA_ABX_C02_P; tmp = RDMEM(EAD)
#define RD_ABX_C02_NP EA_ABX_C02_NP; tmp = RDMEM(EAD)
#define RD_ABX_C02_NP_DISCARD EA_ABX_C02_NP; RDMEM(EAD)
#define RD_ABY_C02_P EA_ABY_C02_P; tmp = RDMEM(EAD)
#define RD_IDY_C02_P EA_IDY_C02_P; tmp = RDMEM_ID(EAD); cpustate->icount -= 1

2
src/emu/cpu/m6502/opsce02.h
View File

@ -179,7 +179,9 @@
#define RD_IDX EA_IDX; tmp = RDMEM(EAD)
#define RD_IDY EA_IDY; tmp = RDMEM(EAD)
#define RD_IDZ EA_IDZ; tmp = RDMEM(EAD)
#define RD_IDZ_DISCARD EA_IDZ; RDMEM(EAD)
#define RD_INSY EA_INSY; tmp = RDMEM(EAD)
#define RD_INSY_DISCARD EA_INSY; RDMEM(EAD)
#define RD_ZPG EA_ZPG; tmp = RDMEM(EAD)
#define RD_ZPG_WORD EA_ZPG; RDMEM_WORD(EAD, tmp)
#define RD_ZPX EA_ZPX; tmp = RDMEM(EAD)

42
src/emu/cpu/m6502/t6502.c
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@ -37,7 +37,7 @@ OP(00) { BRK; } /* 7 BRK */
OP(20) { JSR; } /* 6 JSR */
OP(40) { RTI; } /* 6 RTI */
OP(60) { RTS; } /* 6 RTS */
OP(80) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(80) { RDOPARG(); NOP; } /* 2 NOP IMM */
OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */
OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */
OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */
@ -73,10 +73,10 @@ OP(02) { KIL; } /* 1 KIL */
OP(22) { KIL; } /* 1 KIL */
OP(42) { KIL; } /* 1 KIL */
OP(62) { KIL; } /* 1 KIL */
OP(82) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(82) { RDOPARG(); NOP; } /* 2 NOP IMM */
OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */
OP(c2) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(e2) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(c2) { RDOPARG(); NOP; } /* 2 NOP IMM */
OP(e2) { RDOPARG(); NOP; } /* 2 NOP IMM */
OP(12) { KIL; } /* 1 KIL */
OP(32) { KIL; } /* 1 KIL */
@ -105,23 +105,23 @@ OP(b3) { int tmp; RD_IDY_P; LAX; } /* 5 LAX IDY page penalty */
OP(d3) { int tmp; RD_IDY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP IDY */
OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB IDY */
OP(04) { int tmp; RD_ZPG; NOP; } /* 3 NOP ZPG */
OP(04) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */
OP(44) { int tmp; RD_ZPG; NOP; } /* 3 NOP ZPG */
OP(64) { int tmp; RD_ZPG; NOP; } /* 3 NOP ZPG */
OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
OP(64) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */
OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */
OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */
OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */
OP(14) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(34) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(54) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(74) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(14) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(34) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(74) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */
OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */
OP(d4) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(f4) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */
OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */
@ -199,7 +199,7 @@ OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */
OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */
OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */
OP(69) { int tmp; RD_IMM; ADC; } /* 2 ADC IMM */
OP(89) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(89) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */
OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */
OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */
OP(e9) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */
@ -249,7 +249,7 @@ OP(bb) { int tmp; RD_ABY_P; AST; } /* 4 AST ABY page penalty */
OP(db) { int tmp; RD_ABY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABY */
OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABY */
OP(0c) { int tmp; RD_ABS; NOP; } /* 4 NOP ABS */
OP(0c) { RD_ABS_DISCARD; NOP; } /* 4 NOP ABS */
OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */
OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */
OP(6c) { int tmp; EA_IND; JMP; } /* 5 JMP IND */
@ -258,14 +258,14 @@ OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */
OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */
OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */
OP(1c) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(3c) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(5c) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(7c) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(1c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(3c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(5c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(7c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(9c) { int tmp; EA_ABX_NP; SYH; WB_EA; } /* 5 SYH ABX */
OP(bc) { int tmp; RD_ABX_P; LDY; } /* 4 LDY ABX page penalty */
OP(dc) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(fc) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(dc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(fc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */
OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */

42
src/emu/cpu/m6502/t6509.c
View File

@ -30,7 +30,7 @@ OP(00) { BRK; } /* 7 BRK */
OP(20) { JSR; } /* 6 JSR */
OP(40) { RTI; } /* 6 RTI */
OP(60) { RTS; } /* 6 RTS */
OP(80) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(80) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */
OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */
OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */
OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */
@ -66,10 +66,10 @@ OP(02) { KIL; } /* 1 KIL */
OP(22) { KIL; } /* 1 KIL */
OP(42) { KIL; } /* 1 KIL */
OP(62) { KIL; } /* 1 KIL */
OP(82) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(82) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */
OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */
OP(c2) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(e2) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(c2) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */
OP(e2) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */
OP(12) { KIL; } /* 1 KIL */
OP(32) { KIL; } /* 1 KIL */
@ -98,23 +98,23 @@ OP(b3) { int tmp; RD_IDY_P; LAX; } /* 5 LAX IDY page penalty */
OP(d3) { int tmp; RD_IDY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP IDY */
OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB IDY */
OP(04) { int tmp; RD_ZPG; NOP; } /* 3 NOP ZPG */
OP(04) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */
OP(44) { int tmp; RD_ZPG; NOP; } /* 3 NOP ZPG */
OP(64) { int tmp; RD_ZPG; NOP; } /* 3 NOP ZPG */
OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
OP(64) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */
OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */
OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */
OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */
OP(14) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(34) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(54) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(74) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(14) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(34) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(74) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */
OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */
OP(d4) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(f4) { int tmp; RD_ZPX; NOP; } /* 4 NOP ZPX */
OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */
OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */
@ -192,7 +192,7 @@ OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */
OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */
OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */
OP(69) { int tmp; RD_IMM; ADC; } /* 2 ADC IMM */
OP(89) { int tmp; RD_IMM; NOP; } /* 2 NOP IMM */
OP(89) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */
OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */
OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */
OP(e9) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */
@ -242,7 +242,7 @@ OP(bb) { int tmp; RD_ABY_P; AST; } /* 4 AST ABY page penalty */
OP(db) { int tmp; RD_ABY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABY */
OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABY */
OP(0c) { int tmp; RD_ABS; NOP; } /* 4 NOP ABS */
OP(0c) { RD_ABS_DISCARD; NOP; } /* 4 NOP ABS */
OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */
OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */
OP(6c) { int tmp; EA_IND; JMP; } /* 5 JMP IND */
@ -251,14 +251,14 @@ OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */
OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */
OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */
OP(1c) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(3c) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(5c) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(7c) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(1c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(3c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(5c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(7c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(9c) { int tmp; EA_ABX_NP; SYH; WB_EA; } /* 5 SYH ABX */
OP(bc) { int tmp; RD_ABX_P; LDY; } /* 4 LDY ABX page penalty */
OP(dc) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(fc) { int tmp; RD_ABX_P; NOP; } /* 4 NOP ABX page penalty */
OP(dc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(fc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */
OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */

28
src/emu/cpu/m6502/t65c02.c
View File

@ -74,14 +74,14 @@ OP(b1) { int tmp; RD_IDY_C02_P; LDA; } /* 5 LDA IDY page penalty
OP(d1) { int tmp; RD_IDY_C02_P; CMP; } /* 5 CMP IDY page penalty */
OP(f1) { int tmp; RD_IDY_C02_P; SBC_C02; } /* 5/6 SBC IDY page penalty */
OP(02) { int tmp; RD_IMM; NOP; } /* 2 NOP not sure for rockwell */
OP(22) { int tmp; RD_IMM; NOP; } /* 2 NOP not sure for rockwell */
OP(42) { int tmp; RD_IMM; NOP; } /* 2 NOP not sure for rockwell */
OP(62) { int tmp; RD_IMM; NOP; } /* 2 NOP not sure for rockwell */
OP(82) { int tmp; RD_IMM; NOP; } /* 2 NOP not sure for rockwell */
OP(02) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(22) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(42) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(62) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(82) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */
OP(c2) { int tmp; RD_IMM; NOP; } /* 2 NOP not sure for rockwell */
OP(e2) { int tmp; RD_IMM; NOP; } /* 2 NOP not sure for rockwell */
OP(c2) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(e2) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(12) { int tmp; RD_ZPI; ORA; } /* 5 ORA ZPI */
OP(32) { int tmp; RD_ZPI; AND; } /* 5 AND ZPI */
@ -112,7 +112,7 @@ OP(f3) { NOP; } /* 1 NOP not sure for rock
OP(04) { int tmp; RD_ZPG; RD_EA; TSB; WB_EA; } /* 5 TSB ZPG */
OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */
OP(44) { int tmp; RD_ZPG; NOP; } /* 3 NOP not sure for rockwell */
OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP not sure for rockwell */
OP(64) { int tmp; STZ; WR_ZPG; } /* 3 STZ ZPG */
OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */
OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */
@ -121,12 +121,12 @@ OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */
OP(14) { int tmp; RD_ZPG; RD_EA; TRB; WB_EA; } /* 5 TRB ZPG */
OP(34) { int tmp; RD_ZPX; BIT; } /* 4 BIT ZPX */
OP(54) { int tmp; RD_ZPX; NOP; } /* 4 NOP not sure for rockwell */
OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */
OP(74) { int tmp; STZ; WR_ZPX; } /* 4 STZ ZPX */
OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */
OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */
OP(d4) { int tmp; RD_ZPX; NOP; } /* 4 NOP not sure for rockwell */
OP(f4) { int tmp; RD_ZPX; NOP; } /* 4 NOP not sure for rockwell */
OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */
OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */
OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */
OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */
@ -265,12 +265,12 @@ OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */
OP(1c) { int tmp; RD_ABS; RD_EA; TRB; WB_EA; } /* 6 TRB ABS */
OP(3c) { int tmp; RD_ABX_C02_P; BIT; } /* 4 BIT ABX page penalty */
OP(5c) { int tmp; RD_ABX_C02_NP; RD_DUM; RD_DUM; RD_DUM; RD_DUM; } /* 8 NOP ABX not sure for rockwell. Page penalty not sure */
OP(5c) { RD_ABX_C02_NP_DISCARD; RD_DUM; RD_DUM; RD_DUM; RD_DUM; } /* 8 NOP ABX not sure for rockwell. Page penalty not sure */
OP(7c) { int tmp; EA_IAX; JMP; } /* 6 JMP IAX page penalty */
OP(9c) { int tmp; STZ; WR_ABS; } /* 4 STZ ABS */
OP(bc) { int tmp; RD_ABX_C02_P; LDY; } /* 4 LDY ABX page penalty */
OP(dc) { int tmp; RD_ABX_C02_NP; NOP; } /* 4 NOP ABX not sure for rockwell. Page penalty not sure */
OP(fc) { int tmp; RD_ABX_C02_NP; NOP; } /* 4 NOP ABX not sure for rockwell. Page penalty not sure */
OP(dc) { RD_ABX_C02_NP_DISCARD; NOP; } /* 4 NOP ABX not sure for rockwell. Page penalty not sure */
OP(fc) { RD_ABX_C02_NP_DISCARD; NOP; } /* 4 NOP ABX not sure for rockwell. Page penalty not sure */
OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */
OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */

4
src/emu/cpu/m6502/t65ce02.c
View File

@ -73,7 +73,7 @@ OP(02) { RD_DUM; CLE; } /* 2 CLE */
OP(22) { JSR_IND; } /* 7 JSR IND */
OP(42) { RD_DUM; NEG; } /* 2 NEG */
OP(62) { int tmp; RD_IMM; RTN; } /* 7 RTN IMM */
OP(82) { int tmp; RD_INSY; STA; } /* 6 STA INSY */
OP(82) { RD_INSY_DISCARD; } /* 6 STA INSY */
OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */
OP(c2) { int tmp; RD_IMM; CPZ; } /* 2 CPZ IMM */
OP(e2) { int tmp; RD_INSY; LDA; } /* 6 LDA INSY */
@ -82,7 +82,7 @@ OP(12) { int tmp; RD_IDZ; ORA; } /* 5 ORA IDZ */
OP(32) { int tmp; RD_IDZ; AND; } /* 5 AND IDZ */
OP(52) { int tmp; RD_IDZ; EOR; } /* 5 EOR IDZ */
OP(72) { int tmp; RD_IDZ; ADC; } /* 5 ADC IDZ */
OP(92) { int tmp; RD_IDZ; STA; } /* 5 STA IDZ */
OP(92) { RD_IDZ_DISCARD; } /* 5 STA IDZ */
OP(b2) { int tmp; RD_IDZ; LDA; } /* 5 LDA IDZ */
OP(d2) { int tmp; RD_IDZ; CMP; } /* 5 CMP IDZ */
OP(f2) { int tmp; RD_IDZ; SBC; } /* 5 SBC IDZ */

4
src/emu/cpu/m6502/tdeco16.c
View File

@ -187,7 +187,7 @@ OP(07) { RD_DUM; ILL; } /* 2 ILL / 5 RMB0 ZPG ?? */
OP(27) { RD_DUM; ILL; } /* 2 ILL / 5 RMB2 ZPG ?? */
OP(47) { RD_DUM; ILL; } /* 2 ILL / 5 RMB4 ZPG ?? */
OP(67) {
int tmp; RD_IMM;
RD_IMM_DISCARD;
cpustate->a=cpustate->io->read_byte(0);
// logerror("%04x: VBL (0x67)\n",PCW);
@ -271,7 +271,7 @@ OP(0b) { int tmp; cpustate->icount -= 1; RD_IMM;
}
OP(2b) { RD_DUM; ILL; } /* 2 ILL */
OP(4b) { int tmp; cpustate->icount -= 1; RD_IMM;
OP(4b) { cpustate->icount -= 1; RD_IMM_DISCARD;
//logerror("%04x: OP4B %02x\n",PCW,tmp);
/* TODO: Maybe it's just read I/O 0 and do a logic AND with bit 1? */
cpustate->a=cpustate->io->read_byte(1);