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Merge pull request #1832 from JoakimLarsson/sccintfix
Fixed a regression fifo bug and a bug in the handling of Special Condition Int
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commit
da524ca521
@ -1772,17 +1772,19 @@ void z80scc_channel::do_sccreg_wr1(uint8_t data)
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break;
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case WR1_RX_INT_FIRST:
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LOG(("- Receiver Interrupt on First Character\n"));
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break;
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case WR1_RX_INT_ALL_PARITY:
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LOG(("- Receiver Interrupt on All Characters, Parity Affects Vector\n"));
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LOG(("- Receiver Interrupt on First Character or Special Conditions\n"));
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break;
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case WR1_RX_INT_ALL:
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LOG(("- Receiver Interrupt on All Characters\n"));
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LOG(("- Receiver Interrupt on All Characters or Special Conditions\n"));
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break;
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case WR1_RX_INT_PARITY:
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LOG(("- Receiver Interrupt on Special Conditions only\n"));
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break;
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}
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if ((data & WR1_RX_INT_MODE_MASK) == WR1_PARITY_IS_SPEC_COND)
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LOG(("- Parity error is a Special Condition\n"));
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m_uart->check_interrupts();
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}
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@ -2266,13 +2268,13 @@ uint8_t z80scc_channel::data_read()
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received into the other bytes of the Receive FIFO.*/
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// load data from the FIFO
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data = m_rx_fifo_rp_data();
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data = m_rx_data_fifo[m_rx_fifo_rp];
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// load error status from the FIFO
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m_rr1 = (m_rr1 & ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) | m_rx_error_fifo[m_rx_fifo_rp];
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// trigger interrupt and lock the fifo if an error is present
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if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR))
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if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | ((m_wr1 & WR1_PARITY_IS_SPEC_COND) ? RR1_PARITY_ERROR : 0)))
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{
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logerror("Rx Error %02x\n", m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR));
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m_uart->trigger_interrupt(m_index, INT_SPECIAL);
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@ -2293,18 +2295,6 @@ uint8_t z80scc_channel::data_read()
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return data;
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}
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/* Get data from top of fifo data but restore read pointer in case of exit latch lock */
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uint8_t z80scc_channel::m_rx_fifo_rp_data()
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{
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uint8_t data;
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uint8_t old_rp = m_rx_fifo_rp;
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m_rx_fifo_rp_step();
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data = m_rx_data_fifo[m_rx_fifo_rp];
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m_rx_fifo_rp = old_rp;
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return data;
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}
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/* Step read pointer */
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void z80scc_channel::m_rx_fifo_rp_step()
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{
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@ -409,8 +409,8 @@ protected:
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WR1_RX_INT_MODE_MASK = 0x18,
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WR1_RX_INT_DISABLE = 0x00,
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WR1_RX_INT_FIRST = 0x08,
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WR1_RX_INT_ALL_PARITY = 0x10,
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WR1_RX_INT_ALL = 0x18,
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WR1_RX_INT_ALL = 0x10,
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WR1_RX_INT_PARITY = 0x18,
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WR1_WRDY_ON_RX_TX = 0x20,
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WR1_WRDY_FUNCTION = 0x40,
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WR1_WRDY_ENABLE = 0x80
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