mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
Update iteagle files
This commit is contained in:
U-demo\test
parent
6feb9ac5ca
commit
da682be221
@ -60,6 +60,7 @@ void vrc4373_device::device_start()
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m_simm_size = 1<<21;
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m_simm_base = 0;
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regenerate_config_mapping();
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}
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void vrc4373_device::device_reset()
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@ -120,6 +120,7 @@ private:
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UINT32 m_pci1_laddr, m_pci2_laddr, m_pci_io_laddr;
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UINT32 m_target1_laddr, m_target2_laddr;
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};
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@ -1,10 +1,12 @@
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#include "es1373.h"
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#define LOG_ES (1)
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#define LOG_ES (0)
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#define LOG_ES_REG (0)
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#define LOG_ES_FILE (0)
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static MACHINE_CONFIG_FRAGMENT( es1373 )
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MCFG_TIMER_DRIVER_ADD_PERIODIC("sound_timer", es1373_device, es_timer_callback, attotime::from_hz(44100/16384))
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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MACHINE_CONFIG_END
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machine_config_constructor es1373_device::device_mconfig_additions() const
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@ -20,6 +22,8 @@ ADDRESS_MAP_END
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es1373_device::es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: pci_device(mconfig, ES1373, "Creative Labs Ensoniq AudioPCI97 ES1373", tag, owner, clock, "es1373", __FILE__),
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device_sound_interface(mconfig, *this),
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m_eslog(NULL),
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m_irq_num(-1)
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{
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}
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@ -30,47 +34,72 @@ void es1373_device::set_irq_info(const char *tag, const int irq_num)
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m_irq_num = irq_num;
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}
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//-------------------------------------------------
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// device_stop - device-specific stop
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//-------------------------------------------------
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void es1373_device::device_stop()
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{
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/* debugging */
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if (LOG_ES_FILE && m_eslog)
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{
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fclose(m_eslog);
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m_eslog = NULL;
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}
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void es1373_device::device_start()
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{
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//m_cpu = machine().device<cpu_device>(":maincpu");
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m_cpu = machine().device<cpu_device>(m_cpu_tag);
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pci_device::device_start();
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add_map(0x40, M_IO, FUNC(es1373_device::map));
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// create the stream
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m_stream = machine().sound().stream_alloc(*this, 0, 2, 44100/2);
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m_timer = timer_alloc(0, NULL);
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m_timer->adjust(attotime::zero, 0, attotime::from_hz(44100/2/16));
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}
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void es1373_device::device_reset()
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{
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// debugging
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m_tempCount = 0;
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if (LOG_ES_FILE && m_eslog)
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{
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fclose(m_eslog);
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m_eslog = NULL;
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}
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if (LOG_ES_FILE && !m_eslog)
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m_eslog = fopen("es.log", "w");
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pci_device::device_reset();
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memset(m_es_regs, 0, sizeof(m_es_regs));
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memset(m_ac97_regs, 0, sizeof(m_ac97_regs));
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m_ac97_regs[0] = 0x0800;
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// Reset ADC channel info
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m_adc.number = 0;
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m_adc.enable = false;
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m_adc.int_en = false;
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m_adc.loop_en = false;
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m_adc.initialized = false;
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m_adc.buf_count = 0;
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m_adc.buf_size = 0;
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m_adc.buf_rptr = 0x20;
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m_adc.buf_wptr = 0x20;
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// Reset DAC1 channel info
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m_dac1.number = 1;
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m_dac1.enable = false;
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m_dac1.int_en = false;
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m_dac1.loop_en = false;
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m_dac1.initialized = false;
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m_dac1.buf_count = 0;
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m_dac1.buf_size = 0;
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m_dac1.buf_rptr = 0x0;
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m_dac1.buf_wptr = 0x0;
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// Reset DAC2 channel info
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m_dac2.number = 2;
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m_dac2.enable = false;
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m_dac2.int_en = false;
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m_dac2.loop_en = false;
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m_dac2.initialized = false;
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m_dac2.buf_count = 0;
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m_dac2.buf_size = 0;
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m_dac2.buf_rptr = 0x10;
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m_dac2.buf_wptr = 0x10;
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m_dac2.buf_wptr = 0x10; // Start PCI writing to bottom half of buffer
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m_stream->update();
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}
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void es1373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
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@ -79,68 +108,66 @@ void es1373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_e
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m_memory_space = memory_space;
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}
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TIMER_DEVICE_CALLBACK_MEMBER(es1373_device::es_timer_callback)
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//-------------------------------------------------
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// device_timer - called when our device timer expires
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//-------------------------------------------------
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void es1373_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
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{
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// Only transfer PCI data if bus mastering is enabled
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if (command & 0x4) {
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if (m_dac2.enable && (!(m_dac2.buf_rptr&0x7))) {
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transfer_pci_audio(m_dac2, ES_PCI_READ);
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}
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if (m_dac2.pci_count>8) {
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m_dac2.initialized = true;
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}
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m_stream->update();
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}
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//-------------------------------------------------
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// sound_stream_update - handle update requests for
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// our sound stream
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//-------------------------------------------------
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void es1373_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
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{
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if (m_dac1.enable) {
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logerror("%s: sound_stream_update DAC1 not implemented yet\n", tag());
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}
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if (m_dac2.enable) {
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// The initalized is to signal that inital buffer has been written
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if (m_dac2.buf_count<=m_dac2.buf_size && m_dac2.initialized) {
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// Send data to sound???
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// sound = m_sound_cache[chan.buf_rptr]
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if (0 && LOG_ES)
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logerror("%X: DAC2 buf_count: %i buf_size: %X buf_rptr: %X buf_wptr: %X\n", machine().device("maincpu")->safe_pc(),
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m_dac2.buf_count, m_dac2.buf_size, m_dac2.buf_rptr, m_dac2.buf_wptr);
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if (m_dac2.buf_count==m_dac2.buf_size) {
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if (m_dac2.int_en) {
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m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_DAC2_INT_MASK;
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if (LOG_ES)
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logerror("%X: es_timer_callback Setting DAC2 interrupt\n", machine().device("maincpu")->safe_pc());
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}
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if (m_dac2.loop_en) {
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// Keep playing
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m_dac2.buf_count = m_dac2.buf_count + 1 - 4; // Should check SCTRL_P2_END_MASK
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} else {
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// Stop
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//m_dac2.enable = false;
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}
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} else {
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m_dac2.buf_count++;
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}
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m_dac2.buf_rptr++;
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if (!(m_dac2.buf_rptr&0xf)) {
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m_dac2.buf_rptr -= 0x10;
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}
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}
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send_audio_out(m_dac2, ICSTATUS_DAC2_INT_MASK, outputs[0], outputs[1], samples);
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}
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if (m_adc.enable) {
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if (m_adc.buf_count<=m_adc.buf_size) {
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if (LOG_ES)
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logerror("%s: ADC buf_count: %i buf_size: %i buf_rptr: %i buf_wptr: %i\n", machine().describe_context(),
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m_adc.buf_count, m_adc.buf_size, m_adc.buf_rptr, m_adc.buf_wptr);
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if (m_adc.int_en && m_adc.buf_count==m_adc.buf_size) {
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m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_ADC_INT_MASK;
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if (LOG_ES)
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logerror("%s: es_timer_callback Setting ADC interrupt\n", tag());
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if (m_adc.format!=SCTRL_16BIT_MONO) {
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logerror("%s: sound_stream_update Only SCTRL_16BIT_MONO recorded supported\n", tag());
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} else {
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for (int i=0; i<samples; i++) {
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if (m_adc.buf_count<=m_adc.buf_size) {
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if (LOG_ES)
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logerror("%s: ADC buf_count: %i buf_size: %i buf_rptr: %i buf_wptr: %i\n", machine().describe_context(),
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m_adc.buf_count, m_adc.buf_size, m_adc.buf_rptr, m_adc.buf_wptr);
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if ((m_adc.buf_count&0x1)) {
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m_adc.buf_wptr++;
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}
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m_adc.buf_count++;
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if (m_adc.buf_count>m_adc.buf_size) {
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if (m_adc.loop_en) {
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// Keep playing
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m_adc.buf_count = 0;
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if (LOG_ES)
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logerror("%X: send_audio_out ADC clearing buf_count\n", machine().device("maincpu")->safe_pc());
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}
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if (m_adc.int_en) {
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m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_ADC_INT_MASK;
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if (LOG_ES)
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logerror("%X: send_audio_out Setting ADC interrupt\n", machine().device("maincpu")->safe_pc());
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}
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}
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if (!(m_adc.buf_count&1) && !(m_adc.buf_wptr&0xf)) {
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m_adc.buf_wptr -= 0x10;
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}
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// PCI Write Transfer
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if (command & 0x4) {
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if ((m_adc.buf_rptr&8)^(m_adc.buf_wptr&8)) {
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transfer_pci_audio(m_adc, ES_PCI_WRITE);
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}
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}
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}
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}
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m_adc.buf_count++;
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m_adc.buf_wptr++;
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if (!(m_adc.buf_wptr&0xf)) {
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m_adc.buf_wptr -= 0x10;
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}
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}
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}
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// PCI Write Transfer
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if (command & 0x4) {
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if (m_adc.enable && (!(m_adc.buf_wptr&0x7))) {
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transfer_pci_audio(m_adc, ES_PCI_WRITE);
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}
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}
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if (m_es_regs[ES_INT_CS_STATUS]&(ICSTATUS_DAC1_INT_MASK|ICSTATUS_DAC2_INT_MASK|ICSTATUS_ADC_INT_MASK)) {
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@ -153,37 +180,143 @@ TIMER_DEVICE_CALLBACK_MEMBER(es1373_device::es_timer_callback)
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}
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}
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//-------------------------------------------------
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// send_audio_out - Sends channel audio output data
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//-------------------------------------------------
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void es1373_device::send_audio_out(chan_info& chan, UINT32 intr_mask, stream_sample_t *outL, stream_sample_t *outR, int samples)
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{
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// Only transfer PCI data if bus mastering is enabled
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// Fill initial half buffer
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if (1 && (command & 0x4) && (!chan.initialized)) {
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chan.initialized = true;
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transfer_pci_audio(chan, ES_PCI_READ);
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}
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//UINT32 sample_size = calc_size(chan.format);
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// Send data to sound stream
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bool buf_row_done;
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for (int i=0; i<samples; i++) {
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buf_row_done = false;
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if (chan.buf_count<=chan.buf_size) {
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// Only transfer PCI data if bus mastering is enabled
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// Fill half-buffer when read pointer is at start of next half
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//if ((command & 0x4) && ((chan.buf_rptr&8)^(chan.buf_wptr&8)) && !(m_es_regs[ES_INT_CS_STATUS] & intr_mask)) {
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if ((command & 0x4) && ((chan.buf_rptr&8)^(chan.buf_wptr&8))) {
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transfer_pci_audio(chan, ES_PCI_READ);
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}
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if (LOG_ES && i==0)
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logerror("%X: chan: %X samples: %i buf_count: %X buf_size: %X buf_rptr: %X buf_wptr: %X\n",
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machine().device("maincpu")->safe_pc(), chan.number, samples, chan.buf_count, chan.buf_size, chan.buf_rptr, chan.buf_wptr);
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// Buffer is 4 bytes per location, need to switch on sample mode
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switch (chan.format) {
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case SCTRL_8BIT_MONO:
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logerror("es1373_device::send_audio_out SCTRL_8BIT_MONO not implemented yet\n");
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break;
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case SCTRL_8BIT_STEREO:
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logerror("es1373_device::send_audio_out SCTRL_8BIT_STEREO not implemented yet\n");
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break;
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case SCTRL_16BIT_MONO:
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// The sound cache is 32 bit wide fifo, so each entry is two mono 16 bit samples
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if ((chan.buf_count&0x1)) {
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// Read high 16 bits
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outL[i] = outR[i] = (INT16)(m_sound_cache[chan.buf_rptr]>>16);
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chan.buf_rptr++;
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buf_row_done = true;
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} else {
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// Read low 16 bits
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outL[i] = outR[i] = (INT16)(m_sound_cache[chan.buf_rptr]&0xffff);
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}
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break;
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case SCTRL_16BIT_STEREO:
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// The sound cache is 32 bit wide fifo, so each entry is one stereo 16 bit sample
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outL[i] = (INT16) m_sound_cache[chan.buf_rptr]&0xffff;
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outR[i] = (INT16) m_sound_cache[chan.buf_rptr]>>16;
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chan.buf_rptr++;
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buf_row_done = true;
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break;
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}
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if (LOG_ES_FILE && m_tempCount<1000000) {
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m_tempCount++;
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//logerror("es1373_device::sound_stream_update count: %i samp16: %X\n", i, samp16);
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//if (LOG_ES_FILE && m_eslog)
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//fprintf(m_eslog, "%i\n", samp16);
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}
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chan.buf_count++;
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if (chan.buf_count > chan.buf_size) {
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if (chan.loop_en) {
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// Keep playing
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//chan.buf_count -= 1; // Should check SCTRL_P2_END_MASK
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chan.buf_count = 0;
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//chan.buf_rptr -= 1;
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if (LOG_ES)
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logerror("%X: send_audio_out DAC2 clearing buf_count\n", machine().device("maincpu")->safe_pc());
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}
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if (chan.int_en) {
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m_es_regs[ES_INT_CS_STATUS] |= intr_mask;
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if (LOG_ES)
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logerror("%X: send_audio_out Setting DAC2 interrupt\n", machine().device("maincpu")->safe_pc());
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}
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}
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if (buf_row_done && !(chan.buf_rptr&0xf)) {
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chan.buf_rptr -= 0x10;
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}
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} else {
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// Send zeros?
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outL[i] = outR[i] = 0;
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}
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}
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}
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void es1373_device::transfer_pci_audio(chan_info& chan, int type)
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{
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UINT32 pci_addr, data;
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pci_addr = chan.pci_addr + (chan.pci_count<<2);
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if (type==ES_PCI_READ) {
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// Transfer from PCI to sound cache
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// Always transfer 8 longwords
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for (int i=0; i<8 && (chan.pci_count<=chan.pci_size); i++) {
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if (LOG_ES)
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logerror("%s: transfer_pci_audio start chan: %X pci_addr: %08X pci_count: %X pci_size: %X buf_rptr: %X buf_wptr: %X\n",
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machine().describe_context(), chan.number, pci_addr, chan.pci_count, chan.pci_size, chan.buf_rptr, chan.buf_wptr);
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// Always transfer 8 longwords
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for (int i=0; i<8; i++) {
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pci_addr = chan.pci_addr + (chan.pci_count<<2);
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if (type==ES_PCI_READ) {
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data = m_memory_space->read_dword(pci_addr, 0xffffffff);
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m_sound_cache[chan.buf_wptr++] = data;
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if (!(chan.buf_wptr&0xf)) {
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chan.buf_wptr -= 0x10;
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}
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chan.pci_count++;
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pci_addr += 4;
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}
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} else {
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// Transfer from sound cache to PCI
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// Always transfer 8 longwords
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for (int i=0; i<8 && chan.pci_count<=chan.pci_size; i++) {
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} else {
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data = m_sound_cache[chan.buf_rptr++];
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m_memory_space->write_dword(pci_addr, data);
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if (!(chan.buf_rptr&0xf)) {
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chan.buf_rptr -= 0x10;
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}
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}
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if (chan.pci_count==chan.pci_size) {
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chan.pci_count = 0;
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} else {
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chan.pci_count++;
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pci_addr += 4;
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}
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}
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}
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UINT32 es1373_device::calc_size(const UINT8 &format)
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{
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switch (format) {
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case SCTRL_8BIT_MONO:
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return 1;
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break;
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case SCTRL_8BIT_STEREO:
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return 2;
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break;
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case SCTRL_16BIT_MONO:
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return 2;
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break;
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case SCTRL_16BIT_STEREO:
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return 4;
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break;
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}
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logerror("%s: calc_size Invalid format = %X specified\n", tag(), format);
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return 0;
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}
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READ32_MEMBER (es1373_device::reg_r)
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{
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||||
UINT32 result = m_es_regs[offset];
|
||||
@ -281,6 +414,9 @@ WRITE32_MEMBER(es1373_device::reg_w)
|
||||
m_adc.int_en = m_es_regs[ES_SERIAL_CTRL] & SCTRL_R1_INT_EN_MASK;
|
||||
m_dac2.int_en = m_es_regs[ES_SERIAL_CTRL] & SCTRL_P2_INT_EN_MASK;
|
||||
m_dac1.int_en = m_es_regs[ES_SERIAL_CTRL] & SCTRL_P1_INT_EN_MASK;
|
||||
m_adc.format = (m_es_regs[ES_SERIAL_CTRL] & SCTRL_R1_S_MASK)>>4;
|
||||
m_dac2.format = (m_es_regs[ES_SERIAL_CTRL] & SCTRL_P2_S_MASK)>>2;
|
||||
m_dac1.format = (m_es_regs[ES_SERIAL_CTRL] & SCTRL_P1_S_MASK)>>0;
|
||||
if (!m_adc.int_en) m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_ADC_INT_MASK;
|
||||
if (!m_dac1.int_en) m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_DAC1_INT_MASK;
|
||||
if (!m_dac2.int_en) m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_DAC2_INT_MASK;
|
||||
@ -290,11 +426,11 @@ WRITE32_MEMBER(es1373_device::reg_w)
|
||||
if (m_es_regs[ES_INT_CS_STATUS]&ICSTATUS_INTR_MASK && m_irq_num!=-1) {
|
||||
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
|
||||
m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_INTR_MASK;
|
||||
if (LOG_ES)
|
||||
if (0 && LOG_ES_REG)
|
||||
logerror("%X: es1373_device::reg_w Clearing interrupt\n", machine().device("maincpu")->safe_pc());
|
||||
}
|
||||
}
|
||||
if (LOG_ES_REG)
|
||||
if (0 && LOG_ES_REG)
|
||||
logerror("%s: es1373_device::reg_w adc_int_en: %i dac1_int_en: %i dac2_int_en: %i\n", tag(), m_adc.int_en, m_dac1.int_en, m_dac2.int_en);
|
||||
break;
|
||||
case ES_DAC2_CNT:
|
||||
@ -345,6 +481,8 @@ WRITE32_MEMBER(es1373_device::reg_w)
|
||||
case 0xc:
|
||||
m_dac2.pci_count = (data>>16)&0xffff;
|
||||
m_dac2.pci_size = data&0xffff;
|
||||
if (LOG_ES_REG)
|
||||
logerror("%08X:ES1373 write to offset %02X = %08X & %08X\n", machine().device("maincpu")->safe_pc(), offset*4, data, mem_mask);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
// Creative Labs Ensonic AudioPCI97 ES1373
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef ES1373_H
|
||||
#define ES1373_H
|
||||
|
||||
@ -64,15 +66,21 @@
|
||||
#define SCTRL_P2_S_MASK 0x0000000C
|
||||
#define SCTRL_P1_S_MASK 0x00000003
|
||||
|
||||
#define SCTRL_8BIT_MONO 0x0
|
||||
#define SCTRL_8BIT_STEREO 0x1
|
||||
#define SCTRL_16BIT_MONO 0x2
|
||||
#define SCTRL_16BIT_STEREO 0x3
|
||||
|
||||
#define ES_PCI_READ 0
|
||||
#define ES_PCI_WRITE 1
|
||||
|
||||
struct chan_info {
|
||||
int number;
|
||||
bool enable;
|
||||
bool int_en;
|
||||
bool loop_en;
|
||||
bool initialized;
|
||||
UINT32 samp_size; // Size of one sample in log2(bytes)
|
||||
UINT8 format; // Format of channel
|
||||
UINT32 buf_wptr; // Address to sample cache memory
|
||||
UINT32 buf_rptr; // Address to sample cache memory
|
||||
UINT16 buf_count; // Number of samples that have been played
|
||||
@ -82,7 +90,8 @@ struct chan_info {
|
||||
UINT16 pci_size; // Total number of words (32 bits) minus one in system memory
|
||||
};
|
||||
|
||||
class es1373_device : public pci_device {
|
||||
class es1373_device : public pci_device, public device_sound_interface
|
||||
{
|
||||
public:
|
||||
es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
|
||||
@ -92,16 +101,26 @@ public:
|
||||
|
||||
DECLARE_READ32_MEMBER (reg_r);
|
||||
DECLARE_WRITE32_MEMBER(reg_w);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(es_timer_callback);
|
||||
|
||||
// optional information overrides
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
|
||||
// Sound stream
|
||||
sound_stream *m_stream;
|
||||
|
||||
protected:
|
||||
virtual void device_start();
|
||||
virtual void device_stop();
|
||||
virtual void device_reset();
|
||||
address_space *m_memory_space;
|
||||
//virtual const address_space_config *memory_space_config(address_spacenum spacenum) const;
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
|
||||
|
||||
FILE *m_eslog;
|
||||
|
||||
private:
|
||||
UINT32 m_tempCount;
|
||||
emu_timer *m_timer;
|
||||
address_space *m_memory_space;
|
||||
const char *m_cpu_tag;
|
||||
cpu_device *m_cpu;
|
||||
int m_irq_num;
|
||||
@ -114,6 +133,9 @@ private:
|
||||
chan_info m_dac2;
|
||||
chan_info m_adc;
|
||||
void transfer_pci_audio(chan_info& chan, int type);
|
||||
UINT32 calc_size(const UINT8 &format);
|
||||
void send_audio_out(chan_info& chan, UINT32 intr_mask, stream_sample_t *outL, stream_sample_t *outR, int samples);
|
||||
|
||||
};
|
||||
|
||||
extern const device_type ES1373;
|
||||
|
||||
@ -1,10 +1,9 @@
|
||||
#include "voodoo_pci.h"
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( voodoo_pci )
|
||||
MCFG_DEVICE_ADD("voodoo", VOODOO_BANSHEE, STD_VOODOO_BANSHEE_CLOCK)
|
||||
MCFG_DEVICE_ADD("voodoo", VOODOO_3, STD_VOODOO_3_CLOCK)
|
||||
MCFG_VOODOO_FBMEM(16)
|
||||
MCFG_VOODOO_SCREEN_TAG("screen")
|
||||
MCFG_VOODOO_CPU_TAG(":maincpu")
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
machine_config_constructor voodoo_pci_device::device_mconfig_additions() const
|
||||
@ -18,7 +17,7 @@ DEVICE_ADDRESS_MAP_START(reg_map, 32, voodoo_pci_device)
|
||||
AM_RANGE(0x0, 0x01ffffff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_r, banshee_w)
|
||||
ADDRESS_MAP_END
|
||||
DEVICE_ADDRESS_MAP_START(lfb_map, 32, voodoo_pci_device)
|
||||
AM_RANGE(0x0, 0x00ffffff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_fb_r, banshee_fb_w)
|
||||
AM_RANGE(0x0, 0x01ffffff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_fb_r, banshee_fb_w)
|
||||
ADDRESS_MAP_END
|
||||
DEVICE_ADDRESS_MAP_START(io_map, 32, voodoo_pci_device)
|
||||
AM_RANGE(0x000, 0x0ff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_io_r, banshee_io_w)
|
||||
@ -30,11 +29,17 @@ voodoo_pci_device::voodoo_pci_device(const machine_config &mconfig, const char *
|
||||
{
|
||||
}
|
||||
|
||||
void voodoo_pci_device::set_cpu_tag(const char *_cpu_tag)
|
||||
{
|
||||
cpu_tag = _cpu_tag;
|
||||
}
|
||||
|
||||
void voodoo_pci_device::device_start()
|
||||
{
|
||||
voodoo_device::static_set_cpu_tag(m_voodoo, cpu_tag);
|
||||
pci_device::device_start();
|
||||
add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::reg_map));
|
||||
add_map(16*1024*1024, M_MEM, FUNC(voodoo_pci_device::lfb_map));
|
||||
add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::lfb_map));
|
||||
add_map(256, M_IO, FUNC(voodoo_pci_device::io_map));
|
||||
}
|
||||
|
||||
|
||||
@ -6,8 +6,9 @@
|
||||
#include "machine/pci.h"
|
||||
#include "voodoo.h"
|
||||
|
||||
#define MCFG_VOODOO_ADD(_tag) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, VOODOO_PCI, 0x121a0005, 0x02, 0x000003, 0x000000)
|
||||
#define MCFG_VOODOO_ADD(_tag, _cpu_tag) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, VOODOO_PCI, 0x121a0005, 0x02, 0x000003, 0x000000) \
|
||||
downcast<voodoo_pci_device *>(device)->set_cpu_tag(_cpu_tag);
|
||||
|
||||
class voodoo_pci_device : public pci_device {
|
||||
public:
|
||||
@ -18,12 +19,15 @@ public:
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
|
||||
void set_cpu_tag(const char *tag);
|
||||
|
||||
protected:
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
private:
|
||||
required_device<voodoo_banshee_device> m_voodoo;
|
||||
const char *cpu_tag;
|
||||
|
||||
DECLARE_ADDRESS_MAP(reg_map, 32);
|
||||
DECLARE_ADDRESS_MAP(lfb_map, 32);
|
||||
|
||||
@ -118,7 +118,12 @@ void iteagle_state::machine_start()
|
||||
{
|
||||
/* set the fastest DRC options */
|
||||
m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
|
||||
|
||||
/* configure fast RAM regions for DRC */
|
||||
//m_maincpu->mips3drc_add_fastram(0x00000000, 16*1024*1024-1, FALSE, m_rambase);
|
||||
//m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
|
||||
}
|
||||
|
||||
void iteagle_state::machine_reset()
|
||||
{
|
||||
}
|
||||
@ -134,16 +139,20 @@ static MACHINE_CONFIG_START( gtfore, iteagle_state )
|
||||
MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu")
|
||||
MCFG_ITEAGLE_FPGA_ADD( ":pci:06.0")
|
||||
MCFG_ITEAGLE_IDE_ADD( ":pci:06.1")
|
||||
MCFG_ITEAGLE_IDE_IRQ_ADD( ":maincpu", MIPS3_IRQ2)
|
||||
MCFG_ES1373_ADD( ":pci:07.0")
|
||||
MCFG_SOUND_ROUTE(0, ":pci:07.0:lspeaker", 1.0)
|
||||
MCFG_SOUND_ROUTE(1, ":pci:07.0:rspeaker", 1.0)
|
||||
MCFG_ES1373_IRQ_ADD( ":maincpu", MIPS3_IRQ3)
|
||||
MCFG_VOODOO_ADD( ":pci:09.0")
|
||||
MCFG_VOODOO_ADD( ":pci:09.0", ":maincpu")
|
||||
MCFG_ITEAGLE_EEPROM_ADD( ":pci:0a.0")
|
||||
|
||||
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
|
||||
MCFG_SCREEN_REFRESH_RATE(56.644)
|
||||
MCFG_SCREEN_SIZE(640, 350)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 349)
|
||||
MCFG_SCREEN_REFRESH_RATE(59)
|
||||
MCFG_SCREEN_SIZE(512, 384)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 511, 0, 383)
|
||||
MCFG_SCREEN_UPDATE_DEVICE(":pci:09.0", voodoo_pci_device, screen_update)
|
||||
|
||||
|
||||
@ -158,31 +167,29 @@ MACHINE_CONFIG_END
|
||||
static INPUT_PORTS_START( iteagle )
|
||||
|
||||
PORT_START("SW5")
|
||||
PORT_DIPNAME( 0x3, 0x1, "Resolution" )
|
||||
PORT_DIPNAME( 0xf, 0x1, "Resolution" )
|
||||
PORT_DIPSETTING(0x1, "Medium" )
|
||||
PORT_DIPSETTING(0x0, "Low" )
|
||||
PORT_DIPSETTING(0x2, "Low_Alt" )
|
||||
|
||||
PORT_START("SW51")
|
||||
PORT_DIPNAME( 0x3, 0x0, "Mode" )
|
||||
PORT_DIPSETTING(0x0, "Normal" )
|
||||
PORT_DIPSETTING(0x1, "Operator" )
|
||||
|
||||
PORT_START("IN1")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START1 )
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Left" )
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Right" )
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Fly By" )
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME( "Backspin" )
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Right" )
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME( "Fly By" )
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Backspin" )
|
||||
PORT_BIT( 0x00c0, IP_ACTIVE_HIGH, IPT_UNUSED )
|
||||
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0xfe00, IP_ACTIVE_HIGH, IPT_UNUSED )
|
||||
|
||||
PORT_START("SYSTEM")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE )
|
||||
PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_HIGH )
|
||||
PORT_BIT( 0x00fc, IP_ACTIVE_HIGH, IPT_UNUSED )
|
||||
PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_LOW )
|
||||
PORT_BIT( 0x000c, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPNAME( 0x00f0, 0x00, "SW51" )
|
||||
PORT_DIPSETTING(0x00, "Normal" )
|
||||
PORT_DIPSETTING(0x10, "Operator Mode" )
|
||||
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_VOLUME_UP )
|
||||
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
|
||||
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BILL1 )
|
||||
@ -227,7 +234,7 @@ static INPUT_PORTS_START( gtfore04 )
|
||||
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( gtfore02o )
|
||||
static INPUT_PORTS_START( gtfore02 )
|
||||
PORT_INCLUDE(iteagle)
|
||||
|
||||
PORT_MODIFY("VERSION")
|
||||
@ -237,7 +244,7 @@ static INPUT_PORTS_START( gtfore02o )
|
||||
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( gtfore02 )
|
||||
static INPUT_PORTS_START( gtfore06 )
|
||||
PORT_INCLUDE(iteagle)
|
||||
|
||||
PORT_MODIFY("VERSION")
|
||||
@ -288,27 +295,27 @@ INPUT_PORTS_END
|
||||
ROM_START( iteagle )
|
||||
EAGLE_BIOS
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
ROM_END
|
||||
ROM_START( gtfore06 )
|
||||
EAGLE_BIOS
|
||||
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "g42-us-u.u53", 0x0000, 0x0880, CRC(06e0b452) SHA1(f6b865799cb94941e0e77453b9d556d5988b0194) )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_IMAGE( "golf_fore_2002_v2.01.04_umv", 0, SHA1(e902b91bd739daee0b95b10e5cf33700dd63a76b) ) /* Labeled Golf Fore! V2.01.04 UMV */
|
||||
//DISK_REGION( "ide:1:cdrom" ) // program CD-ROM
|
||||
|
||||
ROM_END
|
||||
|
||||
ROM_START( gtfore02 )
|
||||
EAGLE_BIOS
|
||||
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "g42-us-u.u53", 0x0000, 0x0880, CRC(06e0b452) SHA1(f6b865799cb94941e0e77453b9d556d5988b0194) )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
|
||||
DISK_IMAGE( "golf_fore_2002_v2.01.04_umv", 0, SHA1(e902b91bd739daee0b95b10e5cf33700dd63a76b) ) /* Labeled Golf Fore! V2.01.04 UMV */
|
||||
//DISK_REGION( "ide:1:cdrom" ) // program CD-ROM
|
||||
|
||||
ROM_END
|
||||
|
||||
ROM_START( gtfore02o )
|
||||
EAGLE_BIOS
|
||||
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "g42-us-u.u53", 0x0000, 0x0880, CRC(06e0b452) SHA1(f6b865799cb94941e0e77453b9d556d5988b0194) )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_IMAGE( "golf_fore_2002_v2.00.00", 0, SHA1(d789ef86837a5012beb224c487537dd563d93886) ) /* Labeled Golf Fore! 2002 V2.00.00 */
|
||||
ROM_END
|
||||
|
||||
@ -318,7 +325,7 @@ ROM_START( carnking )
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "ck1-us.u53", 0x0000, 0x0880, NO_DUMP )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_IMAGE( "carnival_king_v_1.00.11", 0, SHA1(c819af66d36df173ab17bf42f4045c7cca3203d8) ) /* Labeled Carnival King V 1.00.11 */
|
||||
ROM_END
|
||||
|
||||
@ -328,7 +335,7 @@ ROM_START( gtfore04 )
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "g44-us-u.u53", 0x0000, 0x0880, NO_DUMP )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_IMAGE( "gt2004", 0, SHA1(739a52d6ce13bb6ac7a543ee0e8086fb66be19b9) )
|
||||
ROM_END
|
||||
|
||||
@ -338,7 +345,7 @@ ROM_START( gtfore05 )
|
||||
ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */
|
||||
ROM_LOAD( "g45-us-u.u53", 0x0000, 0x0880, NO_DUMP )
|
||||
|
||||
DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
|
||||
DISK_REGION( ":pci:06.1:ide2:0:hdd:image" )
|
||||
DISK_IMAGE( "gt2005", 0, SHA1(d8de569d8cf97b5aaada10ce896eb3c75f1b37f1) )
|
||||
ROM_END
|
||||
|
||||
@ -349,8 +356,8 @@ ROM_END
|
||||
*************************************/
|
||||
|
||||
GAME( 2000, iteagle, 0, gtfore, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Eagle BIOS", GAME_IS_BIOS_ROOT )
|
||||
GAME( 2001, gtfore02, iteagle, gtfore, gtfore02, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.01.04 UMV)", GAME_NOT_WORKING | GAME_NO_SOUND )
|
||||
GAME( 2001, gtfore02o, gtfore02, gtfore, gtfore02o, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.00.00)", GAME_NOT_WORKING | GAME_NO_SOUND )
|
||||
GAME( 2001, gtfore02, iteagle, gtfore, gtfore02, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.00.00)", GAME_NOT_WORKING | GAME_NO_SOUND )
|
||||
GAME( 2002, carnking, iteagle, gtfore, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", GAME_NOT_WORKING | GAME_NO_SOUND )
|
||||
GAME( 2003, gtfore04, iteagle, gtfore, gtfore04, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004", GAME_NOT_WORKING | GAME_NO_SOUND )
|
||||
GAME( 2004, gtfore05, iteagle, gtfore, gtfore05, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005", GAME_NOT_WORKING | GAME_NO_SOUND )
|
||||
GAME( 2005, gtfore06, iteagle, gtfore, gtfore06, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete", GAME_NOT_WORKING | GAME_NO_SOUND )
|
||||
|
||||
@ -1,29 +1,26 @@
|
||||
#include "iteagle_fpga.h"
|
||||
#include "coreutil.h"
|
||||
|
||||
#define LOG_FPGA (1)
|
||||
#define LOG_FPGA (0)
|
||||
#define LOG_RTC (0)
|
||||
#define LOG_EEPROM (1)
|
||||
#define LOG_EEPROM (0)
|
||||
#define LOG_IDE (0)
|
||||
#define LOG_IDE_CTRL (0)
|
||||
|
||||
|
||||
const device_type ITEAGLE_FPGA = &device_creator<iteagle_fpga_device>;
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(ctrl_map, 32, iteagle_fpga_device)
|
||||
AM_RANGE(0x000, 0x02f) AM_READWRITE(ctrl_r, ctrl_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(fpga_map, 32, iteagle_fpga_device)
|
||||
AM_RANGE(0x000, 0x01f) AM_READWRITE(fpga_r, fpga_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(rtc_map, 32, iteagle_fpga_device)
|
||||
AM_RANGE(0x000, 0x800) AM_READWRITE(rtc_r, rtc_w)
|
||||
AM_RANGE(0x000, 0x7ff) AM_READWRITE(rtc_r, rtc_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__)
|
||||
: pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__),
|
||||
device_nvram_interface(mconfig, *this)
|
||||
{
|
||||
}
|
||||
|
||||
@ -33,68 +30,91 @@ void iteagle_fpga_device::device_start()
|
||||
status = 0x5555;
|
||||
command = 0x5555;
|
||||
|
||||
add_map(sizeof(m_ctrl_regs), M_IO, FUNC(iteagle_fpga_device::ctrl_map));
|
||||
// ctrl defaults to base address 0x00000000
|
||||
bank_infos[0].adr = 0x00000000 & (~(bank_infos[0].size - 1));
|
||||
|
||||
add_map(sizeof(m_fpga_regs), M_IO, FUNC(iteagle_fpga_device::fpga_map));
|
||||
// fpga defaults to base address 0x00000300
|
||||
bank_infos[1].adr = 0x00000300 & (~(bank_infos[1].size - 1));
|
||||
bank_infos[0].adr = 0x00000300 & (~(bank_infos[0].size - 1));
|
||||
|
||||
add_map(sizeof(m_rtc_regs), M_MEM, FUNC(iteagle_fpga_device::rtc_map));
|
||||
// RTC defaults to base address 0x000c0000
|
||||
bank_infos[2].adr = 0x000c0000 & (~(bank_infos[2].size - 1));
|
||||
bank_infos[1].adr = 0x000c0000 & (~(bank_infos[1].size - 1));
|
||||
}
|
||||
|
||||
void iteagle_fpga_device::device_reset()
|
||||
{
|
||||
pci_device::device_reset();
|
||||
memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs));
|
||||
memset(m_fpga_regs, 0, sizeof(m_fpga_regs));
|
||||
memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
|
||||
// 0x23 & 0x20 = IDE LED
|
||||
m_ctrl_regs[0x10/4] = 0x00000000; // 0xFFFFFFFF causes a write of 0xFFFEFFFF then 0xFFFFFFFF // Not sure
|
||||
//memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
|
||||
//m_rtc_regs[0] = 0x11223344;
|
||||
switch ((machine().root_device().ioport("VERSION")->read()>>4)&0xF) {
|
||||
case 3:
|
||||
m_seq = 0x0a0b0a; // gt02o
|
||||
break;
|
||||
case 4:
|
||||
m_seq = 0x0a020b; // gt04
|
||||
break;
|
||||
case 5:
|
||||
m_seq = 0x0b0a0c; // gt05
|
||||
break;
|
||||
default:
|
||||
m_seq = 0x0c0b0d; // gt02
|
||||
break;
|
||||
}
|
||||
|
||||
m_seq_rem1 = 0;
|
||||
m_seq_rem2 = 0;
|
||||
|
||||
// 0x00&0x2 == 1 for boot
|
||||
m_fpga_regs[0x00/4] = 0xC0000002; // 0xCF000002;// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
|
||||
//m_fpga_regs[0x308/4]=0x0000ffff; // Low 16 bits gets read a lot?
|
||||
m_fpga_regs[0x08/4]=0x00000000; // Low 16 bits gets read a lot?
|
||||
//m_fpga_regs[0x00/4] = 0xC1110002; // 0xCF000002;// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
|
||||
//m_fpga_regs[0x00/4] = 0xC010ffff;
|
||||
// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
|
||||
// Bit 20 seems to be sw51 (operator mode) 0 = Normal, 1 = Operator Mode
|
||||
//m_fpga_regs[0x04/4] = 0x06060044; // Nibble starting at bit 20 is resolution, byte 0 is atmel response
|
||||
m_fpga_regs[0x04/4] = 0x00000000; // Nibble starting at bit 20 is resolution, byte 0 is atmel response
|
||||
//m_fpga_regs[0x308/4]=0x0000ffff; // Low 16 bits gets read alot?
|
||||
//m_fpga_regs[0x08/4]=0x0000ffff; // Low 16 bits is trackball
|
||||
m_prev_reg = 0;
|
||||
}
|
||||
|
||||
READ32_MEMBER( iteagle_fpga_device::ctrl_r )
|
||||
void iteagle_fpga_device::update_sequence(UINT32 data)
|
||||
{
|
||||
UINT32 result = m_fpga_regs[offset];
|
||||
switch (offset) {
|
||||
case 0x0/4:
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
default:
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( iteagle_fpga_device::ctrl_w )
|
||||
{
|
||||
COMBINE_DATA(&m_fpga_regs[offset]);
|
||||
switch (offset) {
|
||||
case 0x20/4: // IDE LED and ??
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
// Probably watchdog
|
||||
} else if (ACCESSING_BITS_24_31) {
|
||||
// Bit 1 is IDE LED
|
||||
} else {
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
UINT32 offset = 0x04/4;
|
||||
if (data & 0x80) {
|
||||
switch (data&0x3) {
|
||||
case 0:
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>4)&0xF);
|
||||
break;
|
||||
case 1:
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>8)&0xF);
|
||||
break;
|
||||
case 2:
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>12)&0xF);
|
||||
break;
|
||||
case 3:
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>0)&0xF);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
UINT32 val1, feed;
|
||||
feed = ((m_seq<<4) ^ m_seq)>>7;
|
||||
if (data & 0x1) {
|
||||
val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
|
||||
m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
|
||||
m_seq_rem2 = ((m_seq & 0x80)>>1) | ((m_seq & 0x100)>>3) | ((m_seq & 0x200)>>5);
|
||||
m_seq = (m_seq>>9) | ((feed&0x1ff)<<15);
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
|
||||
} else if (data & 0x2) {
|
||||
val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
|
||||
m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
|
||||
m_seq = (m_seq>>6) | ((feed&0x3f)<<18);
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
|
||||
} else {
|
||||
val1 = ((m_seq & 0x2)<<6) | ((m_seq & 0x4)<<4) | ((m_seq & 0x8)<<2) | ((m_seq & 0x10)<<0)
|
||||
| ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4) | ((m_seq & 0x80)>>6) | ((m_seq & 0x100)>>8);
|
||||
m_seq = (m_seq>>8) | ((feed&0xff)<<16);
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2) & 0xff);
|
||||
}
|
||||
if (0 && LOG_FPGA)
|
||||
logerror("%s:fpga update_sequence In: %02X Seq: %06X Out: %02X\n", machine().describe_context(), data, m_seq, m_fpga_regs[offset]&0xff);
|
||||
}
|
||||
}
|
||||
|
||||
@ -103,22 +123,30 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
|
||||
UINT32 result = m_fpga_regs[offset];
|
||||
switch (offset) {
|
||||
case 0x00/4:
|
||||
if (LOG_FPGA && (m_prev_reg != offset && m_prev_reg != (0x08/4)))
|
||||
logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
result = ((machine().root_device().ioport("SYSTEM")->read()&0xffff)<<16) | (machine().root_device().ioport("IN1")->read()&0xffff);
|
||||
if (1 && LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x04/4:
|
||||
result = (result & 0xFF0FFFFF) | (machine().root_device().ioport("SW5")->read()<<20); // Resolution
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
result = (result & 0xFF0FFFFF) | ((machine().root_device().ioport("SW5")->read()&0xf)<<20);
|
||||
//if (0 && LOG_FPGA && ACCESSING_BITS_0_7)
|
||||
if (1 && LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
|
||||
case 0x08/4:
|
||||
if (LOG_FPGA && (m_prev_reg != offset && m_prev_reg != (0x00/4)))
|
||||
logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
result = (result & 0xffff0000) | ((machine().root_device().ioport("TRACKY1")->read()&0xff)<<8) | (machine().root_device().ioport("TRACKX1")->read()&0xff);
|
||||
if (1 && LOG_FPGA && m_prev_reg != offset)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x1c/4: // 1d = modem byte
|
||||
result = (result & 0xFFFFFF00) | 0x04;
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
default:
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
}
|
||||
m_prev_reg = offset;
|
||||
@ -127,43 +155,58 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
|
||||
|
||||
WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
|
||||
{
|
||||
UINT8 byte;
|
||||
|
||||
COMBINE_DATA(&m_fpga_regs[offset]);
|
||||
switch (offset) {
|
||||
case 0x04/4:
|
||||
if (ACCESSING_BITS_0_7) {
|
||||
// ATMEL Chip access. Returns version id's when bit 7 is set.
|
||||
byte = data & 0xFF;
|
||||
if (byte & 0x80) {
|
||||
switch (byte&0x3) {
|
||||
case 0:
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>4)&0xF);
|
||||
break;
|
||||
case 1:
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>8)&0xF);
|
||||
break;
|
||||
case 2:
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>12)&0xF);
|
||||
break;
|
||||
case 3:
|
||||
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>0)&0xF);
|
||||
break;
|
||||
}
|
||||
} // Else???
|
||||
update_sequence(data & 0xff);
|
||||
if (0 && LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
} else {
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
default:
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
}
|
||||
}
|
||||
//*************************************
|
||||
//* RTC M48T02
|
||||
//*************************************
|
||||
|
||||
//-------------------------------------------------
|
||||
// nvram_default - called to initialize NVRAM to
|
||||
// its default state
|
||||
//-------------------------------------------------
|
||||
|
||||
void iteagle_fpga_device::nvram_default()
|
||||
{
|
||||
memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// nvram_read - called to read NVRAM from the
|
||||
// .nv file
|
||||
//-------------------------------------------------
|
||||
void iteagle_fpga_device::nvram_read(emu_file &file)
|
||||
{
|
||||
file.read(m_rtc_regs, sizeof(m_rtc_regs));
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// nvram_write - called to write NVRAM to the
|
||||
// .nv file
|
||||
//-------------------------------------------------
|
||||
void iteagle_fpga_device::nvram_write(emu_file &file)
|
||||
{
|
||||
file.write(m_rtc_regs, sizeof(m_rtc_regs));
|
||||
}
|
||||
|
||||
READ32_MEMBER( iteagle_fpga_device::rtc_r )
|
||||
{
|
||||
UINT32 result = m_rtc_regs[offset];
|
||||
@ -176,6 +219,7 @@ READ32_MEMBER( iteagle_fpga_device::rtc_r )
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( iteagle_fpga_device::rtc_w )
|
||||
{
|
||||
system_time systime;
|
||||
@ -197,8 +241,8 @@ WRITE32_MEMBER( iteagle_fpga_device::rtc_w )
|
||||
raw[6] = dec_2_bcd(systime.local_time.month + 1);
|
||||
raw[7] = dec_2_bcd(systime.local_time.year - 1900); // Epoch is 1900
|
||||
m_rtc_regs[0x7F8/4] = (raw[3]<<24) | (raw[2]<<16) | (raw[1]<<8) | (raw[0] <<0);
|
||||
//m_rtc_regs[0x7FC/4] = (raw[7]<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0);
|
||||
m_rtc_regs[0x7FC/4] = (0x95<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0);
|
||||
m_rtc_regs[0x7FC/4] = (raw[7]<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0);
|
||||
//m_rtc_regs[0x7FC/4] = (0x95<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0);
|
||||
}
|
||||
if (LOG_RTC)
|
||||
logerror("%s:RTC write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
@ -222,8 +266,27 @@ DEVICE_ADDRESS_MAP_START(eeprom_map, 32, iteagle_eeprom_device)
|
||||
AM_RANGE(0x0000, 0x000F) AM_READWRITE(eeprom_r, eeprom_w) AM_SHARE("eeprom")
|
||||
ADDRESS_MAP_END
|
||||
|
||||
// When corrupt writes 0x3=2, 0x3e=2, 0xa=0, 0x30=0
|
||||
// 0x4 = HW Version
|
||||
// 0x5 = Serial Num + top byte of 0x4
|
||||
// 0x6 = OperID
|
||||
// 0xe = SW Version
|
||||
// 0x7f = checksum
|
||||
static const UINT16 iteagle_default_eeprom[0x40] =
|
||||
{
|
||||
0x0011,0x0022,0x0033,0x0002,0x1206,0x1111,0x2222,0x1234,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0002,0x0000
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( iteagle_eeprom )
|
||||
MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
|
||||
MCFG_EEPROM_SERIAL_DATA(iteagle_default_eeprom, 0x80)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
machine_config_constructor iteagle_eeprom_device::device_mconfig_additions() const
|
||||
@ -246,6 +309,15 @@ void iteagle_eeprom_device::device_start()
|
||||
|
||||
void iteagle_eeprom_device::device_reset()
|
||||
{
|
||||
// Set software version and calc crc
|
||||
m_eeprom->write(0xe, (machine().root_device().ioport("VERSION")->read()&0xFF00) |
|
||||
(((machine().root_device().ioport("VERSION")->read()>>4)&0x0F)));
|
||||
UINT16 checkSum = 0;
|
||||
for (int i=0; i<0x3f; i++) {
|
||||
checkSum += m_eeprom->read(i);
|
||||
//logerror("eeprom init i: %x data: %04x\n", i, m_eeprom->read(i));
|
||||
}
|
||||
m_eeprom->write(0x3f, checkSum);
|
||||
pci_device::device_reset();
|
||||
}
|
||||
|
||||
@ -257,13 +329,13 @@ READ32_MEMBER( iteagle_eeprom_device::eeprom_r )
|
||||
case 0xC/4: // I2C Handler
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
result = m_eeprom->do_read()<<(16+3);
|
||||
} else {
|
||||
if (LOG_EEPROM)
|
||||
logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
} else {
|
||||
logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (LOG_EEPROM)
|
||||
logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
}
|
||||
@ -278,13 +350,15 @@ WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w )
|
||||
m_eeprom->di_write((data & 0x040000) >> (16+2));
|
||||
m_eeprom->cs_write((data & 0x020000) ? ASSERT_LINE : CLEAR_LINE);
|
||||
m_eeprom->clk_write((data & 0x010000) ? ASSERT_LINE : CLEAR_LINE);
|
||||
} else {
|
||||
if (LOG_EEPROM)
|
||||
logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
} else {
|
||||
//if (LOG_EEPROM)
|
||||
logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (LOG_EEPROM)
|
||||
//if (LOG_EEPROM)
|
||||
logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
}
|
||||
@ -296,17 +370,34 @@ WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w )
|
||||
|
||||
const device_type ITEAGLE_IDE = &device_creator<iteagle_ide_device>;
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(ctrl_map, 32, iteagle_ide_device)
|
||||
AM_RANGE(0x000, 0x02f) AM_READWRITE(ctrl_r, ctrl_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(ide_map, 32, iteagle_ide_device)
|
||||
AM_RANGE(0x0, 0xf) AM_READWRITE(ide_r, ide_w)
|
||||
AM_RANGE(0x0, 0x7) AM_READWRITE(ide_r, ide_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(ide_ctrl_map, 32, iteagle_ide_device)
|
||||
AM_RANGE(0x0, 0x3) AM_READWRITE(ide_ctrl_r, ide_ctrl_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(ide2_map, 32, iteagle_ide_device)
|
||||
AM_RANGE(0x0, 0x7) AM_READWRITE(ide2_r, ide2_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(ide2_ctrl_map, 32, iteagle_ide_device)
|
||||
AM_RANGE(0x0, 0x3) AM_READWRITE(ide2_ctrl_r, ide2_ctrl_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( iteagle_ide )
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, NULL, "cdrom", true)
|
||||
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_ide_device, ide_interrupt))
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, "hdd", NULL, true)
|
||||
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_ide_device, ide2_interrupt))
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
@ -314,31 +405,99 @@ machine_config_constructor iteagle_ide_device::device_mconfig_additions() const
|
||||
{
|
||||
return MACHINE_CONFIG_NAME( iteagle_ide );
|
||||
}
|
||||
|
||||
iteagle_ide_device::iteagle_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: pci_device(mconfig, ITEAGLE_IDE, "ITEagle IDE Controller", tag, owner, clock, "ide", __FILE__),
|
||||
m_ide(*this, "ide")
|
||||
m_ide(*this, "ide"),
|
||||
m_ide2(*this, "ide2"),
|
||||
m_irq_num(-1)
|
||||
{
|
||||
}
|
||||
|
||||
void iteagle_ide_device::set_irq_info(const char *tag, const int irq_num)
|
||||
{
|
||||
m_cpu_tag = tag;
|
||||
m_irq_num = irq_num;
|
||||
}
|
||||
|
||||
void iteagle_ide_device::device_start()
|
||||
{
|
||||
m_cpu = machine().device<cpu_device>(m_cpu_tag);
|
||||
pci_device::device_start();
|
||||
add_map(0x10, M_IO, FUNC(iteagle_ide_device::ide_map));
|
||||
bank_infos[0].adr = 0x1f0;
|
||||
add_map(sizeof(m_ctrl_regs), M_IO, FUNC(ctrl_map));
|
||||
// ctrl defaults to base address 0x00000000
|
||||
bank_infos[0].adr = 0x000;
|
||||
|
||||
add_map(0x8, M_IO, FUNC(iteagle_ide_device::ide_map));
|
||||
bank_infos[1].adr = 0x170;
|
||||
add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide_ctrl_map));
|
||||
bank_infos[1].adr = 0x3f4;
|
||||
bank_infos[2].adr = 0x374;
|
||||
add_map(0x8, M_IO, FUNC(iteagle_ide_device::ide2_map));
|
||||
bank_infos[3].adr = 0x1f0;
|
||||
add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide2_ctrl_map));
|
||||
bank_infos[4].adr = 0x3f4;
|
||||
}
|
||||
|
||||
void iteagle_ide_device::device_reset()
|
||||
{
|
||||
pci_device::device_reset();
|
||||
memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs));
|
||||
// 0x23 & 0x20 = IDE LED
|
||||
m_ctrl_regs[0x10/4] = 0x00000000; // 0x6=No SIMM, 0x2, 0x0 = SIMM
|
||||
}
|
||||
//*************************************
|
||||
//* IDE
|
||||
//*************************************
|
||||
|
||||
READ32_MEMBER( iteagle_ide_device::ctrl_r )
|
||||
{
|
||||
UINT32 result = m_ctrl_regs[offset];
|
||||
switch (offset) {
|
||||
case 0x0/4:
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
default:
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( iteagle_ide_device::ctrl_w )
|
||||
{
|
||||
COMBINE_DATA(&m_ctrl_regs[offset]);
|
||||
switch (offset) {
|
||||
case 0x20/4: // IDE LED and ??
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
// Probably watchdog
|
||||
if (1 && LOG_IDE_CTRL)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
} else if (ACCESSING_BITS_24_31) {
|
||||
// Bit 25 is IDE LED
|
||||
if (1 && LOG_IDE_CTRL)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
} else {
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER( iteagle_ide_device::ide_r )
|
||||
{
|
||||
UINT32 result = m_ide->read_cs0(space, offset, mem_mask);
|
||||
if (offset==0x4/4 && ACCESSING_BITS_24_31) {
|
||||
//result = 0;
|
||||
if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x80000000) {
|
||||
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
|
||||
if (LOG_IDE)
|
||||
logerror("%s:ide_interrupt Clearing interrupt\n", machine().describe_context());
|
||||
}
|
||||
}
|
||||
if (LOG_IDE)
|
||||
logerror("%s:ide_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
return result;
|
||||
@ -362,3 +521,54 @@ WRITE32_MEMBER( iteagle_ide_device::ide_ctrl_w )
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide_ctrl_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
WRITE_LINE_MEMBER(iteagle_ide_device::ide_interrupt)
|
||||
{
|
||||
//cpu_device *m_cpu = machine().device<cpu_device>(":maincpu");
|
||||
if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x80000000) {
|
||||
m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide_interrupt Setting interrupt\n", machine().describe_context());
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER( iteagle_ide_device::ide2_r )
|
||||
{
|
||||
UINT32 result = m_ide2->read_cs0(space, offset, mem_mask);
|
||||
if (offset==0x4/4 && ACCESSING_BITS_24_31) {
|
||||
if ((m_irq_num!=-1) && m_ctrl_regs[0x20/4]&0x40000000) {
|
||||
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide2_interrupt Clearing interrupt\n", machine().describe_context());
|
||||
}
|
||||
}
|
||||
if (LOG_IDE)
|
||||
logerror("%s:ide2_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
return result;
|
||||
}
|
||||
WRITE32_MEMBER( iteagle_ide_device::ide2_w )
|
||||
{
|
||||
m_ide2->write_cs0(space, offset, data, mem_mask);
|
||||
if (LOG_IDE)
|
||||
logerror("%s:ide2_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
READ32_MEMBER( iteagle_ide_device::ide2_ctrl_r )
|
||||
{
|
||||
UINT32 result = m_ide2->read_cs1(space, offset+1, mem_mask);
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide2_ctrl_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
return result;
|
||||
}
|
||||
WRITE32_MEMBER( iteagle_ide_device::ide2_ctrl_w )
|
||||
{
|
||||
m_ide2->write_cs1(space, offset+1, data, mem_mask);
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide2_ctrl_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
WRITE_LINE_MEMBER(iteagle_ide_device::ide2_interrupt)
|
||||
{
|
||||
if ((m_irq_num!=-1) &&m_ctrl_regs[0x20/4]&0x40000000) {
|
||||
m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
|
||||
if (LOG_IDE_CTRL)
|
||||
logerror("%s:ide2_interrupt Setting interrupt\n", machine().describe_context());
|
||||
}
|
||||
}
|
||||
|
||||
@ -17,7 +17,12 @@
|
||||
#define MCFG_ITEAGLE_IDE_ADD(_tag) \
|
||||
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_IDE, 0x11223344, 0x00, 0x010100, 0x00)
|
||||
|
||||
class iteagle_fpga_device : public pci_device {
|
||||
#define MCFG_ITEAGLE_IDE_IRQ_ADD(_cpu_tag, _irq_num) \
|
||||
downcast<iteagle_ide_device *>(device)->set_irq_info(_cpu_tag, _irq_num);
|
||||
|
||||
class iteagle_fpga_device : public pci_device,
|
||||
public device_nvram_interface
|
||||
{
|
||||
public:
|
||||
iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
@ -25,19 +30,24 @@ protected:
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
// device_nvram_interface overrides
|
||||
virtual void nvram_default();
|
||||
virtual void nvram_read(emu_file &file);
|
||||
virtual void nvram_write(emu_file &file);
|
||||
|
||||
private:
|
||||
|
||||
UINT32 m_ctrl_regs[0x30];
|
||||
UINT32 m_fpga_regs[0x20];
|
||||
UINT32 m_rtc_regs[0x800];
|
||||
UINT32 m_rtc_regs[0x200];
|
||||
UINT32 m_prev_reg;
|
||||
|
||||
UINT32 m_seq;
|
||||
UINT32 m_seq_rem1, m_seq_rem2;
|
||||
void update_sequence(UINT32 data);
|
||||
|
||||
DECLARE_ADDRESS_MAP(rtc_map, 32);
|
||||
DECLARE_ADDRESS_MAP(fpga_map, 32);
|
||||
DECLARE_ADDRESS_MAP(ctrl_map, 32);
|
||||
|
||||
DECLARE_READ32_MEMBER( ctrl_r );
|
||||
DECLARE_WRITE32_MEMBER( ctrl_w );
|
||||
DECLARE_READ32_MEMBER( fpga_r );
|
||||
DECLARE_WRITE32_MEMBER( fpga_w );
|
||||
DECLARE_READ32_MEMBER( rtc_r );
|
||||
@ -67,21 +77,43 @@ public:
|
||||
iteagle_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
// optional information overrides
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
void set_irq_info(const char *tag, const int irq_num);
|
||||
|
||||
required_device<bus_master_ide_controller_device> m_ide;
|
||||
required_device<bus_master_ide_controller_device> m_ide2;
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide2_interrupt);
|
||||
|
||||
protected:
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
private:
|
||||
const char *m_cpu_tag;
|
||||
cpu_device *m_cpu;
|
||||
int m_irq_num;
|
||||
|
||||
UINT32 m_ctrl_regs[0x30];
|
||||
|
||||
DECLARE_ADDRESS_MAP(ctrl_map, 32);
|
||||
DECLARE_ADDRESS_MAP(ide_map, 32);
|
||||
DECLARE_ADDRESS_MAP(ide_ctrl_map, 32);
|
||||
DECLARE_ADDRESS_MAP(ide2_map, 32);
|
||||
DECLARE_ADDRESS_MAP(ide2_ctrl_map, 32);
|
||||
|
||||
DECLARE_READ32_MEMBER( ctrl_r );
|
||||
DECLARE_WRITE32_MEMBER( ctrl_w );
|
||||
|
||||
DECLARE_READ32_MEMBER( ide_r );
|
||||
DECLARE_WRITE32_MEMBER( ide_w );
|
||||
DECLARE_READ32_MEMBER( ide_ctrl_r );
|
||||
DECLARE_WRITE32_MEMBER( ide_ctrl_w );
|
||||
|
||||
DECLARE_READ32_MEMBER( ide2_r );
|
||||
DECLARE_WRITE32_MEMBER( ide2_w );
|
||||
DECLARE_READ32_MEMBER( ide2_ctrl_r );
|
||||
DECLARE_WRITE32_MEMBER( ide2_ctrl_w );
|
||||
|
||||
};
|
||||
|
||||
extern const device_type ITEAGLE_FPGA;
|
||||
|
||||
@ -4237,10 +4237,10 @@ gtclassc // (c) 2001 Incredible Technologies
|
||||
gtclasscp // (c) 2001 Incredible Technologies
|
||||
gtclasscs // (c) 2001 Incredible Technologies
|
||||
gtfore02 // (c) 2001 Incredible Technologies
|
||||
gtfore02o // (c) 2001 Incredible Technologies
|
||||
carnking // (c) 2002 Incredible Technologies
|
||||
gtfore04 // (c) 2003 Incredible Technologies
|
||||
gtfore05 // (c) 2004 Incredible Technologies
|
||||
gtfore06 // (c) 2005 Incredible Technologies
|
||||
|
||||
// Leland games
|
||||
cerberus // (c) 1985 Cinematronics
|
||||
|
||||
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Reference in New Issue
Block a user