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Merge pull request #1574 from npwoods/dasmstream_avr8

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Changed the AVR8 disassembler to use 'std::ostream &' internally
This commit is contained in:
R. Belmont 2016-10-27 16:25:58 -04:00 committed by GitHub
commit da84ed911b
1 changed files with 154 additions and 145 deletions
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299
src/devices/cpu/avr8/avr8dasm.cpp
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@ -25,9 +25,8 @@
#define ACONST6(op) ((((op) >> 5) & 0x0030) | ((op) & 0x000f))
#define MULCONST2(op) ((((op) >> 6) & 0x0002) | (((op) >> 3) & 0x0001))
CPU_DISASSEMBLE( avr8 )
static offs_t internal_disasm_avr8(cpu_device *device, std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, int options)
{
char *output = buffer;
int pos = 0;
uint32_t op = oprom[pos++];
op |= oprom[pos++] << 8;
@ -106,28 +105,28 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x0f00)
{
case 0x0000:
output += sprintf( output, "NOP" );
util::stream_format(stream, "NOP");
break;
case 0x0100:
output += sprintf( output, "MOVW R%d:R%d, R%d:R%d", (RD4(op) << 1)+1, RD4(op) << 1, (RR4(op) << 1)+1, RR4(op) << 1 );
util::stream_format(stream, "MOVW R%d:R%d, R%d:R%d", (RD4(op) << 1)+1, RD4(op) << 1, (RR4(op) << 1)+1, RR4(op) << 1);
break;
case 0x0200:
output += sprintf( output, "MULS R%d, R%d", 16+RD4(op), 16+RR4(op) );
util::stream_format(stream, "MULS R%d, R%d", 16+RD4(op), 16+RR4(op));
break;
case 0x0300:
switch(MULCONST2(op))
{
case 0:
output += sprintf( output, "MULSU R%d, R%d", 16+RD3(op), 16+RR3(op) );
util::stream_format(stream, "MULSU R%d, R%d", 16+RD3(op), 16+RR3(op));
break;
case 1:
output += sprintf( output, "FMUL R%d, R%d", 16+RD3(op), 16+RR3(op) );
util::stream_format(stream, "FMUL R%d, R%d", 16+RD3(op), 16+RR3(op));
break;
case 2:
output += sprintf( output, "FMULS R%d, R%d", 16+RD3(op), 16+RR3(op) );
util::stream_format(stream, "FMULS R%d, R%d", 16+RD3(op), 16+RR3(op));
break;
case 3:
output += sprintf( output, "FMULSU R%d, R%d", 16+RD3(op), 16+RR3(op) );
util::stream_format(stream, "FMULSU R%d, R%d", 16+RD3(op), 16+RR3(op));
break;
}
break;
@ -135,19 +134,19 @@ CPU_DISASSEMBLE( avr8 )
case 0x0500:
case 0x0600:
case 0x0700:
output += sprintf( output, "CPC R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "CPC R%d, R%d", RD5(op), RR5(op));
break;
case 0x0800:
case 0x0900:
case 0x0a00:
case 0x0b00:
output += sprintf( output, "SBC R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "SBC R%d, R%d", RD5(op), RR5(op));
break;
case 0x0c00:
case 0x0d00:
case 0x0e00:
case 0x0f00:
output += sprintf( output, "ADD R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "ADD R%d, R%d", RD5(op), RR5(op));
break;
}
break;
@ -155,16 +154,16 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x0c00)
{
case 0x0000:
output += sprintf( output, "CPSE R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "CPSE R%d, R%d", RD5(op), RR5(op));
break;
case 0x0400:
output += sprintf( output, "CP R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "CP R%d, R%d", RD5(op), RR5(op));
break;
case 0x0800:
output += sprintf( output, "SUB R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "SUB R%d, R%d", RD5(op), RR5(op));
break;
case 0x0c00:
output += sprintf( output, "ADC R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "ADC R%d, R%d", RD5(op), RR5(op));
break;
}
break;
@ -172,49 +171,49 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x0c00)
{
case 0x0000:
output += sprintf( output, "AND R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "AND R%d, R%d", RD5(op), RR5(op));
break;
case 0x0400:
output += sprintf( output, "EOR R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "EOR R%d, R%d", RD5(op), RR5(op));
break;
case 0x0800:
output += sprintf( output, "OR R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "OR R%d, R%d", RD5(op), RR5(op));
break;
case 0x0c00:
output += sprintf( output, "MOV R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "MOV R%d, R%d", RD5(op), RR5(op));
break;
}
break;
case 0x3000:
output += sprintf( output, "CPI R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
util::stream_format(stream, "CPI R%d, 0x%02x", 16+RD4(op), KCONST8(op));
break;
case 0x4000:
output += sprintf( output, "SBCI R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
util::stream_format(stream, "SBCI R%d, 0x%02x", 16+RD4(op), KCONST8(op));
break;
case 0x5000:
output += sprintf( output, "SUBI R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
util::stream_format(stream, "SUBI R%d, 0x%02x", 16+RD4(op), KCONST8(op));
break;
case 0x6000:
output += sprintf( output, "ORI R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
util::stream_format(stream, "ORI R%d, 0x%02x", 16+RD4(op), KCONST8(op));
break;
case 0x7000:
output += sprintf( output, "ANDI R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
util::stream_format(stream, "ANDI R%d, 0x%02x", 16+RD4(op), KCONST8(op));
break;
case 0x8000:
case 0xa000:
switch(op & 0x0208)
{
case 0x0000:
output += sprintf( output, "LD(D) R%d, Z+%02x", RD5(op), QCONST6(op) );
util::stream_format(stream, "LD(D) R%d, Z+%02x", RD5(op), QCONST6(op));
break;
case 0x0008:
output += sprintf( output, "LD(D) R%d, Y+%02x", RD5(op), QCONST6(op) );
util::stream_format(stream, "LD(D) R%d, Y+%02x", RD5(op), QCONST6(op));
break;
case 0x0200:
output += sprintf( output, "ST(D) Z+%02x, R%d", QCONST6(op), RD5(op) );
util::stream_format(stream, "ST(D) Z+%02x, R%d", QCONST6(op), RD5(op));
break;
case 0x0208:
output += sprintf( output, "ST(D) Y+%02x, R%d", QCONST6(op), RD5(op) );
util::stream_format(stream, "ST(D) Y+%02x, R%d", QCONST6(op), RD5(op));
break;
}
break;
@ -229,46 +228,46 @@ CPU_DISASSEMBLE( avr8 )
op <<= 16;
op |= oprom[pos++];
op |= oprom[pos++] << 8;
output += sprintf( output, "LDS R%d, (0x%04x)", RD5(op >> 16), op & 0x0000ffff );
util::stream_format(stream, "LDS R%d, (0x%04x)", RD5(op >> 16), op & 0x0000ffff);
break;
case 0x0001:
output += sprintf( output, "LD R%d, Z+", RD5(op) );
util::stream_format(stream, "LD R%d, Z+", RD5(op));
break;
case 0x0002:
output += sprintf( output, "LD R%d,-Z", RD5(op) );
util::stream_format(stream, "LD R%d,-Z", RD5(op));
break;
case 0x0004:
output += sprintf( output, "LPM R%d, Z", RD5(op) );
util::stream_format(stream, "LPM R%d, Z", RD5(op));
break;
case 0x0005:
output += sprintf( output, "LPM R%d, Z+", RD5(op) );
util::stream_format(stream, "LPM R%d, Z+", RD5(op));
break;
case 0x0006:
output += sprintf( output, "ELPM R%d, Z", RD5(op) );
util::stream_format(stream, "ELPM R%d, Z", RD5(op));
break;
case 0x0007:
output += sprintf( output, "ELPM R%d, Z+", RD5(op) );
util::stream_format(stream, "ELPM R%d, Z+", RD5(op));
break;
case 0x0009:
output += sprintf( output, "LD R%d, Y+", RD5(op) );
util::stream_format(stream, "LD R%d, Y+", RD5(op));
break;
case 0x000a:
output += sprintf( output, "LD R%d,-Y", RD5(op) );
util::stream_format(stream, "LD R%d,-Y", RD5(op));
break;
case 0x000c:
output += sprintf( output, "LD R%d, X", RD5(op) );
util::stream_format(stream, "LD R%d, X", RD5(op));
break;
case 0x000d:
output += sprintf( output, "LD R%d, X+", RD5(op) );
util::stream_format(stream, "LD R%d, X+", RD5(op));
break;
case 0x000e:
output += sprintf( output, "LD R%d,-X", RD5(op) );
util::stream_format(stream, "LD R%d,-X", RD5(op));
break;
case 0x000f:
output += sprintf( output, "POP R%d", RD5(op) );
util::stream_format(stream, "POP R%d", RD5(op));
break;
default:
output += sprintf( output, "Undefined (%08x)", op );
util::stream_format(stream, "Undefined (%08x)", op);
break;
}
break;
@ -280,34 +279,34 @@ CPU_DISASSEMBLE( avr8 )
op <<= 16;
op |= oprom[pos++];
op |= oprom[pos++] << 8;
output += sprintf( output, "STS (0x%04x), R%d", op & 0x0000ffff, RD5(op >> 16) );
util::stream_format(stream, "STS (0x%04x), R%d", op & 0x0000ffff, RD5(op >> 16));
break;
case 0x0001:
output += sprintf( output, "ST Z+, R%d", RD5(op) );
util::stream_format(stream, "ST Z+, R%d", RD5(op));
break;
case 0x0002:
output += sprintf( output, "ST -Z , R%d", RD5(op) );
util::stream_format(stream, "ST -Z , R%d", RD5(op));
break;
case 0x0009:
output += sprintf( output, "ST Y+, R%d", RD5(op) );
util::stream_format(stream, "ST Y+, R%d", RD5(op));
break;
case 0x000a:
output += sprintf( output, "ST -Y , R%d", RD5(op) );
util::stream_format(stream, "ST -Y , R%d", RD5(op));
break;
case 0x000c:
output += sprintf( output, "ST X , R%d", RD5(op) );
util::stream_format(stream, "ST X , R%d", RD5(op));
break;
case 0x000d:
output += sprintf( output, "ST X+, R%d", RD5(op) );
util::stream_format(stream, "ST X+, R%d", RD5(op));
break;
case 0x000e:
output += sprintf( output, "ST -X , R%d", RD5(op) );
util::stream_format(stream, "ST -X , R%d", RD5(op));
break;
case 0x000f:
output += sprintf( output, "PUSH R%d", RD5(op) );
util::stream_format(stream, "PUSH R%d", RD5(op));
break;
default:
output += sprintf( output, "Undefined (%08x)", op );
util::stream_format(stream, "Undefined (%08x)", op);
break;
}
break;
@ -315,79 +314,79 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x000f)
{
case 0x0000:
output += sprintf( output, "COM R%d", RD5(op) );
util::stream_format(stream, "COM R%d", RD5(op));
break;
case 0x0001:
output += sprintf( output, "NEG R%d", RD5(op) );
util::stream_format(stream, "NEG R%d", RD5(op));
break;
case 0x0002:
output += sprintf( output, "SWAP R%d", RD5(op) );
util::stream_format(stream, "SWAP R%d", RD5(op));
break;
case 0x0003:
output += sprintf( output, "INC R%d", RD5(op) );
util::stream_format(stream, "INC R%d", RD5(op));
break;
case 0x0005:
output += sprintf( output, "ASR R%d", RD5(op) );
util::stream_format(stream, "ASR R%d", RD5(op));
break;
case 0x0006:
output += sprintf( output, "LSR R%d", RD5(op) );
util::stream_format(stream, "LSR R%d", RD5(op));
break;
case 0x0007:
output += sprintf( output, "ROR R%d", RD5(op) );
util::stream_format(stream, "ROR R%d", RD5(op));
break;
case 0x0008:
switch(op & 0x00f0)
{
case 0x0000:
output += sprintf( output, "SEC" );
util::stream_format(stream, "SEC");
break;
case 0x0010:
output += sprintf( output, "SEZ" );
util::stream_format(stream, "SEZ");
break;
case 0x0020:
output += sprintf( output, "SEN" );
util::stream_format(stream, "SEN");
break;
case 0x0030:
output += sprintf( output, "SEV" );
util::stream_format(stream, "SEV");
break;
case 0x0040:
output += sprintf( output, "SES" );
util::stream_format(stream, "SES");
break;
case 0x0050:
output += sprintf( output, "SEH" );
util::stream_format(stream, "SEH");
break;
case 0x0060:
output += sprintf( output, "SET" );
util::stream_format(stream, "SET");
break;
case 0x0070:
output += sprintf( output, "SEI" );
util::stream_format(stream, "SEI");
break;
case 0x0080:
output += sprintf( output, "CLC" );
util::stream_format(stream, "CLC");
break;
case 0x0090:
output += sprintf( output, "CLZ" );
util::stream_format(stream, "CLZ");
break;
case 0x00a0:
output += sprintf( output, "CLN" );
util::stream_format(stream, "CLN");
break;
case 0x00b0:
output += sprintf( output, "CLV" );
util::stream_format(stream, "CLV");
break;
case 0x00c0:
output += sprintf( output, "CLS" );
util::stream_format(stream, "CLS");
break;
case 0x00d0:
output += sprintf( output, "CLH" );
util::stream_format(stream, "CLH");
break;
case 0x00e0:
output += sprintf( output, "CLT" );
util::stream_format(stream, "CLT");
break;
case 0x00f0:
output += sprintf( output, "CLI" );
util::stream_format(stream, "CLI");
break;
default:
output += sprintf( output, "Undefined (%08x)", op );
util::stream_format(stream, "Undefined (%08x)", op);
break;
}
break;
@ -395,35 +394,35 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x00f0)
{
case 0x0000:
output += sprintf( output, "IJMP" );
util::stream_format(stream, "IJMP");
break;
case 0x0010:
output += sprintf( output, "EIJMP" );
util::stream_format(stream, "EIJMP");
break;
default:
output += sprintf( output, "Undefined (%08x)", op );
util::stream_format(stream, "Undefined (%08x)", op);
break;
}
break;
case 0x000a:
output += sprintf( output, "DEC R%d", RD5(op) );
util::stream_format(stream, "DEC R%d", RD5(op));
break;
case 0x000c:
case 0x000d:
addr = KCONST22(op) << 16;
addr |= oprom[pos++];
addr |= oprom[pos++] << 8;
output += sprintf( output, "JMP 0x%06x", addr << 1 );
util::stream_format(stream, "JMP 0x%06x", addr << 1);
break;
case 0x000e:
case 0x000f:
addr = KCONST22(op) << 16;
addr |= oprom[pos++];
addr |= oprom[pos++] << 8;
output += sprintf( output, "CALL 0x%06x", addr << 1 );
util::stream_format(stream, "CALL 0x%06x", addr << 1);
break;
default:
output += sprintf( output, "Undefined (%08x)", op );
util::stream_format(stream, "Undefined (%08x)", op);
break;
}
break;
@ -431,58 +430,58 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x000f)
{
case 0x0000:
output += sprintf( output, "COM R%d", RD5(op) );
util::stream_format(stream, "COM R%d", RD5(op));
break;
case 0x0001:
output += sprintf( output, "NEG R%d", RD5(op) );
util::stream_format(stream, "NEG R%d", RD5(op));
break;
case 0x0002:
output += sprintf( output, "SWAP R%d", RD5(op) );
util::stream_format(stream, "SWAP R%d", RD5(op));
break;
case 0x0003:
output += sprintf( output, "INC R%d", RD5(op) );
util::stream_format(stream, "INC R%d", RD5(op));
break;
case 0x0005:
output += sprintf( output, "ASR R%d", RD5(op) );
util::stream_format(stream, "ASR R%d", RD5(op));
break;
case 0x0006:
output += sprintf( output, "LSR R%d", RD5(op) );
util::stream_format(stream, "LSR R%d", RD5(op));
break;
case 0x0007:
output += sprintf( output, "ROR R%d", RD5(op) );
util::stream_format(stream, "ROR R%d", RD5(op));
break;
case 0x0008:
switch(op & 0x00f0)
{
case 0x0000:
output += sprintf( output, "RET" );
util::stream_format(stream, "RET");
break;
case 0x0010:
output += sprintf( output, "RETI" );
util::stream_format(stream, "RETI");
break;
case 0x0080:
output += sprintf( output, "SLEEP" );
util::stream_format(stream, "SLEEP");
break;
case 0x0090:
output += sprintf( output, "BREAK" );
util::stream_format(stream, "BREAK");
break;
case 0x00a0:
output += sprintf( output, "WDR" );
util::stream_format(stream, "WDR");
break;
case 0x00c0:
output += sprintf( output, "LPM" );
util::stream_format(stream, "LPM");
break;
case 0x00d0:
output += sprintf( output, "ELPM" );
util::stream_format(stream, "ELPM");
break;
case 0x00e0:
output += sprintf( output, "SPM" );
util::stream_format(stream, "SPM");
break;
case 0x00f0:
output += sprintf( output, "SPM Z+" );
util::stream_format(stream, "SPM Z+");
break;
default:
output += sprintf( output, "Undefined (%08x)", op );
util::stream_format(stream, "Undefined (%08x)", op);
break;
}
break;
@ -490,70 +489,70 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x00f0)
{
case 0x0000:
output += sprintf( output, "ICALL" );
util::stream_format(stream, "ICALL");
break;
case 0x0010:
output += sprintf( output, "EICALL" );
util::stream_format(stream, "EICALL");
break;
default:
output += sprintf( output, "Undefined (%08x)", op );
util::stream_format(stream, "Undefined (%08x)", op);
break;
}
break;
case 0x000a:
output += sprintf( output, "DEC R%d", RD5(op) );
util::stream_format(stream, "DEC R%d", RD5(op));
break;
case 0x000c:
case 0x000d:
op <<= 16;
op |= oprom[pos++];
op |= oprom[pos++] << 8;
output += sprintf( output, "JMP 0x%06x", KCONST22(op) << 1 );
util::stream_format(stream, "JMP 0x%06x", KCONST22(op) << 1);
break;
case 0x000e:
case 0x000f:
op <<= 16;
op |= oprom[pos++];
op |= oprom[pos++] << 8;
output += sprintf( output, "CALL 0x%06x", KCONST22(op) << 1 );
util::stream_format(stream, "CALL 0x%06x", KCONST22(op) << 1);
break;
}
break;
case 0x0600:
output += sprintf( output, "ADIW R%d:R%d, 0x%02x", 24+(RD2(op) << 1)+1, 24+(RD2(op) << 1), KCONST6(op) );
util::stream_format(stream, "ADIW R%d:R%d, 0x%02x", 24+(RD2(op) << 1)+1, 24+(RD2(op) << 1), KCONST6(op));
break;
case 0x0700:
output += sprintf( output, "SBIW R%d:R%d, 0x%02x", 24+(RD2(op) << 1)+1, 24+(RD2(op) << 1), KCONST6(op) );
util::stream_format(stream, "SBIW R%d:R%d, 0x%02x", 24+(RD2(op) << 1)+1, 24+(RD2(op) << 1), KCONST6(op));
break;
case 0x0800:
if (ACONST5(op) < 0x20)
output += sprintf( output, "CBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
util::stream_format(stream, "CBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)]);
else
output += sprintf( output, "CBI 0x%02x, %d", ACONST5(op), RR3(op) );
util::stream_format(stream, "CBI 0x%02x, %d", ACONST5(op), RR3(op));
break;
case 0x0900:
if (ACONST5(op) < 0x20)
output += sprintf( output, "SBIC %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
util::stream_format(stream, "SBIC %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)]);
else
output += sprintf( output, "SBIC 0x%02x, %d", ACONST5(op), RR3(op) );
util::stream_format(stream, "SBIC 0x%02x, %d", ACONST5(op), RR3(op));
break;
case 0x0a00:
if (ACONST5(op) < 0x20)
output += sprintf( output, "SBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
util::stream_format(stream, "SBI %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)]);
else
output += sprintf( output, "SBI 0x%02x, %d", ACONST5(op), RR3(op) );
util::stream_format(stream, "SBI 0x%02x, %d", ACONST5(op), RR3(op));
break;
case 0x0b00:
if (ACONST5(op) < 0x20)
output += sprintf( output, "SBIS %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)] );
util::stream_format(stream, "SBIS %s, %s", register_names[ACONST5(op)], register_bit_names[ACONST5(op)][RR3(op)]);
else
output += sprintf( output, "SBIS 0x%02x, %d", ACONST5(op), RR3(op) );
util::stream_format(stream, "SBIS 0x%02x, %d", ACONST5(op), RR3(op));
break;
case 0x0c00:
case 0x0d00:
case 0x0e00:
case 0x0f00:
output += sprintf( output, "MUL R%d, R%d", RD5(op), RR5(op) );
util::stream_format(stream, "MUL R%d, R%d", RD5(op), RR5(op));
break;
}
break;
@ -561,29 +560,29 @@ CPU_DISASSEMBLE( avr8 )
if(op & 0x0800)
{
if (ACONST6(op) < 0x40 ) {
output += sprintf( output, "OUT %s, R%d", register_names[ACONST6(op)], RD5(op) );
util::stream_format(stream, "OUT %s, R%d", register_names[ACONST6(op)], RD5(op));
} else {
output += sprintf( output, "OUT 0x%02x, R%d", ACONST6(op), RD5(op) );
util::stream_format(stream, "OUT 0x%02x, R%d", ACONST6(op), RD5(op));
}
}
else
{
if (ACONST6(op) < 0x40 ) {
output += sprintf( output, "IN R%d, %s", RD5(op), register_names[ACONST6(op)] );
util::stream_format(stream, "IN R%d, %s", RD5(op), register_names[ACONST6(op)]);
} else {
output += sprintf( output, "IN R%d, 0x%02x", RD5(op), ACONST6(op) );
util::stream_format(stream, "IN R%d, 0x%02x", RD5(op), ACONST6(op));
}
}
break;
case 0xc000:
//I'm not sure if this is correct. why pc + ... : pc + 8 + ... ?
output += sprintf( output, "RJMP %08x", (((op & 0x0800) ? pc + ((op & 0x0fff) | 0xfffff000) : pc + 8 + (op & 0x0fff)) << 0) );
util::stream_format(stream, "RJMP %08x", (((op & 0x0800) ? pc + ((op & 0x0fff) | 0xfffff000) : pc + 8 + (op & 0x0fff)) << 0));
break;
case 0xd000:
output += sprintf( output, "RCALL %08x", (((op & 0x0800) ? ((op & 0x0fff) | 0xfffff000) : (op & 0x0fff)) << 1) );
util::stream_format(stream, "RCALL %08x", (((op & 0x0800) ? ((op & 0x0fff) | 0xfffff000) : (op & 0x0fff)) << 1));
break;
case 0xe000:
output += sprintf( output, "LDI R%d, 0x%02x", 16 + RD4(op), KCONST8(op) );
util::stream_format(stream, "LDI R%d, 0x%02x", 16 + RD4(op), KCONST8(op));
break;
case 0xf000:
switch(op & 0x0c00)
@ -592,28 +591,28 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x0007)
{
case 0x0000:
output += sprintf( output, "BRLO %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRLO %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0001:
output += sprintf( output, "BREQ %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BREQ %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0002:
output += sprintf( output, "BRMI %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRMI %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0003:
output += sprintf( output, "BRVS %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRVS %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0004:
output += sprintf( output, "BRLT %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRLT %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0005:
output += sprintf( output, "BRHS %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRHS %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0006:
output += sprintf( output, "BRTS %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRTS %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0007:
output += sprintf( output, "BRIE %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRIE %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
}
break;
@ -621,49 +620,49 @@ CPU_DISASSEMBLE( avr8 )
switch(op & 0x0007)
{
case 0x0000:
output += sprintf( output, "BRSH %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRSH %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0001:
output += sprintf( output, "BRNE %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRNE %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0002:
output += sprintf( output, "BRPL %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRPL %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0003:
output += sprintf( output, "BRVC %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRVC %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0004:
output += sprintf( output, "BRGE %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRGE %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0005:
output += sprintf( output, "BRHC %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRHC %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0006:
output += sprintf( output, "BRTC %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRTC %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
case 0x0007:
output += sprintf( output, "BRID %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1) );
util::stream_format(stream, "BRID %08x", (((op & 0x0200) ? (KCONST7(op) | 0xff80) : KCONST7(op)) << 1));
break;
}
break;
case 0x0800:
if(op & 0x0200)
{
output += sprintf( output, "BST R%d, %d", RD5(op), RR3(op) );
util::stream_format(stream, "BST R%d, %d", RD5(op), RR3(op));
}
else
{
output += sprintf( output, "BLD R%d, %d", RD5(op), RR3(op) );
util::stream_format(stream, "BLD R%d, %d", RD5(op), RR3(op));
}
break;
case 0x0c00:
if(op & 0x0200)
{
output += sprintf( output, "SBRS R%d, %d", RD5(op), RR3(op) );
util::stream_format(stream, "SBRS R%d, %d", RD5(op), RR3(op));
}
else
{
output += sprintf( output, "SBRC R%d, %d", RD5(op), RR3(op) );
util::stream_format(stream, "SBRC R%d, %d", RD5(op), RR3(op));
}
break;
}
@ -672,3 +671,13 @@ CPU_DISASSEMBLE( avr8 )
return pos | DASMFLAG_SUPPORTED;
}
CPU_DISASSEMBLE(avr8)
{
std::ostringstream stream;
offs_t result = internal_disasm_avr8(device, stream, pc, oprom, opram, options);
std::string stream_str = stream.str();
strcpy(buffer, stream_str.c_str());
return result;
}