From dae4b631d7de1da925e8dff8c4684d45c072743f Mon Sep 17 00:00:00 2001 From: "R. Belmont" Date: Wed, 27 Aug 2008 02:22:58 +0000 Subject: [PATCH] SH4, Naomi, and Hikaru updates [Samuele Zannoli] - Fixed SH-4 core to support multiple SH-4s - Fixed LDCSR instruction - Fixed SH-4 I/O ports - Skeleton Hikaru driver with memory maps and both SH-4s - Fixed JVS/Maple translation so Naomi 2 BIOS runs --- src/emu/cpu/sh4/sh4.c | 81 ++++++++++++++++++++------------------- src/emu/cpu/sh4/sh4comn.c | 9 ++--- src/emu/cpu/sh4/sh4comn.h | 4 +- src/mame/drivers/hikaru.c | 31 ++++++++++++++- src/mame/machine/dc.c | 1 + 5 files changed, 78 insertions(+), 48 deletions(-) diff --git a/src/emu/cpu/sh4/sh4.c b/src/emu/cpu/sh4/sh4.c index 66d2e34bc15..cda9e8b2a86 100644 --- a/src/emu/cpu/sh4/sh4.c +++ b/src/emu/cpu/sh4/sh4.c @@ -300,7 +300,7 @@ INLINE void ANDM(UINT32 i) sh4.ea = sh4.gbr + sh4.r[0]; temp = i & RB( sh4.ea ); WB( sh4.ea, temp ); - sh4_icount -= 2; + sh4.sh4_icount -= 2; } /* code cycles t-bit @@ -314,7 +314,7 @@ INLINE void BF(UINT32 d) INT32 disp = ((INT32)d << 24) >> 24; sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; change_pc(sh4.pc & AM); - sh4_icount -= 2; + sh4.sh4_icount -= 2; } } @@ -329,7 +329,7 @@ INLINE void BFS(UINT32 d) INT32 disp = ((INT32)d << 24) >> 24; sh4.delay = sh4.pc; sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4_icount--; + sh4.sh4_icount--; } } @@ -349,12 +349,12 @@ INLINE void BRA(UINT32 d) * NOP */ if (next_opcode == 0x0009) - sh4_icount %= 3; /* cycles for BRA $ and NOP taken (3) */ + sh4.sh4_icount %= 3; /* cycles for BRA $ and NOP taken (3) */ } #endif sh4.delay = sh4.pc; sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4_icount--; + sh4.sh4_icount--; } /* code cycles t-bit @@ -365,7 +365,7 @@ INLINE void BRAF(UINT32 m) { sh4.delay = sh4.pc; sh4.pc += sh4.r[m] + 2; - sh4_icount--; + sh4.sh4_icount--; } /* code cycles t-bit @@ -379,7 +379,7 @@ INLINE void BSR(UINT32 d) sh4.pr = sh4.pc + 2; sh4.delay = sh4.pc; sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4_icount--; + sh4.sh4_icount--; } /* code cycles t-bit @@ -391,7 +391,7 @@ INLINE void BSRF(UINT32 m) sh4.pr = sh4.pc + 2; sh4.delay = sh4.pc; sh4.pc += sh4.r[m] + 2; - sh4_icount--; + sh4.sh4_icount--; } /* code cycles t-bit @@ -405,7 +405,7 @@ INLINE void BT(UINT32 d) INT32 disp = ((INT32)d << 24) >> 24; sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; change_pc(sh4.pc & AM); - sh4_icount -= 2; + sh4.sh4_icount -= 2; } } @@ -420,7 +420,7 @@ INLINE void BTS(UINT32 d) INT32 disp = ((INT32)d << 24) >> 24; sh4.delay = sh4.pc; sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4_icount--; + sh4.sh4_icount--; } } @@ -732,7 +732,7 @@ INLINE void DMULS(UINT32 m, UINT32 n) } sh4.mach = Res2; sh4.macl = Res0; - sh4_icount--; + sh4.sh4_icount--; } /* DMULU.L Rm,Rn */ @@ -760,7 +760,7 @@ INLINE void DMULU(UINT32 m, UINT32 n) Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3; sh4.mach = Res2; sh4.macl = Res0; - sh4_icount--; + sh4.sh4_icount--; } /* DT Rn */ @@ -779,10 +779,10 @@ INLINE void DT(UINT32 n) */ if (next_opcode == 0x8bfd) { - while (sh4.r[n] > 1 && sh4_icount > 4) + while (sh4.r[n] > 1 && sh4.sh4_icount > 4) { sh4.r[n]--; - sh4_icount -= 4; /* cycles for DT (1) and BF taken (3) */ + sh4.sh4_icount -= 4; /* cycles for DT (1) and BF taken (3) */ } } } @@ -826,18 +826,21 @@ INLINE void JSR(UINT32 m) sh4.delay = sh4.pc; sh4.pr = sh4.pc + 2; sh4.pc = sh4.ea = sh4.r[m]; - sh4_icount--; + sh4.sh4_icount--; } /* LDC Rm,SR */ INLINE void LDCSR(UINT32 m) { +UINT32 reg; + + reg = sh4.r[m]; if ((Machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) sh4_syncronize_register_bank((sh4.sr & sRB) >> 29); if ((sh4.r[m] & sRB) != (sh4.sr & sRB)) sh4_change_register_bank(sh4.r[m] & sRB ? 1 : 0); - sh4.sr = sh4.r[m] & FLAGS; + sh4.sr = reg & FLAGS; sh4_exception_recompute(); } @@ -866,7 +869,7 @@ UINT32 old; if ((old & sRB) != (sh4.sr & sRB)) sh4_change_register_bank(sh4.sr & sRB ? 1 : 0); sh4.r[m] += 4; - sh4_icount -= 2; + sh4.sh4_icount -= 2; sh4_exception_recompute(); } @@ -876,7 +879,7 @@ INLINE void LDCMGBR(UINT32 m) sh4.ea = sh4.r[m]; sh4.gbr = RL( sh4.ea ); sh4.r[m] += 4; - sh4_icount -= 2; + sh4.sh4_icount -= 2; } /* LDC.L @Rm+,VBR */ @@ -885,7 +888,7 @@ INLINE void LDCMVBR(UINT32 m) sh4.ea = sh4.r[m]; sh4.vbr = RL( sh4.ea ); sh4.r[m] += 4; - sh4_icount -= 2; + sh4.sh4_icount -= 2; } /* LDS Rm,MACH */ @@ -1004,7 +1007,7 @@ INLINE void MAC_L(UINT32 m, UINT32 n) sh4.mach = Res2; sh4.macl = Res0; } - sh4_icount -= 2; + sh4.sh4_icount -= 2; } /* MAC.W @Rm+,@Rn+ */ @@ -1056,7 +1059,7 @@ INLINE void MAC_W(UINT32 m, UINT32 n) if (templ > sh4.macl) sh4.mach += 1; } - sh4_icount -= 2; + sh4.sh4_icount -= 2; } /* MOV Rm,Rn */ @@ -1337,7 +1340,7 @@ INLINE void MOVT(UINT32 n) INLINE void MULL(UINT32 m, UINT32 n) { sh4.macl = sh4.r[n] * sh4.r[m]; - sh4_icount--; + sh4.sh4_icount--; } /* MULS Rm,Rn */ @@ -1392,7 +1395,7 @@ INLINE void OR(UINT32 m, UINT32 n) INLINE void ORI(UINT32 i) { sh4.r[0] |= i; - sh4_icount -= 2; + sh4.sh4_icount -= 2; } /* OR.B #imm,@(R0,GBR) */ @@ -1452,7 +1455,7 @@ INLINE void RTE(void) if ((sh4.ssr & sRB) != (sh4.sr & sRB)) sh4_change_register_bank(sh4.ssr & sRB ? 1 : 0); sh4.sr = sh4.ssr; - sh4_icount--; + sh4.sh4_icount--; sh4_exception_recompute(); } @@ -1461,7 +1464,7 @@ INLINE void RTS(void) { sh4.delay = sh4.pc; sh4.pc = sh4.ea = sh4.pr; - sh4_icount--; + sh4.sh4_icount--; } /* SETT */ @@ -1538,7 +1541,7 @@ INLINE void SHLR16(UINT32 n) INLINE void SLEEP(void) { sh4.pc -= 2; - sh4_icount -= 2; + sh4.sh4_icount -= 2; /* Wait_for_exception; */ } @@ -1566,7 +1569,7 @@ INLINE void STCMSR(UINT32 n) sh4.r[n] -= 4; sh4.ea = sh4.r[n]; WL( sh4.ea, sh4.sr ); - sh4_icount--; + sh4.sh4_icount--; } /* STC.L GBR,@-Rn */ @@ -1575,7 +1578,7 @@ INLINE void STCMGBR(UINT32 n) sh4.r[n] -= 4; sh4.ea = sh4.r[n]; WL( sh4.ea, sh4.gbr ); - sh4_icount--; + sh4.sh4_icount--; } /* STC.L VBR,@-Rn */ @@ -1584,7 +1587,7 @@ INLINE void STCMVBR(UINT32 n) sh4.r[n] -= 4; sh4.ea = sh4.r[n]; WL( sh4.ea, sh4.vbr ); - sh4_icount--; + sh4.sh4_icount--; } /* STS MACH,Rn */ @@ -1716,7 +1719,7 @@ INLINE void TAS(UINT32 n) temp |= 0x80; /* Bus Lock disable */ WB( sh4.ea, temp ); - sh4_icount -= 3; + sh4.sh4_icount -= 3; } /* TRAPA #imm */ @@ -1742,7 +1745,7 @@ INLINE void TRAPA(UINT32 i) sh4.pc = sh4.vbr + 0x00000100; change_pc(sh4.pc & AM); - sh4_icount -= 7; + sh4.sh4_icount -= 7; } /* TST Rm,Rn */ @@ -1775,7 +1778,7 @@ INLINE void TSTM(UINT32 i) sh4.sr |= T; else sh4.sr &= ~T; - sh4_icount -= 2; + sh4.sh4_icount -= 2; } /* XOR Rm,Rn */ @@ -1801,7 +1804,7 @@ INLINE void XORM(UINT32 i) temp = RB( sh4.ea ); temp ^= imm; WB( sh4.ea, temp ); - sh4_icount -= 2; + sh4.sh4_icount -= 2; } /* XTRCT Rm,Rn */ @@ -1862,7 +1865,7 @@ INLINE void STCMRBANK(UINT32 m, UINT32 n) sh4.r[n] -= 4; sh4.ea = sh4.r[n]; WL( sh4.ea, sh4.rbnk[sh4.sr&sRB ? 0 : 1][m & 7]); - sh4_icount--; + sh4.sh4_icount--; } /* MOVCA.L R0,@Rn */ @@ -3313,7 +3316,7 @@ static void sh4_reset(void) /* Execute cycles - returns number of cycles actually run */ static int sh4_execute(int cycles) { - sh4_icount = cycles; + sh4.sh4_icount = cycles; if (sh4.cpu_off) return 0; @@ -3361,10 +3364,10 @@ static int sh4_execute(int cycles) { sh4_check_pending_irq("mame_sh4_execute"); } - sh4_icount--; - } while( sh4_icount > 0 ); + sh4.sh4_icount--; + } while( sh4.sh4_icount > 0 ); - return cycles - sh4_icount; + return cycles - sh4.sh4_icount; } /* Get registers, return context size */ @@ -3706,7 +3709,7 @@ void sh4_get_info(UINT32 state, cpuinfo *info) case CPUINFO_PTR_EXECUTE: info->execute = sh4_execute; break; case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = sh4_dasm; break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &sh4_icount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &sh4.sh4_icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ case CPUINFO_STR_NAME: strcpy(info->s, "SH-4"); break; diff --git a/src/emu/cpu/sh4/sh4comn.c b/src/emu/cpu/sh4/sh4comn.c index d3dcd678520..1fca0152af0 100644 --- a/src/emu/cpu/sh4/sh4comn.c +++ b/src/emu/cpu/sh4/sh4comn.c @@ -12,7 +12,6 @@ #include "sh4regs.h" #include "sh4comn.h" -int sh4_icount; SH4 sh4; static const int tcnt_div[8] = { 4, 16, 64, 256, 1024, 1, 1, 1 }; @@ -886,11 +885,11 @@ WRITE32_HANDLER( sh4_internal_w ) sh4.ioport16_direction &= 0xffff; sh4.ioport16_pullup = (sh4.ioport16_pullup | sh4.ioport16_direction) ^ 0xffff; if (sh4.m[BCR2] & 1) - io_write_dword_64le(SH4_IOPORT_16, sh4.m[PDTRA] & sh4.ioport16_direction); + io_write_dword_64le(SH4_IOPORT_16, (UINT64)(sh4.m[PDTRA] & sh4.ioport16_direction) | ((UINT64)sh4.m[PCTRA] << 16)); break; case PDTRA: if (sh4.m[BCR2] & 1) - io_write_dword_64le(SH4_IOPORT_16, sh4.m[PDTRA] & sh4.ioport16_direction); + io_write_dword_64le(SH4_IOPORT_16, (UINT64)(sh4.m[PDTRA] & sh4.ioport16_direction) | ((UINT64)sh4.m[PCTRA] << 16)); break; case PCTRB: sh4.ioport4_pullup = 0; @@ -902,11 +901,11 @@ WRITE32_HANDLER( sh4_internal_w ) sh4.ioport4_direction &= 0xf; sh4.ioport4_pullup = (sh4.ioport4_pullup | sh4.ioport4_direction) ^ 0xf; if (sh4.m[BCR2] & 1) - io_write_dword_64le(SH4_IOPORT_4, sh4.m[PDTRB] & sh4.ioport4_direction); + io_write_dword_64le(SH4_IOPORT_4, (sh4.m[PDTRB] & sh4.ioport4_direction) | (sh4.m[PCTRB] << 16)); break; case PDTRB: if (sh4.m[BCR2] & 1) - io_write_dword_64le(SH4_IOPORT_4, sh4.m[PDTRB] & sh4.ioport4_direction); + io_write_dword_64le(SH4_IOPORT_4, (sh4.m[PDTRB] & sh4.ioport4_direction) | (sh4.m[PCTRB] << 16)); break; case SCBRR2: diff --git a/src/emu/cpu/sh4/sh4comn.h b/src/emu/cpu/sh4/sh4comn.h index 30f6aba1d7c..80950c894d6 100644 --- a/src/emu/cpu/sh4/sh4comn.h +++ b/src/emu/cpu/sh4/sh4comn.h @@ -74,8 +74,9 @@ typedef struct emu_timer *rtc_timer; emu_timer *timer[3]; UINT32 refresh_timer_base; - int dma_timer_active[2]; + int dma_timer_active[4]; + int sh4_icount; int is_slave, cpu_number; int cpu_clock, bus_clock, pm_clock; int fpu_sz, fpu_pr; @@ -85,7 +86,6 @@ typedef struct void (*ftcsr_read_callback)(UINT32 data); } SH4; -extern int sh4_icount; extern SH4 sh4; enum diff --git a/src/mame/drivers/hikaru.c b/src/mame/drivers/hikaru.c index 3314b816e2a..788078cfa77 100644 --- a/src/mame/drivers/hikaru.c +++ b/src/mame/drivers/hikaru.c @@ -276,8 +276,33 @@ static INPUT_PORTS_START( hikaru ) INPUT_PORTS_END static ADDRESS_MAP_START( hikaru_map, ADDRESS_SPACE_PROGRAM, 64 ) - AM_RANGE(0x00000000, 0x001fffff) AM_ROM - AM_RANGE(0x0C000000, 0x0C00ffff) AM_RAM + AM_RANGE(0x00000000, 0x001FFFFF) AM_ROM AM_SHARE(1) + AM_RANGE(0x00400000, 0x004000FF) AM_NOP // unknown + AM_RANGE(0x00800000, 0x008000FF) AM_NOP // unknown + AM_RANGE(0x00830000, 0x00831FFF) AM_NOP // unknown + AM_RANGE(0x00838000, 0x008380ff) AM_NOP // unknown + AM_RANGE(0x0082F000, 0x0082F0ff) AM_NOP // unknown + AM_RANGE(0x00C00000, 0x00C002FF) AM_RAM // unknown nvram? + AM_RANGE(0x01000000, 0x010001FF) AM_NOP // unknown + AM_RANGE(0x02000000, 0x020000FF) AM_NOP // unknown + AM_RANGE(0x02710000, 0x027100FF) AM_NOP // unknown + AM_RANGE(0x03000000, 0x030000FF) AM_NOP // unknown + AM_RANGE(0x04000000, 0x040000FF) AM_NOP // unknown + AM_RANGE(0x0C000000, 0x0DFFFFFF) AM_RAM + AM_RANGE(0x14000000, 0x140000FF) AM_NOP // unknown + AM_RANGE(0x14004000, 0x140041FF) AM_RAM // unknown + AM_RANGE(0x15000000, 0x150000FF) AM_NOP // unknown + AM_RANGE(0x16001000, 0x160010FF) AM_RAM // unknown + AM_RANGE(0x1A000000, 0x1A0000FF) AM_NOP // unknown +ADDRESS_MAP_END + +static ADDRESS_MAP_START( hikaru_map_slave, ADDRESS_SPACE_PROGRAM, 64 ) + ADDRESS_MAP_UNMAP_HIGH + AM_RANGE(0x00000000, 0x001FFFFF) AM_ROM AM_SHARE(1) + AM_RANGE(0x0C000000, 0x0DFFFFFF) AM_RAM + AM_RANGE(0x10000000, 0x100000FF) AM_RAM + AM_RANGE(0x1A800000, 0x1A8000FF) AM_RAM + AM_RANGE(0x1B000000, 0x1B0001FF) AM_RAM ADDRESS_MAP_END @@ -288,6 +313,8 @@ static MACHINE_DRIVER_START( hikaru ) MDRV_CPU_PROGRAM_MAP(hikaru_map,0) // MDRV_CPU_IO_MAP(hikaru_port,0) // MDRV_CPU_VBLANK_INT("main", hikaru,vblank) + MDRV_CPU_ADD("slave", SH4, CPU_CLOCK) + MDRV_CPU_PROGRAM_MAP(hikaru_map_slave,0) // MDRV_MACHINE_START( hikaru ) // MDRV_MACHINE_RESET( hikaru ) diff --git a/src/mame/machine/dc.c b/src/mame/machine/dc.c index 762dbd37011..eac56a6f6e0 100644 --- a/src/mame/machine/dc.c +++ b/src/mame/machine/dc.c @@ -457,6 +457,7 @@ WRITE64_HANDLER( dc_maple_w ) maple0x86data2[pos+8] = 1; maple0x86data2[pos+1] = 0x8e; maple0x86data2[pos+9] = 1; + maple0x86data2[pos+5] = 0xe0; // 4 + 1 + 0x10 + ?,8e,addr,0,?,?,addr?,len,status,report1,jvsbytes... ddtdata.length=11; tocopy += 10;