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https://github.com/holub/mame
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m377xx: preliminary M37720 support [R. Belmont]
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@ -1,7 +1,7 @@
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// license:BSD-3-Clause
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// license:BSD-3-Clause
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// copyright-holders:R. Belmont, Karl Stenerud, hap
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// copyright-holders:R. Belmont, Karl Stenerud, hap
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/*
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/*
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Mitsubishi M37702/37710 CPU Emulator
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Mitsubishi M37702/37710/37720 CPU Emulator
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The 7700 series is based on the WDC 65C816 core, with the following
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The 7700 series is based on the WDC 65C816 core, with the following
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notable changes:
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notable changes:
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@ -65,6 +65,7 @@
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DEFINE_DEVICE_TYPE(M37702M2, m37702m2_device, "m37702m2", "M37702M2")
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DEFINE_DEVICE_TYPE(M37702M2, m37702m2_device, "m37702m2", "M37702M2")
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DEFINE_DEVICE_TYPE(M37702S1, m37702s1_device, "m37702s1", "M37702S1")
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DEFINE_DEVICE_TYPE(M37702S1, m37702s1_device, "m37702s1", "M37702S1")
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DEFINE_DEVICE_TYPE(M37710S4, m37710s4_device, "m37710s4", "M37710S4")
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DEFINE_DEVICE_TYPE(M37710S4, m37710s4_device, "m37710s4", "M37710S4")
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DEFINE_DEVICE_TYPE(M37720S1, m37720s1_device, "m37720s1", "M37720S1")
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// On-board RAM, ROM, and peripherals
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// On-board RAM, ROM, and peripherals
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@ -72,7 +73,7 @@ DEFINE_DEVICE_TYPE(M37710S4, m37710s4_device, "m37710s4", "M37710S4")
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// M37702M2: 512 bytes internal RAM, 16K internal mask ROM
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// M37702M2: 512 bytes internal RAM, 16K internal mask ROM
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// (M37702E2: same with EPROM instead of mask ROM)
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// (M37702E2: same with EPROM instead of mask ROM)
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DEVICE_ADDRESS_MAP_START( map, 16, m37702m2_device )
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DEVICE_ADDRESS_MAP_START( map, 16, m37702m2_device )
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AM_RANGE(0x000000, 0x00007f) AM_READWRITE(m37710_internal_word_r, m37710_internal_word_w)
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AM_RANGE(0x000000, 0x00007f) AM_READWRITE8(m37710_internal_r, m37710_internal_w, 0xffff)
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AM_RANGE(0x000080, 0x00027f) AM_RAM
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AM_RANGE(0x000080, 0x00027f) AM_RAM
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AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION(M37710_INTERNAL_ROM_REGION, 0)
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AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION(M37710_INTERNAL_ROM_REGION, 0)
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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@ -80,17 +81,23 @@ ADDRESS_MAP_END
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// M37702S1: 512 bytes internal RAM, no internal ROM
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// M37702S1: 512 bytes internal RAM, no internal ROM
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DEVICE_ADDRESS_MAP_START( map, 16, m37702s1_device )
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DEVICE_ADDRESS_MAP_START( map, 16, m37702s1_device )
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AM_RANGE(0x000000, 0x00007f) AM_READWRITE(m37710_internal_word_r, m37710_internal_word_w)
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AM_RANGE(0x000000, 0x00007f) AM_READWRITE8(m37710_internal_r, m37710_internal_w, 0xffff)
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AM_RANGE(0x000080, 0x00027f) AM_RAM
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AM_RANGE(0x000080, 0x00027f) AM_RAM
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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// M37710S4: 2048 bytes internal RAM, no internal ROM
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// M37710S4: 2048 bytes internal RAM, no internal ROM
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DEVICE_ADDRESS_MAP_START( map, 16, m37710s4_device )
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DEVICE_ADDRESS_MAP_START( map, 16, m37710s4_device )
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AM_RANGE(0x000000, 0x00007f) AM_READWRITE(m37710_internal_word_r, m37710_internal_word_w)
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AM_RANGE(0x000000, 0x00007f) AM_READWRITE8(m37710_internal_r, m37710_internal_w, 0xffff)
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AM_RANGE(0x000080, 0x00087f) AM_RAM
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AM_RANGE(0x000080, 0x00087f) AM_RAM
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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// M37720S1: 512 bytes internal RAM, no internal ROM, built-in DMA
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DEVICE_ADDRESS_MAP_START( map, 16, m37720s1_device )
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AM_RANGE(0x000000, 0x00007f) AM_READWRITE8(m37710_internal_r, m37710_internal_w, 0xffff)
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AM_RANGE(0x000080, 0x00027f) AM_RAM
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ADDRESS_MAP_END
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// many other combinations of RAM and ROM size exist
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// many other combinations of RAM and ROM size exist
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@ -125,9 +132,14 @@ m37710s4_device::m37710s4_device(const machine_config &mconfig, const char *tag,
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{
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{
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}
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}
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device_memory_interface::space_config_vector m37710_cpu_device::memory_space_config() const
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m37720s1_device::m37720s1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: m37710_cpu_device(mconfig, M37720S1, tag, owner, clock, address_map_delegate(FUNC(m37720s1_device::map), this))
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{
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{
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return space_config_vector {
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}
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std::vector<std::pair<int, const address_space_config *>> m37710_cpu_device::memory_space_config() const
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{
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return std::vector<std::pair<int, const address_space_config *>> {
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std::make_pair(AS_PROGRAM, &m_program_config),
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std::make_pair(AS_PROGRAM, &m_program_config),
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std::make_pair(AS_IO, &m_io_config)
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std::make_pair(AS_IO, &m_io_config)
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};
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};
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@ -138,22 +150,26 @@ device_memory_interface::space_config_vector m37710_cpu_device::memory_space_con
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const int m37710_cpu_device::m37710_irq_levels[M37710_LINE_MAX] =
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const int m37710_cpu_device::m37710_irq_levels[M37710_LINE_MAX] =
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{
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{
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// maskable
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// maskable
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0x70, // ADC 0
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0x6f, // DMA3 0
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0x73, // UART 1 XMIT 1
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0x6e, // DMA2 1
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0x74, // UART 1 RECV 2
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0x6d, // DMA1 2
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0x71, // UART 0 XMIT 3
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0x6c, // DMA0 3
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0x72, // UART 0 RECV 4
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0x70, // ADC 4
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0x7c, // Timer B2 5
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0x73, // UART 1 XMIT 5
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0x7b, // Timer B1 6
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0x74, // UART 1 RECV 6
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0x7a, // Timer B0 7
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0x71, // UART 0 XMIT 7
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0x79, // Timer A4 8
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0x72, // UART 0 RECV 8
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0x78, // Timer A3 9
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0x7c, // Timer B2 9
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0x77, // Timer A2 10
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0x7b, // Timer B1 10
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0x76, // Timer A1 11
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0x7a, // Timer B0 11
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0x75, // Timer A0 12
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0x79, // Timer A4 12
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0x7f, // IRQ 2 13
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0x78, // Timer A3 13
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0x7e, // IRQ 1 14
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0x77, // Timer A2 14
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0x7d, // IRQ 0 15
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0x76, // Timer A1 15
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0x75, // Timer A0 16
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0x7f, // IRQ 2 13
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0x7e, // IRQ 1 18
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0x7d, // IRQ 0 19
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// non-maskable
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// non-maskable
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0, // watchdog
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0, // watchdog
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@ -166,6 +182,10 @@ const int m37710_cpu_device::m37710_irq_levels[M37710_LINE_MAX] =
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const int m37710_cpu_device::m37710_irq_vectors[M37710_LINE_MAX] =
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const int m37710_cpu_device::m37710_irq_vectors[M37710_LINE_MAX] =
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{
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{
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// maskable
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// maskable
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0xffce, // DMA3
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0xffd0, // DMA2
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0xffd2, // DMA1
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0xffd4, // DMA0
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0xffd6, // A-D converter
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0xffd6, // A-D converter
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0xffd8, // UART1 transmit
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0xffd8, // UART1 transmit
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0xffda, // UART1 receive
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0xffda, // UART1 receive
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@ -205,7 +225,7 @@ const char *const m37710_cpu_device::m37710_rnames[128] =
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"Port P3 reg",
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"Port P3 reg",
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"Port P2 dir reg",
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"Port P2 dir reg",
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"Port P3 dir reg",
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"Port P3 dir reg",
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"Port P4 reg",
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"Port P4 reg", // 10 (0x0A) - ports 0, 1, 2, 3 don't exist on 37720
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"Port P5 reg",
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"Port P5 reg",
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"Port P4 dir reg",
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"Port P4 dir reg",
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"Port P5 dir reg",
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"Port P5 dir reg",
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@ -293,20 +313,20 @@ const char *const m37710_cpu_device::m37710_rnames[128] =
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"",
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"",
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"Watchdog reset", // 0x60
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"Watchdog reset", // 0x60
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"Watchdog frequency", // 0x61
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"Watchdog frequency", // 0x61
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"Real-time output control",
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"",
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"DRAM control",
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"",
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"Refresh timer",
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"",
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"DMAC control L",
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"DMAC control H",
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"",
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"",
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"",
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"",
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"",
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"DMA0 IRQ ctrl",
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"",
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"DMA1 IRQ ctrl",
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"",
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"DMA2 IRQ ctrl",
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"",
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"DMA3 IRQ ctrl",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"A/D IRQ ctrl",
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"A/D IRQ ctrl",
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"UART0 xmit IRQ ctrl", // 0x70
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"UART0 xmit IRQ ctrl", // 0x70
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"UART0 recv IRQ ctrl",
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"UART0 recv IRQ ctrl",
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@ -335,9 +355,11 @@ TIMER_CALLBACK_MEMBER( m37710_cpu_device::m37710_timer_cb )
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int which = param;
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int which = param;
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int curirq = M37710_LINE_TIMERA0 - which;
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int curirq = M37710_LINE_TIMERA0 - which;
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// logerror("Timer %d expired\n", which);
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m_timers[which]->adjust(m_reload[which], param);
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m_timers[which]->adjust(m_reload[which], param);
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m37710_set_irq_line(curirq, HOLD_LINE);
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m37710_set_irq_line(curirq, ASSERT_LINE);
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signal_interrupt_trigger();
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signal_interrupt_trigger();
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}
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}
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@ -465,7 +487,7 @@ void m37710_cpu_device::m37710_recalc_timer(int timer)
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}
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}
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}
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}
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uint8_t m37710_cpu_device::m37710_internal_r(int offset)
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READ8_MEMBER(m37710_cpu_device::m37710_internal_r)
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{
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{
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uint8_t d;
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uint8_t d;
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@ -574,7 +596,7 @@ uint8_t m37710_cpu_device::m37710_internal_r(int offset)
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return m_m37710_regs[offset];
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return m_m37710_regs[offset];
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}
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}
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void m37710_cpu_device::m37710_internal_w(int offset, uint8_t data)
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WRITE8_MEMBER(m37710_cpu_device::m37710_internal_w)
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{
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{
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int i;
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int i;
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uint8_t prevdata;
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uint8_t prevdata;
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@ -666,27 +688,6 @@ void m37710_cpu_device::m37710_internal_w(int offset, uint8_t data)
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}
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}
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}
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}
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READ16_MEMBER( m37710_cpu_device::m37710_internal_word_r )
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{
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uint16_t ret = 0;
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if (mem_mask & 0x00ff)
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ret |= m37710_internal_r(offset*2);
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if (mem_mask & 0xff00)
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ret |= m37710_internal_r(offset*2+1)<<8;
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return ret;
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}
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WRITE16_MEMBER( m37710_cpu_device::m37710_internal_word_w )
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{
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if (mem_mask & 0x00ff)
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m37710_internal_w(offset*2, data & 0xff);
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if (mem_mask & 0xff00)
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m37710_internal_w(offset*2+1, data>>8);
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}
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const m37710_cpu_device::opcode_func *m37710_cpu_device::m37710i_opcodes[4] =
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const m37710_cpu_device::opcode_func *m37710_cpu_device::m37710i_opcodes[4] =
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{
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{
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m37710i_opcodes_M0X0,
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m37710i_opcodes_M0X0,
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@ -792,7 +793,6 @@ void m37710_cpu_device::m37710i_update_irqs()
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// let's do it...
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// let's do it...
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// push PB, then PC, then status
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// push PB, then PC, then status
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CLK(13);
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CLK(13);
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// osd_printf_debug("taking IRQ %d: PC = %06x, SP = %04x, IPL %d\n", wantedIRQ, REG_PB | REG_PC, REG_S, m_ipl);
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m37710i_push_8(REG_PB>>16);
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m37710i_push_8(REG_PB>>16);
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m37710i_push_16(REG_PC);
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m37710i_push_16(REG_PC);
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m37710i_push_8(m_ipl);
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m37710i_push_8(m_ipl);
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@ -804,7 +804,6 @@ void m37710_cpu_device::m37710i_update_irqs()
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// then PB=0, PC=(vector)
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// then PB=0, PC=(vector)
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REG_PB = 0;
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REG_PB = 0;
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REG_PC = m37710_read_16(m37710_irq_vectors[wantedIRQ]);
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REG_PC = m37710_read_16(m37710_irq_vectors[wantedIRQ]);
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// logerror("IRQ @ %06x\n", REG_PB | REG_PC);
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}
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}
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}
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}
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@ -24,7 +24,11 @@ M37710 CPU Emulator v0.1
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enum
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enum
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{
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{
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// these interrupts are maskable
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// these interrupts are maskable
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M37710_LINE_ADC = 0,
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M37710_LINE_DMA3 = 0,
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M37710_LINE_DMA2,
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M37710_LINE_DMA1,
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M37710_LINE_DMA0,
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M37710_LINE_ADC,
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M37710_LINE_UART1XMIT,
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M37710_LINE_UART1XMIT,
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M37710_LINE_UART1RECV,
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M37710_LINE_UART1RECV,
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M37710_LINE_UART0XMIT,
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M37710_LINE_UART0XMIT,
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@ -93,8 +97,8 @@ enum
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class m37710_cpu_device : public cpu_device
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class m37710_cpu_device : public cpu_device
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{
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{
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public:
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public:
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DECLARE_READ16_MEMBER( m37710_internal_word_r );
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DECLARE_READ8_MEMBER( m37710_internal_r );
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DECLARE_WRITE16_MEMBER( m37710_internal_word_w );
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DECLARE_WRITE8_MEMBER( m37710_internal_w );
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protected:
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protected:
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// construction/destruction
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// construction/destruction
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@ -112,7 +116,7 @@ protected:
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virtual void execute_set_input(int inputnum, int state) override;
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virtual void execute_set_input(int inputnum, int state) override;
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// device_memory_interface overrides
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// device_memory_interface overrides
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virtual space_config_vector memory_space_config() const override;
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virtual std::vector<std::pair<int, const address_space_config *>> memory_space_config() const override;
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// device_state_interface overrides
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// device_state_interface overrides
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virtual void state_import(const device_state_entry &entry) override;
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virtual void state_import(const device_state_entry &entry) override;
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@ -172,6 +176,10 @@ private:
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uint8_t m_m37710_regs[128];
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uint8_t m_m37710_regs[128];
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attotime m_reload[8];
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attotime m_reload[8];
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emu_timer *m_timers[8];
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emu_timer *m_timers[8];
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uint32_t m_dma0_src, m_dma0_dst, m_dma0_cnt, m_dma0_mode;
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uint32_t m_dma1_src, m_dma1_dst, m_dma1_cnt, m_dma1_mode;
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uint32_t m_dma2_src, m_dma2_dst, m_dma2_cnt, m_dma2_mode;
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uint32_t m_dma3_src, m_dma3_dst, m_dma3_cnt, m_dma3_mode;
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// for debugger
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// for debugger
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uint32_t m_debugger_pc;
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uint32_t m_debugger_pc;
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@ -2038,10 +2046,19 @@ protected:
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DECLARE_ADDRESS_MAP(map, 16);
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DECLARE_ADDRESS_MAP(map, 16);
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};
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};
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class m37720s1_device : public m37710_cpu_device
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{
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public:
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// construction/destruction
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m37720s1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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DECLARE_ADDRESS_MAP(map, 16);
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};
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DECLARE_DEVICE_TYPE(M37702M2, m37702m2_device)
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DECLARE_DEVICE_TYPE(M37702M2, m37702m2_device)
|
||||||
DECLARE_DEVICE_TYPE(M37702S1, m37702s1_device)
|
DECLARE_DEVICE_TYPE(M37702S1, m37702s1_device)
|
||||||
DECLARE_DEVICE_TYPE(M37710S4, m37710s4_device)
|
DECLARE_DEVICE_TYPE(M37710S4, m37710s4_device)
|
||||||
|
DECLARE_DEVICE_TYPE(M37720S1, m37720s1_device)
|
||||||
|
|
||||||
|
|
||||||
/* ======================================================================== */
|
/* ======================================================================== */
|
||||||
|
@ -2508,6 +2508,10 @@ TABLE_FUNCTION(void, set_line, (int line, int state))
|
|||||||
case M37710_LINE_IRQ2:
|
case M37710_LINE_IRQ2:
|
||||||
case M37710_LINE_IRQ1:
|
case M37710_LINE_IRQ1:
|
||||||
case M37710_LINE_IRQ0:
|
case M37710_LINE_IRQ0:
|
||||||
|
case M37710_LINE_DMA0:
|
||||||
|
case M37710_LINE_DMA1:
|
||||||
|
case M37710_LINE_DMA2:
|
||||||
|
case M37710_LINE_DMA3:
|
||||||
switch(state)
|
switch(state)
|
||||||
{
|
{
|
||||||
case CLEAR_LINE:
|
case CLEAR_LINE:
|
||||||
|
Loading…
Reference in New Issue
Block a user