[CDI] Modernized CD-i and removed tag lookups [MooglyGuy]
This commit is contained in:
Ryan Holtz
parent
a4008406f8
commit
db398d6f0e
@ -61,10 +61,9 @@ static ADDRESS_MAP_START( cdimono1_mem, AS_PROGRAM, 16, cdi_state )
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#if ENABLE_UART_PRINTING
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AM_RANGE(0x00301400, 0x00301403) AM_READ_LEGACY(uart_loopback_enable)
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#endif
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AM_RANGE(0x00300000, 0x00303bff) AM_DEVREADWRITE_LEGACY("cdic", cdic_ram_r, cdic_ram_w)
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//AM_RANGE(0x00300000, 0x00303bff) AM_RAM AM_SHARE("cdic_regs.ram")
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AM_RANGE(0x00303c00, 0x00303fff) AM_DEVREADWRITE_LEGACY("cdic", cdic_r, cdic_w)
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AM_RANGE(0x00310000, 0x00317fff) AM_DEVREADWRITE_LEGACY("slave", slave_r, slave_w)
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AM_RANGE(0x00300000, 0x00303bff) AM_DEVREADWRITE("cdic", cdicdic_device, ram_r, ram_w)
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AM_RANGE(0x00303c00, 0x00303fff) AM_DEVREADWRITE("cdic", cdicdic_device, regs_r, regs_w)
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AM_RANGE(0x00310000, 0x00317fff) AM_DEVREADWRITE("slave", cdislave_device, slave_r, slave_w)
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//AM_RANGE(0x00318000, 0x0031ffff) AM_NOP
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AM_RANGE(0x00320000, 0x00323fff) AM_DEVREADWRITE8_LEGACY("mk48t08", timekeeper_r, timekeeper_w, 0xff00) /* nvram (only low bytes used) */
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AM_RANGE(0x00400000, 0x0047ffff) AM_ROM AM_REGION("maincpu", 0)
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@ -72,7 +71,7 @@ static ADDRESS_MAP_START( cdimono1_mem, AS_PROGRAM, 16, cdi_state )
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//AM_RANGE(0x00500000, 0x0057ffff) AM_RAM
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AM_RANGE(0x00500000, 0x00ffffff) AM_NOP
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//AM_RANGE(0x00e00000, 0x00efffff) AM_RAM // DVC
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AM_RANGE(0x80000000, 0x8000807f) AM_READWRITE_LEGACY(scc68070_periphs_r, scc68070_periphs_w)
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AM_RANGE(0x80000000, 0x8000807f) AM_DEVREADWRITE("scc68070", cdi68070_device, periphs_r, periphs_w)
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ADDRESS_MAP_END
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/*************************
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@ -81,48 +80,47 @@ ADDRESS_MAP_END
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INPUT_CHANGED_MEMBER(cdi_state::mcu_input)
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{
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scc68070_regs_t *scc68070 = &m_scc68070_regs;
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bool send = false;
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switch((FPTR)param)
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{
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case 0x39:
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if(ioport("INPUT1")->read() & 0x01) send = true;
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if(m_input1->read() & 0x01) send = true;
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break;
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case 0x37:
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if(ioport("INPUT1")->read() & 0x02) send = true;
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if(m_input1->read() & 0x02) send = true;
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break;
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case 0x31:
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if(ioport("INPUT1")->read() & 0x04) send = true;
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if(m_input1->read() & 0x04) send = true;
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break;
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case 0x32:
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if(ioport("INPUT1")->read() & 0x08) send = true;
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if(m_input1->read() & 0x08) send = true;
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break;
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case 0x33:
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if(ioport("INPUT1")->read() & 0x10) send = true;
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if(m_input1->read() & 0x10) send = true;
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break;
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case 0x30:
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if(ioport("INPUT2")->read() & 0x01) send = true;
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if(m_input2->read() & 0x01) send = true;
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break;
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case 0x38:
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if(ioport("INPUT2")->read() & 0x02) send = true;
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if(m_input2->read() & 0x02) send = true;
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break;
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case 0x34:
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if(ioport("INPUT2")->read() & 0x04) send = true;
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if(m_input2->read() & 0x04) send = true;
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break;
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case 0x35:
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if(ioport("INPUT2")->read() & 0x08) send = true;
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if(m_input2->read() & 0x08) send = true;
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break;
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case 0x36:
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if(ioport("INPUT2")->read() & 0x10) send = true;
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if(m_input2->read() & 0x10) send = true;
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break;
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}
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if(send)
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{
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UINT8 data = (UINT8)((FPTR)param & 0x000000ff);
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scc68070_quizard_rx(machine(), scc68070, data);
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m_scc->quizard_rx(data);
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}
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}
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@ -191,7 +189,11 @@ INPUT_PORTS_END
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void cdi_state::machine_start()
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{
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scc68070_register_globals(machine(), &m_scc68070_regs);
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}
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INTERRUPT_GEN_MEMBER( cdi_state::mcu_frame )
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{
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m_scc->mcu_frame();
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}
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MACHINE_RESET_MEMBER(cdi_state,cdi)
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@ -201,9 +203,7 @@ MACHINE_RESET_MEMBER(cdi_state,cdi)
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//device_t *cdrom_dev = machine().device("cdrom");
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memcpy(dst, src, 0x8);
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scc68070_init(machine(), &m_scc68070_regs);
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machine().device("maincpu")->reset();
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m_maincpu->reset();
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m_dmadac[0] = machine().device<dmadac_sound_device>("dac1");
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m_dmadac[1] = machine().device<dmadac_sound_device>("dac2");
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@ -213,16 +213,16 @@ MACHINE_RESET_MEMBER(cdi_state,quizrd12)
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{
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MACHINE_RESET_CALL_MEMBER( cdi );
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scc68070_set_quizard_mcu_value(machine(), 0x021f);
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scc68070_set_quizard_mcu_ack(machine(), 0x5a);
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m_scc->set_quizard_mcu_value(0x021f);
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m_scc->set_quizard_mcu_ack(0x5a);
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}
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MACHINE_RESET_MEMBER(cdi_state,quizrd17)
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{
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MACHINE_RESET_CALL_MEMBER( cdi );
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scc68070_set_quizard_mcu_value(machine(), 0x021f);
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scc68070_set_quizard_mcu_ack(machine(), 0x5a);
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m_scc->set_quizard_mcu_value(0x021f);
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m_scc->set_quizard_mcu_ack(0x5a);
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}
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/* Untested - copied from quizrd17 */
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@ -230,8 +230,8 @@ MACHINE_RESET_MEMBER(cdi_state,quizrd18)
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{
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MACHINE_RESET_CALL_MEMBER( cdi );
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scc68070_set_quizard_mcu_value(machine(), 0x021f);
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scc68070_set_quizard_mcu_ack(machine(), 0x5a);
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m_scc->set_quizard_mcu_value(0x021f);
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m_scc->set_quizard_mcu_ack(0x5a);
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}
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MACHINE_RESET_MEMBER(cdi_state,quizrd22)
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@ -242,8 +242,8 @@ MACHINE_RESET_MEMBER(cdi_state,quizrd22)
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// 0x001: French
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// 0x188: German
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scc68070_set_quizard_mcu_value(machine(), 0x188);
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scc68070_set_quizard_mcu_ack(machine(), 0x59);
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m_scc->set_quizard_mcu_value(0x188);
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m_scc->set_quizard_mcu_ack(0x59);
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}
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/* Untested - copied from quizrd22 */
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@ -255,16 +255,16 @@ MACHINE_RESET_MEMBER(cdi_state,quizrd23)
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// 0x001: French
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// 0x188: German
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scc68070_set_quizard_mcu_value(machine(), 0x188);
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scc68070_set_quizard_mcu_ack(machine(), 0x59);
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m_scc->set_quizard_mcu_value(0x188);
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m_scc->set_quizard_mcu_ack(0x59);
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}
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MACHINE_RESET_MEMBER(cdi_state,quizrd32)
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{
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MACHINE_RESET_CALL_MEMBER( cdi );
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scc68070_set_quizard_mcu_value(machine(), 0x00ae);
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scc68070_set_quizard_mcu_ack(machine(), 0x58);
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m_scc->set_quizard_mcu_value(0x00ae);
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m_scc->set_quizard_mcu_ack(0x58);
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}
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/* Untested - copied from quizrd32 */
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@ -272,8 +272,8 @@ MACHINE_RESET_MEMBER(cdi_state,quizrd34)
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{
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MACHINE_RESET_CALL_MEMBER( cdi );
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scc68070_set_quizard_mcu_value(machine(), 0x00ae);
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scc68070_set_quizard_mcu_ack(machine(), 0x58);
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m_scc->set_quizard_mcu_value(0x00ae);
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m_scc->set_quizard_mcu_ack(0x58);
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}
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/* Untested - copied from quizrr41 */
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@ -281,26 +281,26 @@ MACHINE_RESET_MEMBER(cdi_state,quizrr40)
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{
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MACHINE_RESET_CALL_MEMBER( cdi );
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//scc68070_set_quizard_mcu_value(machine(), 0x0139);
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scc68070_set_quizard_mcu_value(machine(), 0x011f);
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scc68070_set_quizard_mcu_ack(machine(), 0x57);
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//m_scc->set_quizard_mcu_value(0x0139);
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m_scc->set_quizard_mcu_value(0x011f);
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m_scc->set_quizard_mcu_ack(0x57);
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}
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MACHINE_RESET_MEMBER(cdi_state,quizrr41)
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{
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MACHINE_RESET_CALL_MEMBER( cdi );
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//scc68070_set_quizard_mcu_value(machine(), 0x0139);
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scc68070_set_quizard_mcu_value(machine(), 0x011f);
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scc68070_set_quizard_mcu_ack(machine(), 0x57);
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//m_scc->set_quizard_mcu_value(0x0139);
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m_scc->set_quizard_mcu_value(0x011f);
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m_scc->set_quizard_mcu_ack(0x57);
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}
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MACHINE_RESET_MEMBER(cdi_state,quizrr42)
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{
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MACHINE_RESET_CALL_MEMBER( cdi );
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scc68070_set_quizard_mcu_value(machine(), 0x01ae);
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scc68070_set_quizard_mcu_ack(machine(), 0x57);
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m_scc->set_quizard_mcu_value(0x01ae);
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m_scc->set_quizard_mcu_ack(0x57);
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}
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static DEVICE_IMAGE_DISPLAY_INFO(cdi_cdinfo)
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@ -343,10 +343,9 @@ static MACHINE_CONFIG_START( cdi, cdi_state )
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MCFG_DEFAULT_LAYOUT(layout_cdi)
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MCFG_CDICDIC_ADD( "cdic" )
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MCFG_CDISLAVE_ADD( "slave" )
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MCFG_CDI68070_ADD("scc68070")
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MCFG_CDICDIC_ADD("cdic")
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MCFG_CDISLAVE_ADD("slave")
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/* sound hardware */
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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@ -384,7 +383,7 @@ MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( quizard, cdi_base )
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MCFG_CPU_MODIFY("maincpu")
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MCFG_CPU_PROGRAM_MAP(cdimono1_mem)
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MCFG_CPU_VBLANK_INT("screen", scc68070_mcu_frame)
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MCFG_CPU_VBLANK_INT_DRIVER("screen", cdi_state, mcu_frame)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( quizrd12, quizard )
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@ -16,19 +16,40 @@ class cdi_state : public driver_device
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{
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public:
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cdi_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag) ,
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_planea(*this, "planea"),
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m_planeb(*this, "planeb"){ }
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m_planeb(*this, "planeb"),
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m_input1(*this, "INPUT1"),
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m_input2(*this, "INPUT2"),
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m_mousex(*this, "MOUSEX"),
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m_mousey(*this, "MOUSEY"),
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m_mousebtn(*this, "MOUSEBTN"),
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m_slave(*this, "slave"),
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m_scc(*this, "scc68070"),
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m_cdic(*this, "cdic"),
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m_cdda(*this, "cdda"){ }
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required_device<cpu_device> m_maincpu;
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required_shared_ptr<UINT16> m_planea;
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required_shared_ptr<UINT16> m_planeb;
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optional_device<ioport_port> m_input1;
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optional_device<ioport_port> m_input2;
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required_ioport m_mousex;
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required_ioport m_mousey;
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required_ioport m_mousebtn;
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required_device<cdislave_device> m_slave;
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required_device<cdi68070_device> m_scc;
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required_device<cdicdic_device> m_cdic;
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required_device<cdda_device> m_cdda;
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dmadac_sound_device *m_dmadac[2];
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INTERRUPT_GEN_MEMBER( mcu_frame );
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UINT8 m_timer_set;
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emu_timer *m_test_timer;
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bitmap_rgb32 m_lcdbitmap;
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scc68070_regs_t m_scc68070_regs;
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mcd212_regs_t m_mcd212_regs;
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mcd212_ab_t m_mcd212_ab;
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DECLARE_INPUT_CHANGED_MEMBER(mcu_input);
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File diff suppressed because it is too large
Load Diff
@ -19,25 +19,11 @@ TODO:
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*******************************************************************************/
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#ifndef _MACHINE_CDI070_H_
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#define _MACHINE_CDI070_H_
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#ifndef _MACHINE_CDI68070_H_
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#define _MACHINE_CDI68070_H_
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#include "emu.h"
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struct scc68070_i2c_regs_t
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{
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UINT8 reserved0;
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UINT8 data_register;
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UINT8 reserved1;
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UINT8 address_register;
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UINT8 reserved2;
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UINT8 status_register;
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UINT8 reserved3;
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UINT8 control_register;
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UINT8 reserved;
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UINT8 clock_control_register;
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};
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#define ISR_MST 0x80 // Master
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#define ISR_TRX 0x40 // Transmitter
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#define ISR_BB 0x20 // Busy
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@ -47,30 +33,6 @@ struct scc68070_i2c_regs_t
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#define ISR_AD0 0x02 // Address Zero
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#define ISR_LRB 0x01 // Last Received Bit
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struct scc68070_uart_regs_t
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{
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UINT8 reserved0;
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UINT8 mode_register;
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UINT8 reserved1;
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UINT8 status_register;
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UINT8 reserved2;
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UINT8 clock_select;
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UINT8 reserved3;
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UINT8 command_register;
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UINT8 reserved4;
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UINT8 transmit_holding_register;
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UINT8 reserved5;
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UINT8 receive_holding_register;
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INT16 receive_pointer;
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UINT8 receive_buffer[32768];
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emu_timer* rx_timer;
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INT16 transmit_pointer;
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UINT8 transmit_buffer[32768];
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emu_timer* tx_timer;
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};
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#define UMR_OM 0xc0
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#define UMR_OM_NORMAL 0x00
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#define UMR_OM_ECHO 0x40
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@ -90,17 +52,6 @@ struct scc68070_uart_regs_t
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#define USR_TXRDY 0x04
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#define USR_RXRDY 0x01
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struct scc68070_timer_regs_t
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{
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UINT8 timer_status_register;
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UINT8 timer_control_register;
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UINT16 reload_register;
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UINT16 timer0;
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UINT16 timer1;
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UINT16 timer2;
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emu_timer* timer0_timer;
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};
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#define TSR_OV0 0x80
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#define TSR_MA1 0x40
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#define TSR_CAP1 0x20
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@ -130,31 +81,6 @@ struct scc68070_timer_regs_t
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#define TCR_M2_CAPTURE 0x02
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#define TCR_M2_COUNT 0x03
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struct scc68070_dma_channel_t
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{
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UINT8 channel_status;
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UINT8 channel_error;
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UINT8 reserved0[2];
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UINT8 device_control;
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UINT8 operation_control;
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UINT8 sequence_control;
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UINT8 channel_control;
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UINT8 reserved1[3];
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UINT16 transfer_counter;
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UINT32 memory_address_counter;
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UINT8 reserved2[4];
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UINT32 device_address_counter;
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UINT8 reserved3[40];
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};
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#define CSR_COC 0x80
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#define CSR_NDT 0x20
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#define CSR_ERR 0x10
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@ -193,61 +119,186 @@ struct scc68070_dma_channel_t
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#define CCR_INE 0x08
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#define CCR_IPL 0x07
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struct scc68070_dma_regs_t
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//**************************************************************************
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// INTERFACE CONFIGURATION MACROS
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//**************************************************************************
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#define MCFG_CDI68070_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, MACHINE_CDI68070, 0)
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#define MCFG_CDI68070_REPLACE(_tag) \
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MCFG_DEVICE_REPLACE(_tag, MACHINE_CDI68070, 0)
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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// ======================> cdi68070_device
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|
||||
class cdi68070_device : public device_t
|
||||
{
|
||||
scc68070_dma_channel_t channel[2];
|
||||
public:
|
||||
// construction/destruction
|
||||
cdi68070_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// external callbacks
|
||||
void init();
|
||||
void uart_rx(UINT8 data);
|
||||
void uart_tx(UINT8 data);
|
||||
|
||||
// UART Access for Quizard
|
||||
void set_quizard_mcu_value(UINT16 value);
|
||||
void set_quizard_mcu_ack(UINT8 ack);
|
||||
void quizard_rx(UINT8 data);
|
||||
|
||||
void mcu_frame();
|
||||
|
||||
DECLARE_READ16_MEMBER(periphs_r);
|
||||
DECLARE_WRITE16_MEMBER(periphs_w);
|
||||
|
||||
TIMER_CALLBACK_MEMBER( timer0_callback );
|
||||
TIMER_CALLBACK_MEMBER( rx_callback );
|
||||
TIMER_CALLBACK_MEMBER( tx_callback );
|
||||
|
||||
// register structures
|
||||
struct i2c_regs_t
|
||||
{
|
||||
UINT8 reserved0;
|
||||
UINT8 data_register;
|
||||
UINT8 reserved1;
|
||||
UINT8 address_register;
|
||||
UINT8 reserved2;
|
||||
UINT8 status_register;
|
||||
UINT8 reserved3;
|
||||
UINT8 control_register;
|
||||
UINT8 reserved;
|
||||
UINT8 clock_control_register;
|
||||
};
|
||||
|
||||
struct uart_regs_t
|
||||
{
|
||||
UINT8 reserved0;
|
||||
UINT8 mode_register;
|
||||
UINT8 reserved1;
|
||||
UINT8 status_register;
|
||||
UINT8 reserved2;
|
||||
UINT8 clock_select;
|
||||
UINT8 reserved3;
|
||||
UINT8 command_register;
|
||||
UINT8 reserved4;
|
||||
UINT8 transmit_holding_register;
|
||||
UINT8 reserved5;
|
||||
UINT8 receive_holding_register;
|
||||
|
||||
INT16 receive_pointer;
|
||||
UINT8 receive_buffer[32768];
|
||||
emu_timer* rx_timer;
|
||||
|
||||
INT16 transmit_pointer;
|
||||
UINT8 transmit_buffer[32768];
|
||||
emu_timer* tx_timer;
|
||||
};
|
||||
|
||||
struct timer_regs_t
|
||||
{
|
||||
UINT8 timer_status_register;
|
||||
UINT8 timer_control_register;
|
||||
UINT16 reload_register;
|
||||
UINT16 timer0;
|
||||
UINT16 timer1;
|
||||
UINT16 timer2;
|
||||
emu_timer* timer0_timer;
|
||||
};
|
||||
|
||||
struct dma_channel_t
|
||||
{
|
||||
UINT8 channel_status;
|
||||
UINT8 channel_error;
|
||||
|
||||
UINT8 reserved0[2];
|
||||
|
||||
UINT8 device_control;
|
||||
UINT8 operation_control;
|
||||
UINT8 sequence_control;
|
||||
UINT8 channel_control;
|
||||
|
||||
UINT8 reserved1[3];
|
||||
|
||||
UINT16 transfer_counter;
|
||||
|
||||
UINT32 memory_address_counter;
|
||||
|
||||
UINT8 reserved2[4];
|
||||
|
||||
UINT32 device_address_counter;
|
||||
|
||||
UINT8 reserved3[40];
|
||||
};
|
||||
|
||||
struct dma_regs_t
|
||||
{
|
||||
dma_channel_t channel[2];
|
||||
};
|
||||
|
||||
struct mmu_desc_t
|
||||
{
|
||||
UINT16 attr;
|
||||
UINT16 length;
|
||||
UINT8 undefined;
|
||||
UINT8 segment;
|
||||
UINT16 base;
|
||||
};
|
||||
|
||||
struct mmu_regs_t
|
||||
{
|
||||
UINT8 status;
|
||||
UINT8 control;
|
||||
|
||||
UINT8 reserved[0x3e];
|
||||
|
||||
mmu_desc_t desc[8];
|
||||
};
|
||||
|
||||
dma_regs_t& dma() { return m_dma; }
|
||||
|
||||
UINT16 get_lir() { return m_lir; }
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
private:
|
||||
|
||||
void uart_rx_check();
|
||||
void uart_tx_check();
|
||||
void set_timer_callback(int channel);
|
||||
|
||||
// internal state
|
||||
emu_timer *m_interrupt_timer;
|
||||
|
||||
UINT16 m_seeds[10];
|
||||
UINT8 m_state[8];
|
||||
|
||||
UINT16 m_mcu_value;
|
||||
UINT8 m_mcu_ack;
|
||||
|
||||
UINT16 m_lir;
|
||||
UINT8 m_picr1;
|
||||
UINT8 m_picr2;
|
||||
|
||||
i2c_regs_t m_i2c;
|
||||
uart_regs_t m_uart;
|
||||
timer_regs_t m_timers;
|
||||
dma_regs_t m_dma;
|
||||
mmu_regs_t m_mmu;
|
||||
|
||||
// non-static internal members
|
||||
void quizard_calculate_state();
|
||||
void quizard_set_seeds(UINT8 *rx);
|
||||
void quizard_handle_byte_tx();
|
||||
};
|
||||
|
||||
struct scc68070_mmu_desc_t
|
||||
{
|
||||
UINT16 attr;
|
||||
UINT16 length;
|
||||
UINT8 undefined;
|
||||
UINT8 segment;
|
||||
UINT16 base;
|
||||
};
|
||||
// device type definition
|
||||
extern const device_type MACHINE_CDI68070;
|
||||
|
||||
struct scc68070_mmu_regs_t
|
||||
{
|
||||
UINT8 status;
|
||||
UINT8 control;
|
||||
|
||||
UINT8 reserved[0x3e];
|
||||
|
||||
scc68070_mmu_desc_t desc[8];
|
||||
};
|
||||
|
||||
struct scc68070_regs_t
|
||||
{
|
||||
UINT16 lir;
|
||||
UINT8 picr1;
|
||||
UINT8 picr2;
|
||||
|
||||
scc68070_i2c_regs_t i2c;
|
||||
scc68070_uart_regs_t uart;
|
||||
scc68070_timer_regs_t timers;
|
||||
scc68070_dma_regs_t dma;
|
||||
scc68070_mmu_regs_t mmu;
|
||||
};
|
||||
|
||||
// Member functions
|
||||
TIMER_CALLBACK( scc68070_timer0_callback );
|
||||
TIMER_CALLBACK( scc68070_rx_callback );
|
||||
TIMER_CALLBACK( scc68070_tx_callback );
|
||||
DECLARE_READ16_HANDLER( scc68070_periphs_r );
|
||||
DECLARE_WRITE16_HANDLER( scc68070_periphs_w );
|
||||
//DECLARE_READ16_HANDLER( uart_loopback_enable );
|
||||
|
||||
void scc68070_init(running_machine &machine, scc68070_regs_t *scc68070);
|
||||
void scc68070_uart_rx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data);
|
||||
void scc68070_uart_tx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data);
|
||||
void scc68070_register_globals(running_machine &machine, scc68070_regs_t *scc68070);
|
||||
|
||||
// UART Access for Quizard
|
||||
void scc68070_set_quizard_mcu_value(running_machine &machine, UINT16 value);
|
||||
void scc68070_set_quizard_mcu_ack(running_machine &machine, UINT8 ack);
|
||||
void scc68070_quizard_rx(running_machine &machine, scc68070_regs_t *scc68070, UINT8 data);
|
||||
|
||||
INTERRUPT_GEN( scc68070_mcu_frame );
|
||||
|
||||
#endif // _MACHINE_CDI070_H_
|
||||
#endif // _MACHINE_CDI68070_H_
|
||||
|
||||
@ -530,14 +530,15 @@ void cdicdic_device::decode_audio_sector(const UINT8 *xa, INT32 triggered)
|
||||
}
|
||||
|
||||
// After an appropriate delay for decoding to take place...
|
||||
TIMER_CALLBACK( cdicdic_device::audio_sample_trigger )
|
||||
TIMER_CALLBACK_MEMBER( cdicdic_device::audio_sample_trigger )
|
||||
{
|
||||
cdicdic_device *cdic = static_cast<cdicdic_device *>(machine.device("cdic"));
|
||||
cdic->sample_trigger();
|
||||
sample_trigger();
|
||||
}
|
||||
|
||||
void cdicdic_device::sample_trigger()
|
||||
{
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
if(m_decode_addr == 0xffff)
|
||||
{
|
||||
verboselog(machine(), 0, "Decode stop requested, stopping playback\n" );
|
||||
@ -553,8 +554,8 @@ void cdicdic_device::sample_trigger()
|
||||
|
||||
// Set the CDIC interrupt line
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for soundmap decode\n" );
|
||||
machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -590,14 +591,15 @@ void cdicdic_device::sample_trigger()
|
||||
}
|
||||
}
|
||||
|
||||
TIMER_CALLBACK( cdicdic_device::trigger_readback_int )
|
||||
TIMER_CALLBACK_MEMBER( cdicdic_device::trigger_readback_int )
|
||||
{
|
||||
cdicdic_device *cdic = static_cast<cdicdic_device *>(machine.device("cdic"));
|
||||
cdic->process_delayed_command();
|
||||
process_delayed_command();
|
||||
}
|
||||
|
||||
void cdicdic_device::process_delayed_command()
|
||||
{
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
switch(m_command)
|
||||
{
|
||||
case 0x23: // Reset Mode 1
|
||||
@ -707,8 +709,8 @@ void cdicdic_device::process_delayed_command()
|
||||
|
||||
//printf( "Setting CDIC interrupt line\n" );
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for audio sector\n" );
|
||||
machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
}
|
||||
else if((buffer[CDIC_SECTOR_SUBMODE2] & (CDIC_SUBMODE_DATA | CDIC_SUBMODE_AUDIO | CDIC_SUBMODE_VIDEO)) == 0x00)
|
||||
{
|
||||
@ -726,8 +728,8 @@ void cdicdic_device::process_delayed_command()
|
||||
{
|
||||
//printf( "Setting CDIC interrupt line\n" );
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for message sector\n" );
|
||||
machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -746,8 +748,8 @@ void cdicdic_device::process_delayed_command()
|
||||
|
||||
//printf( "Setting CDIC interrupt line\n" );
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for data sector\n" );
|
||||
machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
}
|
||||
|
||||
if((buffer[CDIC_SECTOR_SUBMODE2] & CDIC_SUBMODE_EOF) == 0 && m_command != 0x23)
|
||||
@ -803,7 +805,7 @@ void cdicdic_device::process_delayed_command()
|
||||
|
||||
if(!cdrom_read_data(m_cd, lba, buffer, CD_TRACK_RAW_DONTCARE))
|
||||
{
|
||||
printf( "liajfoaijsdofiaodf\n");
|
||||
mame_printf_verbose("Unable to read CD-ROM data.\n");
|
||||
}
|
||||
|
||||
if(!(msf & 0x0000ff))
|
||||
@ -811,7 +813,7 @@ void cdicdic_device::process_delayed_command()
|
||||
// next_lba = next_nybbles[0] + next_nybbles[1]*10 + ((next_nybbles[2] + next_nybbles[3]*10)*75) + ((next_nybbles[4] + next_nybbles[5]*10)*75*60);
|
||||
verboselog(machine(), 0, "Playing CDDA sector from MSF location %06x\n", m_time | 2 );
|
||||
|
||||
cdda_start_audio(machine().device("cdda"), lba, rounded_next_msf);
|
||||
cdda_start_audio(state->m_cdda, lba, rounded_next_msf);
|
||||
}
|
||||
|
||||
m_ram[(m_data_buffer & 5) * (0xa00/2) + 0x924/2] = 0x0001; // CTRL
|
||||
@ -841,8 +843,8 @@ void cdicdic_device::process_delayed_command()
|
||||
}
|
||||
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for CDDA sector\n" );
|
||||
machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
break;
|
||||
}
|
||||
case 0x2c: // Seek
|
||||
@ -892,20 +894,16 @@ void cdicdic_device::process_delayed_command()
|
||||
m_time = next_msf << 8;
|
||||
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for Seek sector\n" );
|
||||
machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_4, 128);
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
READ16_DEVICE_HANDLER( cdic_r )
|
||||
{
|
||||
return downcast<cdicdic_device *>(device)->register_read(offset, mem_mask);
|
||||
}
|
||||
|
||||
UINT16 cdicdic_device::register_read(const UINT32 offset, const UINT16 mem_mask)
|
||||
READ16_MEMBER( cdicdic_device::regs_r )
|
||||
{
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
UINT32 addr = offset + 0x3c00/2;
|
||||
|
||||
switch(addr)
|
||||
@ -944,7 +942,7 @@ UINT16 cdicdic_device::register_read(const UINT32 offset, const UINT16 mem_mask)
|
||||
m_audio_buffer &= 0x7fff;
|
||||
if(!((m_audio_buffer | m_x_buffer) & 0x8000))
|
||||
{
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, CLEAR_LINE);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
|
||||
verboselog(machine(), 0, "Clearing CDIC interrupt line\n" );
|
||||
////printf("Clearing CDIC interrupt line\n" );
|
||||
}
|
||||
@ -958,7 +956,7 @@ UINT16 cdicdic_device::register_read(const UINT32 offset, const UINT16 mem_mask)
|
||||
m_x_buffer &= 0x7fff;
|
||||
if(!((m_audio_buffer | m_x_buffer) & 0x8000))
|
||||
{
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_4, CLEAR_LINE);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
|
||||
verboselog(machine(), 0, "Clearing CDIC interrupt line\n" );
|
||||
////printf("Clearing CDIC interrupt line\n" );
|
||||
}
|
||||
@ -987,12 +985,7 @@ UINT16 cdicdic_device::register_read(const UINT32 offset, const UINT16 mem_mask)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_DEVICE_HANDLER( cdic_w )
|
||||
{
|
||||
downcast<cdicdic_device *>(device)->register_write(offset, data, mem_mask);
|
||||
}
|
||||
|
||||
void cdicdic_device::register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask)
|
||||
WRITE16_MEMBER( cdicdic_device::regs_w )
|
||||
{
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
@ -1051,9 +1044,8 @@ void cdicdic_device::register_write(const UINT32 offset, const UINT16 data, cons
|
||||
|
||||
case 0x3ff8/2:
|
||||
{
|
||||
scc68070_regs_t *scc68070 = &state->m_scc68070_regs;
|
||||
UINT32 start = scc68070->dma.channel[0].memory_address_counter;
|
||||
UINT32 count = scc68070->dma.channel[0].transfer_counter;
|
||||
UINT32 start = state->m_scc->dma().channel[0].memory_address_counter;
|
||||
UINT32 count = state->m_scc->dma().channel[0].transfer_counter;
|
||||
UINT32 index = 0;
|
||||
UINT32 device_index = (data & 0x3fff) >> 1;
|
||||
UINT16 *memory = state->m_planea;
|
||||
@ -1068,7 +1060,7 @@ void cdicdic_device::register_write(const UINT32 offset, const UINT16 data, cons
|
||||
}
|
||||
for(index = start / 2; index < (start / 2 + count); index++)
|
||||
{
|
||||
if(scc68070->dma.channel[0].operation_control & OCR_D)
|
||||
if(state->m_scc->dma().channel[0].operation_control & OCR_D)
|
||||
{
|
||||
memory[index] = m_ram[device_index++];
|
||||
}
|
||||
@ -1077,7 +1069,7 @@ void cdicdic_device::register_write(const UINT32 offset, const UINT16 data, cons
|
||||
m_ram[device_index++] = memory[index];
|
||||
}
|
||||
}
|
||||
scc68070->dma.channel[0].memory_address_counter += scc68070->dma.channel[0].transfer_counter * 2;
|
||||
state->m_scc->dma().channel[0].memory_address_counter += state->m_scc->dma().channel[0].transfer_counter * 2;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1123,7 +1115,7 @@ void cdicdic_device::register_write(const UINT32 offset, const UINT16 data, cons
|
||||
break;
|
||||
}
|
||||
case 0x2b: // Stop CDDA
|
||||
cdda_stop_audio(machine().device("cdda"));
|
||||
cdda_stop_audio(state->m_cdda);
|
||||
m_interrupt_timer->adjust(attotime::never);
|
||||
break;
|
||||
case 0x23: // Reset Mode 1
|
||||
@ -1171,7 +1163,6 @@ void cdicdic_device::register_write(const UINT32 offset, const UINT16 data, cons
|
||||
cdicdic_device::cdicdic_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: device_t(mconfig, MACHINE_CDICDIC, "CDICDIC", tag, owner, clock)
|
||||
{
|
||||
init();
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -1180,12 +1171,25 @@ cdicdic_device::cdicdic_device(const machine_config &mconfig, const char *tag, d
|
||||
|
||||
void cdicdic_device::device_start()
|
||||
{
|
||||
register_globals();
|
||||
save_item(NAME(m_command));
|
||||
save_item(NAME(m_time));
|
||||
save_item(NAME(m_file));
|
||||
save_item(NAME(m_channel));
|
||||
save_item(NAME(m_audio_channel));
|
||||
save_item(NAME(m_audio_buffer));
|
||||
save_item(NAME(m_x_buffer));
|
||||
save_item(NAME(m_dma_control));
|
||||
save_item(NAME(m_z_buffer));
|
||||
save_item(NAME(m_interrupt_vector));
|
||||
save_item(NAME(m_data_buffer));
|
||||
|
||||
m_interrupt_timer = machine().scheduler().timer_alloc(FUNC(trigger_readback_int));
|
||||
save_item(NAME(m_audio_sample_freq));
|
||||
save_item(NAME(m_audio_sample_size));
|
||||
|
||||
m_interrupt_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdicdic_device::trigger_readback_int), this));
|
||||
m_interrupt_timer->adjust(attotime::never);
|
||||
|
||||
m_audio_sample_timer = machine().scheduler().timer_alloc(FUNC(audio_sample_trigger));
|
||||
m_audio_sample_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdicdic_device::audio_sample_trigger), this));
|
||||
m_audio_sample_timer->adjust(attotime::never);
|
||||
|
||||
m_ram = auto_alloc_array(machine(), UINT16, 0x3c00/2);
|
||||
@ -1197,25 +1201,8 @@ void cdicdic_device::device_start()
|
||||
|
||||
void cdicdic_device::device_reset()
|
||||
{
|
||||
init();
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
cdrom_image_device *cdrom_dev = machine().device<cdrom_image_device>("cdrom");
|
||||
if( cdrom_dev )
|
||||
{
|
||||
// MESS case (has CDROM device)
|
||||
m_cd = cdrom_dev->get_cdrom_file();
|
||||
cdda_set_cdrom(machine().device("cdda"), m_cd);
|
||||
}
|
||||
else
|
||||
{
|
||||
// MAME case
|
||||
m_cd = cdrom_open(get_disk_handle(machine(), ":cdrom"));
|
||||
cdda_set_cdrom(machine().device("cdda"), m_cd);
|
||||
}
|
||||
}
|
||||
|
||||
void cdicdic_device::init()
|
||||
{
|
||||
m_command = 0;
|
||||
m_time = 0;
|
||||
m_file = 0;
|
||||
@ -1233,44 +1220,28 @@ void cdicdic_device::init()
|
||||
|
||||
m_decode_addr = 0;
|
||||
m_decode_delay = 0;
|
||||
|
||||
cdrom_image_device *cdrom_dev = machine().device<cdrom_image_device>("cdrom");
|
||||
if( cdrom_dev )
|
||||
{
|
||||
// MESS case (has CDROM device)
|
||||
m_cd = cdrom_dev->get_cdrom_file();
|
||||
cdda_set_cdrom(state->m_cdda, m_cd);
|
||||
}
|
||||
else
|
||||
{
|
||||
// MAME case
|
||||
m_cd = cdrom_open(get_disk_handle(machine(), ":cdrom"));
|
||||
cdda_set_cdrom(state->m_cdda, m_cd);
|
||||
}
|
||||
}
|
||||
|
||||
void cdicdic_device::register_globals()
|
||||
WRITE16_MEMBER( cdicdic_device::ram_w )
|
||||
{
|
||||
save_item(NAME(m_command));
|
||||
save_item(NAME(m_time));
|
||||
save_item(NAME(m_file));
|
||||
save_item(NAME(m_channel));
|
||||
save_item(NAME(m_audio_channel));
|
||||
save_item(NAME(m_audio_buffer));
|
||||
save_item(NAME(m_x_buffer));
|
||||
save_item(NAME(m_dma_control));
|
||||
save_item(NAME(m_z_buffer));
|
||||
save_item(NAME(m_interrupt_vector));
|
||||
save_item(NAME(m_data_buffer));
|
||||
|
||||
save_item(NAME(m_audio_sample_freq));
|
||||
save_item(NAME(m_audio_sample_size));
|
||||
}
|
||||
|
||||
WRITE16_DEVICE_HANDLER( cdic_ram_w )
|
||||
{
|
||||
downcast<cdicdic_device *>(device)->ram_write(offset, data, mem_mask);
|
||||
}
|
||||
|
||||
void cdicdic_device::ram_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask)
|
||||
{
|
||||
verboselog(machine(), 5, "cdic_ram_w: %08x = %04x & %04x\n", 0x00300000 + offset*2, data, mem_mask);
|
||||
COMBINE_DATA(&m_ram[offset]);
|
||||
}
|
||||
|
||||
READ16_DEVICE_HANDLER( cdic_ram_r )
|
||||
READ16_MEMBER( cdicdic_device::ram_r )
|
||||
{
|
||||
return downcast<cdicdic_device *>(device)->ram_read(offset, mem_mask);
|
||||
}
|
||||
|
||||
UINT16 cdicdic_device::ram_read(const UINT32 offset, const UINT16 mem_mask)
|
||||
{
|
||||
verboselog(machine(), 5, "cdic_ram_r: %08x = %04x & %04x\n", 0x00300000 + offset * 2, m_ram[offset], mem_mask);
|
||||
return m_ram[offset];
|
||||
}
|
||||
|
||||
@ -26,7 +26,7 @@ TODO:
|
||||
|
||||
#include "emu.h"
|
||||
#include "cdrom.h"
|
||||
|
||||
#include "sound/cdda.h"
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
@ -59,6 +59,12 @@ public:
|
||||
void register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask);
|
||||
UINT16 register_read(const UINT32 offset, const UINT16 mem_mask);
|
||||
|
||||
DECLARE_READ16_MEMBER( regs_r );
|
||||
DECLARE_WRITE16_MEMBER( regs_w );
|
||||
DECLARE_READ16_MEMBER( ram_r );
|
||||
DECLARE_WRITE16_MEMBER( ram_w );
|
||||
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
@ -67,8 +73,8 @@ protected:
|
||||
virtual void device_clock_changed() { }
|
||||
|
||||
// internal callbacks
|
||||
static TIMER_CALLBACK( audio_sample_trigger );
|
||||
static TIMER_CALLBACK( trigger_readback_int );
|
||||
TIMER_CALLBACK_MEMBER( audio_sample_trigger );
|
||||
TIMER_CALLBACK_MEMBER( trigger_readback_int );
|
||||
|
||||
private:
|
||||
// internal state
|
||||
@ -99,9 +105,6 @@ private:
|
||||
int m_xa_last[4];
|
||||
UINT16 *m_ram;
|
||||
|
||||
void register_globals();
|
||||
void init();
|
||||
|
||||
// static internal members
|
||||
static void decode_xa_mono(INT32 *cdic_xa_last, const UINT8 *xa, INT16 *dp);
|
||||
static void decode_xa_mono8(INT32 *cdic_xa_last, const UINT8 *xa, INT16 *dp);
|
||||
@ -120,16 +123,4 @@ private:
|
||||
// device type definition
|
||||
extern const device_type MACHINE_CDICDIC;
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// READ/WRITE HANDLERS
|
||||
//**************************************************************************
|
||||
|
||||
DECLARE_READ16_DEVICE_HANDLER( cdic_r );
|
||||
DECLARE_WRITE16_DEVICE_HANDLER( cdic_w );
|
||||
DECLARE_READ16_DEVICE_HANDLER( cdic_ram_r );
|
||||
DECLARE_WRITE16_DEVICE_HANDLER( cdic_ram_w );
|
||||
|
||||
|
||||
#endif // __CDICDIC_H__
|
||||
|
||||
@ -50,17 +50,13 @@ INLINE void verboselog(running_machine &machine, int n_level, const char *s_fmt,
|
||||
// MEMBER FUNCTIONS
|
||||
//**************************************************************************
|
||||
|
||||
TIMER_CALLBACK( cdislave_device::trigger_readback_int )
|
||||
TIMER_CALLBACK_MEMBER( cdislave_device::trigger_readback_int )
|
||||
{
|
||||
cdislave_device *slave = static_cast<cdislave_device *>(machine.device("slave"));
|
||||
slave->readback_trigger();
|
||||
}
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
void cdislave_device::readback_trigger()
|
||||
{
|
||||
verboselog(machine(), 0, "Asserting IRQ2\n" );
|
||||
machine().device("maincpu")->execute().set_input_line_vector(M68K_IRQ_2, 26);
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_2, ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_2, 26);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
|
||||
m_interrupt_timer->adjust(attotime::never);
|
||||
}
|
||||
|
||||
@ -79,9 +75,11 @@ void cdislave_device::prepare_readback(attotime delay, UINT8 channel, UINT8 coun
|
||||
|
||||
void cdislave_device::perform_mouse_update()
|
||||
{
|
||||
UINT16 x = machine().root_device().ioport("MOUSEX")->read();
|
||||
UINT16 y = machine().root_device().ioport("MOUSEY")->read();
|
||||
UINT8 buttons = machine().root_device().ioport("MOUSEBTN")->read();
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
UINT16 x = state->m_mousex->read();
|
||||
UINT16 y = state->m_mousey->read();
|
||||
UINT8 buttons = state->m_mousebtn->read();
|
||||
|
||||
UINT16 old_mouse_x = m_real_mouse_x;
|
||||
UINT16 old_mouse_y = m_real_mouse_y;
|
||||
@ -122,13 +120,10 @@ INPUT_CHANGED_MEMBER( cdislave_device::mouse_update )
|
||||
perform_mouse_update();
|
||||
}
|
||||
|
||||
READ16_DEVICE_HANDLER( slave_r )
|
||||
READ16_MEMBER( cdislave_device::slave_r )
|
||||
{
|
||||
return downcast<cdislave_device *>(device)->register_read(offset, mem_mask);
|
||||
}
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
UINT16 cdislave_device::register_read(const UINT32 offset, const UINT16 mem_mask)
|
||||
{
|
||||
if(m_channel[offset].m_out_count)
|
||||
{
|
||||
UINT8 ret = m_channel[offset].m_out_buf[m_channel[offset].m_out_index];
|
||||
@ -144,7 +139,7 @@ UINT16 cdislave_device::register_read(const UINT32 offset, const UINT16 mem_mask
|
||||
case 0xf4:
|
||||
case 0xf7:
|
||||
verboselog(machine(), 0, "slave_r: De-asserting IRQ2\n" );
|
||||
machine().device("maincpu")->execute().set_input_line(M68K_IRQ_2, CLEAR_LINE);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -180,12 +175,7 @@ void cdislave_device::set_mouse_position()
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_DEVICE_HANDLER( slave_w )
|
||||
{
|
||||
downcast<cdislave_device *>(device)->register_write(offset, data, mem_mask);
|
||||
}
|
||||
|
||||
void cdislave_device::register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask)
|
||||
WRITE16_MEMBER( cdislave_device::slave_w )
|
||||
{
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
@ -429,7 +419,6 @@ void cdislave_device::register_write(const UINT32 offset, const UINT16 data, con
|
||||
cdislave_device::cdislave_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: device_t(mconfig, MACHINE_CDISLAVE, "CDISLAVE", tag, owner, clock)
|
||||
{
|
||||
init();
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -437,53 +426,6 @@ cdislave_device::cdislave_device(const machine_config &mconfig, const char *tag,
|
||||
//-------------------------------------------------
|
||||
|
||||
void cdislave_device::device_start()
|
||||
{
|
||||
register_globals();
|
||||
|
||||
m_interrupt_timer = machine().scheduler().timer_alloc(FUNC(trigger_readback_int));
|
||||
m_interrupt_timer->adjust(attotime::never);
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_reset - device-specific reset
|
||||
//-------------------------------------------------
|
||||
|
||||
void cdislave_device::device_reset()
|
||||
{
|
||||
init();
|
||||
}
|
||||
|
||||
void cdislave_device::init()
|
||||
{
|
||||
for(INT32 index = 0; index < 4; index++)
|
||||
{
|
||||
m_channel[index].m_out_buf[0] = 0;
|
||||
m_channel[index].m_out_buf[1] = 0;
|
||||
m_channel[index].m_out_buf[2] = 0;
|
||||
m_channel[index].m_out_buf[3] = 0;
|
||||
m_channel[index].m_out_index = 0;
|
||||
m_channel[index].m_out_count = 0;
|
||||
m_channel[index].m_out_cmd = 0;
|
||||
}
|
||||
|
||||
memset(m_in_buf, 0, 17);
|
||||
m_in_index = 0;
|
||||
m_in_count = 0;
|
||||
|
||||
m_polling_active = 0;
|
||||
|
||||
m_xbus_interrupt_enable = 0;
|
||||
|
||||
memset(m_lcd_state, 0, 16);
|
||||
|
||||
m_real_mouse_x = 0xffff;
|
||||
m_real_mouse_y = 0xffff;
|
||||
|
||||
m_fake_mouse_x = 0;
|
||||
m_fake_mouse_y = 0;
|
||||
}
|
||||
|
||||
void cdislave_device::register_globals()
|
||||
{
|
||||
save_item(NAME(m_channel[0].m_out_buf[0]));
|
||||
save_item(NAME(m_channel[0].m_out_buf[1]));
|
||||
@ -529,4 +471,41 @@ void cdislave_device::register_globals()
|
||||
|
||||
save_item(NAME(m_fake_mouse_x));
|
||||
save_item(NAME(m_fake_mouse_y));
|
||||
|
||||
m_interrupt_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdislave_device::trigger_readback_int), this));
|
||||
m_interrupt_timer->adjust(attotime::never);
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_reset - device-specific reset
|
||||
//-------------------------------------------------
|
||||
|
||||
void cdislave_device::device_reset()
|
||||
{
|
||||
for(INT32 index = 0; index < 4; index++)
|
||||
{
|
||||
m_channel[index].m_out_buf[0] = 0;
|
||||
m_channel[index].m_out_buf[1] = 0;
|
||||
m_channel[index].m_out_buf[2] = 0;
|
||||
m_channel[index].m_out_buf[3] = 0;
|
||||
m_channel[index].m_out_index = 0;
|
||||
m_channel[index].m_out_count = 0;
|
||||
m_channel[index].m_out_cmd = 0;
|
||||
}
|
||||
|
||||
memset(m_in_buf, 0, 17);
|
||||
m_in_index = 0;
|
||||
m_in_count = 0;
|
||||
|
||||
m_polling_active = 0;
|
||||
|
||||
m_xbus_interrupt_enable = 0;
|
||||
|
||||
memset(m_lcd_state, 0, 16);
|
||||
|
||||
m_real_mouse_x = 0xffff;
|
||||
m_real_mouse_y = 0xffff;
|
||||
|
||||
m_fake_mouse_x = 0;
|
||||
m_fake_mouse_y = 0;
|
||||
}
|
||||
|
||||
@ -51,8 +51,9 @@ public:
|
||||
|
||||
UINT8* get_lcd_state() { return m_lcd_state; }
|
||||
void readback_trigger();
|
||||
void register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask);
|
||||
UINT16 register_read(const UINT32 offset, const UINT16 mem_mask);
|
||||
|
||||
DECLARE_READ16_MEMBER( slave_r );
|
||||
DECLARE_WRITE16_MEMBER( slave_w );
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
@ -62,7 +63,7 @@ protected:
|
||||
virtual void device_clock_changed() { }
|
||||
|
||||
// internal callbacks
|
||||
static TIMER_CALLBACK( trigger_readback_int );
|
||||
TIMER_CALLBACK_MEMBER( trigger_readback_int );
|
||||
|
||||
private:
|
||||
// internal state
|
||||
@ -96,9 +97,6 @@ private:
|
||||
UINT16 m_fake_mouse_x;
|
||||
UINT16 m_fake_mouse_y;
|
||||
|
||||
void register_globals();
|
||||
void init();
|
||||
|
||||
// static internal members
|
||||
|
||||
// non-static internal members
|
||||
@ -111,14 +109,4 @@ private:
|
||||
// device type definition
|
||||
extern const device_type MACHINE_CDISLAVE;
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// READ/WRITE HANDLERS
|
||||
//**************************************************************************
|
||||
|
||||
DECLARE_READ16_DEVICE_HANDLER( slave_r );
|
||||
DECLARE_WRITE16_DEVICE_HANDLER( slave_w );
|
||||
|
||||
|
||||
#endif // __CDISLAVE_H__
|
||||
|
||||
@ -620,11 +620,11 @@ static void mcd212_process_ica(mcd212_regs_t *mcd212, int channel)
|
||||
mcd212->channel[1].csrr |= 1 << (2 - channel);
|
||||
if(mcd212->channel[1].csrr & (MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2))
|
||||
{
|
||||
UINT8 interrupt = (state->m_scc68070_regs.lir >> 4) & 7;
|
||||
UINT8 interrupt = (state->m_scc->get_lir() >> 4) & 7;
|
||||
if(interrupt)
|
||||
{
|
||||
machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
|
||||
machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
@ -633,8 +633,8 @@ static void mcd212_process_ica(mcd212_regs_t *mcd212, int channel)
|
||||
UINT8 interrupt = state->m_scc68070_regs.lir & 7;
|
||||
if(interrupt)
|
||||
{
|
||||
machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
|
||||
machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -711,11 +711,11 @@ static void mcd212_process_dca(mcd212_regs_t *mcd212, int channel)
|
||||
mcd212->channel[1].csrr |= 1 << (2 - channel);
|
||||
if(mcd212->channel[1].csrr & (MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2))
|
||||
{
|
||||
UINT8 interrupt = (state->m_scc68070_regs.lir >> 4) & 7;
|
||||
UINT8 interrupt = (state->m_scc->get_lir() >> 4) & 7;
|
||||
if(interrupt)
|
||||
{
|
||||
machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
|
||||
machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
@ -724,8 +724,8 @@ static void mcd212_process_dca(mcd212_regs_t *mcd212, int channel)
|
||||
UINT8 interrupt = state->m_scc68070_regs.lir & 7;
|
||||
if(interrupt)
|
||||
{
|
||||
machine.device("maincpu")->execute().set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
|
||||
machine.device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -1371,16 +1371,16 @@ READ16_HANDLER( mcd212_r )
|
||||
else
|
||||
{
|
||||
UINT8 old_csr = mcd212->channel[1].csrr;
|
||||
UINT8 interrupt1 = (state->m_scc68070_regs.lir >> 4) & 7;
|
||||
UINT8 interrupt1 = (state->m_scc->get_lir() >> 4) & 7;
|
||||
//UINT8 interrupt2 = state->m_scc68070_regs.lir & 7;
|
||||
mcd212->channel[1].csrr &= ~(MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2);
|
||||
if(interrupt1)
|
||||
{
|
||||
space.machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt1 - 1), CLEAR_LINE);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt1 - 1), CLEAR_LINE);
|
||||
}
|
||||
//if(interrupt2)
|
||||
//{
|
||||
// space.machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1 + (interrupt2 - 1), CLEAR_LINE);
|
||||
// state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt2 - 1), CLEAR_LINE);
|
||||
//}
|
||||
return old_csr;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user