From 3ff214100201c3b28777601a43353397d53392f2 Mon Sep 17 00:00:00 2001 From: David Haywood Date: Thu, 29 Oct 2015 23:27:01 +0000 Subject: [PATCH] internal loggers (nw) --- src/devices/bus/vcs/harmony_melody.c | 5 - src/devices/cpu/arm7/lpc210x.c | 200 ++++++++++++++++++++++++++- src/devices/cpu/arm7/lpc210x.h | 48 +++++++ 3 files changed, 245 insertions(+), 8 deletions(-) diff --git a/src/devices/bus/vcs/harmony_melody.c b/src/devices/bus/vcs/harmony_melody.c index a42a16aa4ea..d6bf0291fdc 100644 --- a/src/devices/bus/vcs/harmony_melody.c +++ b/src/devices/bus/vcs/harmony_melody.c @@ -82,11 +82,6 @@ void a26_rom_harmony_device::device_start() } static ADDRESS_MAP_START( harmony_arm7_map, AS_PROGRAM, 32, a26_rom_harmony_device ) - // these are not listed in the ARM manual as internal areas, so probably external? what maps here? - AM_RANGE(0x3FFFC000, 0x3FFFC003) AM_RAM - AM_RANGE(0x3FFFC010, 0x3FFFC013) AM_RAM - AM_RANGE(0x3FFFC014, 0x3FFFC017) AM_RAM // reads - AM_RANGE(0x3FFFC018, 0x3FFFC01b) AM_RAM ADDRESS_MAP_END static MACHINE_CONFIG_FRAGMENT( a26_harmony ) diff --git a/src/devices/cpu/arm7/lpc210x.c b/src/devices/cpu/arm7/lpc210x.c index 18f51f3a3a8..72388cf18f6 100644 --- a/src/devices/cpu/arm7/lpc210x.c +++ b/src/devices/cpu/arm7/lpc210x.c @@ -18,9 +18,24 @@ const device_type LPC2103 = &device_creator; static ADDRESS_MAP_START( lpc2103_map, AS_PROGRAM, 32, lpc210x_device ) AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(flash_r, flash_w) // 32kb internal FLASH rom - AM_RANGE(0x40000000, 0x40001fff) AM_RAM // 8kb internal SROM (writes should actually latch - see docs) + + AM_RANGE(0x3FFFC000, 0x3FFFC01f) AM_READWRITE( fio_r, fio_w ) // GPIO - AM_RANGE(0xE01FC088, 0xE01FC08b) AM_READ(arm_E01FC088_r) + + AM_RANGE(0x40000000, 0x40001fff) AM_RAM // 8kb internal SROM (writes should actually latch - see docs) + + AM_RANGE(0xE0004000, 0xE000407f) AM_READWRITE( timer0_r, timer0_w) + + AM_RANGE(0xE0008000, 0xE000807f) AM_READWRITE( timer1_r, timer1_w) + + AM_RANGE(0xE002C000, 0xE002C007) AM_READWRITE( pin_r, pin_w ) + + AM_RANGE(0xE01FC000, 0xE01FC007) AM_READWRITE( mam_r, mam_w ) + AM_RANGE(0xE01FC080, 0xE01FC08f) AM_READWRITE( pll_r, pll_w ) // phase locked loop + AM_RANGE(0xE01FC100, 0xE01FC103) AM_READWRITE( apbdiv_r, apbdiv_w ) + AM_RANGE(0xE01FC1a0, 0xE01FC1a3) AM_READWRITE( scs_r, scs_w ) + + AM_RANGE(0xFFFFF000, 0xFFFFF2ff) AM_READWRITE( vic_r, vic_w ) // interrupt controller ADDRESS_MAP_END @@ -71,7 +86,6 @@ void lpc210x_device::device_start() arm7_cpu_device::device_start(); } - //------------------------------------------------- // device_reset - device-specific reset //------------------------------------------------- @@ -79,8 +93,188 @@ void lpc210x_device::device_start() void lpc210x_device::device_reset() { arm7_cpu_device::device_reset(); + + m_TxPR[0] = 0; + m_TxPR[1] = 0; } +/* VIC (Vectored Interrupt Controller) */ + +READ32_MEMBER( lpc210x_device::vic_r ) +{ + switch (offset*4) + { + default: + logerror("%08x unhandled read from VIC offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask); + } + + return 0x00000000; +} + + +WRITE32_MEMBER( lpc210x_device::vic_w ) +{ + switch (offset * 4) + { + default: + logerror("%08x unhandled write VIC offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask); + } +} + +/* PIN Select block */ + +READ32_MEMBER( lpc210x_device::pin_r ) +{ + switch (offset*4) + { + default: + logerror("%08x unhandled read from PINSEL offset %08x mem_mask %08x\n",space.device().safe_pc(), offset * 4, mem_mask); + } + + return 0x00000000; +} + + +WRITE32_MEMBER( lpc210x_device::pin_w ) +{ + switch (offset * 4) + { + default: + logerror("%08x unhandled write PINSEL offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask); + } +} + +/* MAM block (memory conttroller) */ + +READ32_MEMBER( lpc210x_device::mam_r ) +{ + switch (offset*4) + { + default: + logerror("%08x unhandled read from MAM offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask); + } + + return 0x00000000; +} + + +WRITE32_MEMBER( lpc210x_device::mam_w ) +{ + switch (offset * 4) + { + default: + logerror("%08x unhandled write MAM offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask); + } +} + +/* FIO block */ + +READ32_MEMBER( lpc210x_device::fio_r ) +{ + switch (offset*4) + { + default: + logerror("%08x unhandled read from FIO offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask); + } + + return 0x00000000; +} + + +WRITE32_MEMBER( lpc210x_device::fio_w ) +{ + switch (offset * 4) + { + default: + logerror("%08x unhandled write FIO offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask); + } +} + + +/* APB Divider */ + +READ32_MEMBER( lpc210x_device::apbdiv_r ) +{ + logerror("%08x unhandled read from APBDIV offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask); + return 0x00000000; +} + + +WRITE32_MEMBER( lpc210x_device::apbdiv_w ) +{ + logerror("%08x unhandled write APBDIV offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask); +} + +/* Syscon misc registers */ + +READ32_MEMBER( lpc210x_device::scs_r ) +{ + logerror("%08x unhandled read from SCS offset %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, mem_mask); + return 0x00000000; +} + + +WRITE32_MEMBER( lpc210x_device::scs_w ) +{ + logerror("%08x unhandled write SCS offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask); +} + +/* PLL Phase Locked Loop */ + +READ32_MEMBER( lpc210x_device::pll_r ) +{ + switch (offset*4) + { + default: + logerror("%08x unhandled read from PLL offset %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, mem_mask); + } + + return 0xffffffff; +} + + +WRITE32_MEMBER( lpc210x_device::pll_w ) +{ + switch (offset * 4) + { + default: + logerror("%08x unhandled write PLL offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask); + } +} + + +/* Timers */ + +UINT32 lpc210x_device::read_timer(address_space &space, int timer, int offset, UINT32 mem_mask) +{ + switch (offset*4) + { + case 0x0c: + return m_TxPR[timer]; + + default: + logerror("%08x unhandled read from timer %d offset %02x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, mem_mask); + } + + return 0x00000000; +} + + +void lpc210x_device::write_timer(address_space &space, int timer, int offset, UINT32 data, UINT32 mem_mask) +{ + switch (offset * 4) + { + case 0x0c: + COMBINE_DATA(&m_TxPR[timer]); + logerror("%08x Timer %d Prescale Register set to %08x\n", space.device().safe_pc(),timer, m_TxPR[timer]); + break; + + default: + logerror("%08x unhandled write timer %d offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, data, mem_mask); + } +} + + static MACHINE_CONFIG_FRAGMENT( lpc210x ) MACHINE_CONFIG_END diff --git a/src/devices/cpu/arm7/lpc210x.h b/src/devices/cpu/arm7/lpc210x.h index 7928dc939f4..0fc502d31bd 100644 --- a/src/devices/cpu/arm7/lpc210x.h +++ b/src/devices/cpu/arm7/lpc210x.h @@ -34,6 +34,45 @@ public: DECLARE_READ32_MEMBER(flash_r); DECLARE_WRITE32_MEMBER(flash_w); + // timer 0 / 1 + DECLARE_READ32_MEMBER(timer0_r) { return read_timer(space, 0, offset, mem_mask); } + DECLARE_WRITE32_MEMBER(timer0_w) { write_timer(space, 0, offset, data, mem_mask); } + + DECLARE_READ32_MEMBER(timer1_r) { return read_timer(space, 1, offset, mem_mask); } + DECLARE_WRITE32_MEMBER(timer1_w) { write_timer(space, 1, offset, data, mem_mask); } + + void write_timer(address_space &space, int timer, int offset, UINT32 data, UINT32 mem_mask); + UINT32 read_timer(address_space &space, int timer, int offset, UINT32 mem_mask); + + UINT32 m_TxPR[2]; + + // VIC + DECLARE_READ32_MEMBER(vic_r); + DECLARE_WRITE32_MEMBER(vic_w); + + // PIN select block + DECLARE_READ32_MEMBER(pin_r); + DECLARE_WRITE32_MEMBER(pin_w); + + //PLL Phase Locked Loop + DECLARE_READ32_MEMBER(pll_r); + DECLARE_WRITE32_MEMBER(pll_w); + + //MAM memory controller + DECLARE_READ32_MEMBER(mam_r); + DECLARE_WRITE32_MEMBER(mam_w); + + //APB divider + DECLARE_READ32_MEMBER(apbdiv_r); + DECLARE_WRITE32_MEMBER(apbdiv_w); + + //syscon misc + DECLARE_READ32_MEMBER(scs_r); + DECLARE_WRITE32_MEMBER(scs_w); + + // fio + DECLARE_READ32_MEMBER(fio_r); + DECLARE_WRITE32_MEMBER(fio_w); protected: // device-level overrides @@ -43,9 +82,18 @@ protected: virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const; + + + + + private: address_space_config m_program_config; + + + + };