diff --git a/src/mame/drivers/wpc_an.c b/src/mame/drivers/wpc_an.c index 51793c997a5..08e446e6408 100644 --- a/src/mame/drivers/wpc_an.c +++ b/src/mame/drivers/wpc_an.c @@ -12,46 +12,6 @@ #define LOG_WPC (1) -/* AMFDS9 */ -/* Printer board */ -#define WPC_PRINTBUSY (0x10) /* xxxxx R: Printer ready ??? */ -#define WPC_PRINTDATA (0x11) /* xxxxx W: send to printer */ -#define WPC_PRINTDATAX (0x12) /* xxxxx W: 0: Printer data available */ -/* Sound board */ -#define WPC_SOUNDS11 (0x21) /* xxx RW: R: Sound data availble, W: Reset soundboard ? */ -#define WPC_SOUNDIF (0x2c) /* xxx RW: Sound board interface */ -#define WPC_SOUNDBACK (0x2d) /* xxx RW: R: Sound data availble, W: Reset soundboard ? */ - -#define WPC_SOLENOID1 (0x30) /* xxxxxx W: Solenoid 25-28 */ -#define WPC_SOLENOID2 (0x31) /* xxxxxx W: Solenoid 1- 8 */ -#define WPC_SOLENOID3 (0x32) /* xxxxxx W: Solenoid 17-24 */ -#define WPC_SOLENOID4 (0x33) /* xxxxxx W: Solenoid 9-16 */ -#define WPC_LAMPROW (0x34) /* xxxxxx W: Lamp row */ -#define WPC_LAMPCOLUMN (0x35) /* xxxxxx W: Lamp column enable */ -#define WPC_GILAMPS (0x36) /* W: GI lights ?? */ -#define WPC_DIPSWITCH (0x37) /* xxxxxx R: CPU board dip-switches */ -#define WPC_SWCOINDOOR (0x38) /* xxxxxx W: Coin door switches */ -#define WPC_SWROWREAD (0x39) /* xxxx R: Switch row read */ -#define WPC_SWCOLSELECT (0x3a) /* xxxx W: Switch column enable */ -#define WPC_ALPHAPOS (0x3b) /* x W: Select alphanumeric position */ -#define WPC_ALPHA1LO (0x3c) /* x W: Display 1st row hi bits */ -#define WPC_ALPHA1HI (0x3d) /* x W: Display 1st row lo bits */ -#define WPC_ALPHA2LO (0x3e) /* x W: Display 2nd row hi bits */ -#define WPC_ALPHA2HI (0x3f) /* x W: b 2nd row lo bits */ -#define WPC_LED (0x42) /* xxxxxx W: CPU LED (bit 7) */ -#define WPC_IRQACK (0x43) /* W: IRQ Ack ??? */ -#define WPC_SHIFTADRH (0x44) /* xxxxxx RW: See above */ -#define WPC_SHIFTADRL (0x45) /* xxxxxx RW: See above */ -#define WPC_SHIFTBIT (0x46) /* xxxxxx RW: See above */ -#define WPC_SHIFTBIT2 (0x47) /* xxxxxx RW: See above */ -#define WPC_FIRQSRC (0x48) /* xxxx R: bit 7 0=DMD, 1=SOUND? W: Clear FIRQ line */ -#define WPC_RTCHOUR (0x4a) /* xxxxxx RW: Real time clock: hour */ -#define WPC_RTCMIN (0x4b) /* xxxxxx RW: Real time clock: minute */ -#define WPC_ROMBANK (0x4c) /* xxxxxx W: Rombank switch */ -#define WPC_PROTMEM (0x4d) /* xxxxxx W: enabled/disable protected memory */ -#define WPC_PROTMEMCTRL (0x4e) /* xxxxxx W: Set protected memory area */ -#define WPC_WATCHDOG (0x4f) /* xxxxxx W: Watchdog */ - class wpc_an_state : public driver_device { public: @@ -92,20 +52,10 @@ public: DECLARE_WRITE8_MEMBER(wpc_sound_s11_w); DECLARE_WRITE8_MEMBER(wpc_rombank_w); private: - UINT8 m_alpha_pos; // selected LED position - UINT16 m_alpha_data[40]; UINT16 m_vblank_count; UINT32 m_irq_count; - UINT8 m_switch_col; // select switch column UINT8 m_bankmask; - UINT8 m_switches[12]; - UINT8 m_memprotect; - UINT16 m_memprotect_mask; UINT8 m_ram[0x3000]; - UINT8 m_shift_addr_high; - UINT8 m_shift_addr_low; - UINT8 m_shift_bit1; - UINT8 m_shift_bit2; emu_timer* m_vblank_timer; emu_timer* m_irq_timer; }; @@ -258,7 +208,6 @@ void wpc_an_state::device_timer(emu_timer &timer, device_timer_id id, int param, WRITE8_MEMBER(wpc_an_state::wpc_rombank_w) { m_cpubank->set_entry(data & m_bankmask); - logerror("WPC: masked ROM bank selected %02x\n",data & m_bankmask); } WRITE_LINE_MEMBER(wpc_an_state::wpcsnd_reply_w) diff --git a/src/mame/drivers/wpc_dot.c b/src/mame/drivers/wpc_dot.c index 3fec61ef467..4eb7ff6c16d 100644 --- a/src/mame/drivers/wpc_dot.c +++ b/src/mame/drivers/wpc_dot.c @@ -1,46 +1,389 @@ #include "emu.h" #include "cpu/m6809/m6809.h" +#include "audio/wpcsnd.h" +#include "machine/wpc.h" +#include "rendlay.h" class wpc_dot_state : public driver_device { public: wpc_dot_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag), - m_maincpu(*this, "maincpu") + m_maincpu(*this, "maincpu"), + m_wpcsnd(*this,"wpcsnd"), + m_wpc(*this,"wpc"), + m_cpubank(*this, "cpubank"), + m_fixedbank(*this, "fixedbank"), + m_dmdbank1(*this, "dmdbank1"), + m_dmdbank2(*this, "dmdbank2"), + m_dmdbank3(*this, "dmdbank3"), + m_dmdbank4(*this, "dmdbank4"), + m_dmdbank5(*this, "dmdbank5"), + m_dmdbank6(*this, "dmdbank6") { } protected: // devices required_device m_maincpu; + required_device m_wpcsnd; + required_device m_wpc; + required_memory_bank m_cpubank; + required_memory_bank m_fixedbank; + required_memory_bank m_dmdbank1; + required_memory_bank m_dmdbank2; + required_memory_bank m_dmdbank3; + required_memory_bank m_dmdbank4; + required_memory_bank m_dmdbank5; + required_memory_bank m_dmdbank6; // driver_device overrides virtual void machine_reset(); + virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr); + static const device_timer_id TIMER_VBLANK = 0; + static const device_timer_id TIMER_IRQ = 1; public: DECLARE_DRIVER_INIT(wpc_dot); + DECLARE_READ8_MEMBER(ram_r); + DECLARE_WRITE8_MEMBER(ram_w); + DECLARE_WRITE_LINE_MEMBER(wpcsnd_reply_w); + DECLARE_WRITE_LINE_MEMBER(wpc_irq_w); + DECLARE_WRITE_LINE_MEMBER(wpc_firq_w); + DECLARE_READ8_MEMBER(wpc_sound_ctrl_r); + DECLARE_WRITE8_MEMBER(wpc_sound_ctrl_w); + DECLARE_READ8_MEMBER(wpc_sound_data_r); + DECLARE_WRITE8_MEMBER(wpc_sound_data_w); + DECLARE_WRITE8_MEMBER(wpc_sound_s11_w); + DECLARE_WRITE8_MEMBER(wpc_rombank_w); + DECLARE_WRITE8_MEMBER(wpc_dmdbank_w); + + UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + +private: + UINT16 m_vblank_count; + UINT32 m_irq_count; + UINT8 m_bankmask; + UINT8 m_ram[0x3000]; + UINT8 m_dmdram[0x2000]; + emu_timer* m_vblank_timer; + emu_timer* m_irq_timer; }; static ADDRESS_MAP_START( wpc_dot_map, AS_PROGRAM, 8, wpc_dot_state ) - AM_RANGE(0x0000, 0xffff) AM_NOP + AM_RANGE(0x0000, 0x2fff) AM_READWRITE(ram_r,ram_w) + AM_RANGE(0x3000, 0x31ff) AM_RAMBANK("dmdbank1") + AM_RANGE(0x3200, 0x33ff) AM_RAMBANK("dmdbank2") + AM_RANGE(0x3400, 0x35ff) AM_RAMBANK("dmdbank3") + AM_RANGE(0x3600, 0x37ff) AM_RAMBANK("dmdbank4") + AM_RANGE(0x3800, 0x39ff) AM_RAMBANK("dmdbank5") + AM_RANGE(0x3a00, 0x3bff) AM_RAMBANK("dmdbank6") + AM_RANGE(0x3c00, 0x3faf) AM_RAM + AM_RANGE(0x3fb0, 0x3fff) AM_DEVREADWRITE("wpc",wpc_device,read,write) // WPC device + AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("cpubank") + AM_RANGE(0x8000, 0xffff) AM_ROMBANK("fixedbank") ADDRESS_MAP_END static INPUT_PORTS_START( wpc_dot ) + PORT_START("INP0") + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("INP1") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) // left flipper + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) // right flipper + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_TILT ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) + + PORT_START("INP2") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) + PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) // always closed + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K) + + PORT_START("INP4") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_M) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_COMMA) + + PORT_START("INP8") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_STOP) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_SLASH) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_COLON) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_QUOTE) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_MINUS) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_EQUALS) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_BACKSPACE) + + PORT_START("INP10") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_OPENBRACE) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_CLOSEBRACE) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_BACKSLASH) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_ENTER) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_LEFT) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_RIGHT) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_UP) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_DOWN) + + PORT_START("INP20") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_O) + + PORT_START("INP40") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_LALT) + PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("INP80") + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN ) + + PORT_START("COIN") + PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) + PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) + PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 ) + PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN4 ) + PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Service / Escape") PORT_CODE(KEYCODE_DEL_PAD) + PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_VOLUME_DOWN ) PORT_CODE(KEYCODE_MINUS_PAD) + PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_VOLUME_UP ) PORT_CODE(KEYCODE_PLUS_PAD) + PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Begin Test / Enter") PORT_CODE(KEYCODE_ENTER_PAD) + + PORT_START("DIPS") + PORT_DIPNAME(0x01,0x01,"Switch 1") PORT_DIPLOCATION("SWA:1") + PORT_DIPSETTING(0x00,DEF_STR( Off )) + PORT_DIPSETTING(0x01,DEF_STR( On )) + PORT_DIPNAME(0x02,0x02,"Switch 2") PORT_DIPLOCATION("SWA:2") + PORT_DIPSETTING(0x00,DEF_STR( Off )) + PORT_DIPSETTING(0x02,DEF_STR( On )) + PORT_DIPNAME(0x04,0x00,"W20") PORT_DIPLOCATION("SWA:3") + PORT_DIPSETTING(0x00,DEF_STR( Off )) + PORT_DIPSETTING(0x04,DEF_STR( On )) + PORT_DIPNAME(0x08,0x00,"W19") PORT_DIPLOCATION("SWA:4") + PORT_DIPSETTING(0x00,DEF_STR( Off )) + PORT_DIPSETTING(0x08,DEF_STR( On )) + PORT_DIPNAME(0xf0,0x00,"Country") PORT_DIPLOCATION("SWA:5,6,7,8") + PORT_DIPSETTING(0x00,"USA 1") + PORT_DIPSETTING(0x10,"France 1") + PORT_DIPSETTING(0x20,"Germany") + PORT_DIPSETTING(0x30,"France 2") + PORT_DIPSETTING(0x40,"Unknown 1") + PORT_DIPSETTING(0x50,"Unknown 2") + PORT_DIPSETTING(0x60,"Unknown 3") + PORT_DIPSETTING(0x70,"Unknown 4") + PORT_DIPSETTING(0x80,"Export 1") + PORT_DIPSETTING(0x90,"France 3") + PORT_DIPSETTING(0xa0,"Export 2") + PORT_DIPSETTING(0xb0,"France 4") + PORT_DIPSETTING(0xc0,"UK") + PORT_DIPSETTING(0xd0,"Europe") + PORT_DIPSETTING(0xe0,"Spain") + PORT_DIPSETTING(0xf0,"USA 2") INPUT_PORTS_END +void wpc_dot_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) +{ + switch(id) + { + case TIMER_VBLANK: + if((m_vblank_count % 4) == (m_wpc->get_dmd_firq_line()*4/32)) + { + m_maincpu->set_input_line(M6809_FIRQ_LINE,ASSERT_LINE); + m_wpc->set_dmd_firq(); + } + m_vblank_count++; + break; + case TIMER_IRQ: + m_maincpu->set_input_line(M6809_IRQ_LINE,ASSERT_LINE); + break; + } +} + void wpc_dot_state::machine_reset() { + m_cpubank->set_entry(0); + m_vblank_count = 0; + m_irq_count = 0; } DRIVER_INIT_MEMBER(wpc_dot_state,wpc_dot) { + UINT8 *fixed = memregion("code")->base(); + UINT32 codeoff = memregion("code")->bytes() - 0x8000; + m_cpubank->configure_entries(0, 32, &fixed[0], 0x4000); + m_cpubank->set_entry(0); + m_fixedbank->configure_entries(0, 1, &fixed[codeoff],0x8000); + m_fixedbank->set_entry(0); + m_dmdbank1->configure_entries(0, 16, &m_dmdram[0x0000],0x200); + m_dmdbank1->set_entry(0); + m_dmdbank2->configure_entries(0, 16, &m_dmdram[0x0000],0x200); + m_dmdbank2->set_entry(1); + m_dmdbank3->configure_entries(0, 16, &m_dmdram[0x0000],0x200); + m_dmdbank3->set_entry(2); + m_dmdbank4->configure_entries(0, 16, &m_dmdram[0x0000],0x200); + m_dmdbank4->set_entry(3); + m_dmdbank5->configure_entries(0, 16, &m_dmdram[0x0000],0x200); + m_dmdbank5->set_entry(4); + m_dmdbank6->configure_entries(0, 16, &m_dmdram[0x0000],0x200); + m_dmdbank6->set_entry(5); + m_vblank_timer = timer_alloc(TIMER_VBLANK); + m_vblank_timer->adjust(attotime::from_hz(60),0,attotime::from_hz(60)); + m_irq_timer = timer_alloc(TIMER_IRQ); + m_irq_timer->adjust(attotime::from_hz(976),0,attotime::from_hz(976)); + m_bankmask = (memregion("code")->bytes() >> 14) - 1; + logerror("WPC: ROM bank mask = %02x\n",m_bankmask); + memset(m_ram,0,0x3000); + save_pointer(m_dmdram,"DMD RAM",0x2000); +} + +READ8_MEMBER(wpc_dot_state::ram_r) +{ + return m_ram[offset]; +} + +WRITE8_MEMBER(wpc_dot_state::ram_w) +{ + if((!m_wpc->memprotect_active()) || ((offset & m_wpc->get_memprotect_mask()) != m_wpc->get_memprotect_mask())) + m_ram[offset] = data; + else + logerror("WPC: Memory protection violation at 0x%04x (mask=0x%04x)\n",offset,m_wpc->get_memprotect_mask()); +} + +WRITE8_MEMBER(wpc_dot_state::wpc_rombank_w) +{ + m_cpubank->set_entry(data & m_bankmask); +} + +WRITE8_MEMBER(wpc_dot_state::wpc_dmdbank_w) +{ + UINT8 page = offset >> 4; + + switch(offset & 0x07) + { + case 0: + m_dmdbank1->set_entry(data + (page*16)); + break; + case 1: + m_dmdbank2->set_entry(data + (page*16)); + break; + case 2: + m_dmdbank3->set_entry(data + (page*16)); + break; + case 3: + m_dmdbank4->set_entry(data + (page*16)); + break; + case 4: + m_dmdbank5->set_entry(data + (page*16)); + break; + case 5: + m_dmdbank6->set_entry(data + (page*16)); + break; + } +} + +WRITE_LINE_MEMBER(wpc_dot_state::wpcsnd_reply_w) +{ + if(state) + { + m_maincpu->set_input_line(M6809_FIRQ_LINE,ASSERT_LINE); + m_wpc->set_snd_firq(); + } +} + +WRITE_LINE_MEMBER(wpc_dot_state::wpc_irq_w) +{ + m_maincpu->set_input_line(M6809_IRQ_LINE,CLEAR_LINE); +} + +WRITE_LINE_MEMBER(wpc_dot_state::wpc_firq_w) +{ + m_maincpu->set_input_line(M6809_FIRQ_LINE,CLEAR_LINE); +} + +READ8_MEMBER(wpc_dot_state::wpc_sound_ctrl_r) +{ + return m_wpcsnd->ctrl_r(); // ack FIRQ? +} + +WRITE8_MEMBER(wpc_dot_state::wpc_sound_ctrl_w) +{ + m_wpcsnd->ctrl_w(data); +} + +READ8_MEMBER(wpc_dot_state::wpc_sound_data_r) +{ + return m_wpcsnd->data_r(); +} + +WRITE8_MEMBER(wpc_dot_state::wpc_sound_data_w) +{ + m_wpcsnd->data_w(data); +} + +UINT32 wpc_dot_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + UINT8 x,y,bit; + UINT32 offset = (m_wpc->get_visible_page() * 0x200); + UINT32 col; + + for(y=0;y<32;y++) // scanline + { + for(x=0;x<128;x+=8) // column + { + for(bit=0;bit<8;bit++) // bits + { + if(m_dmdram[offset] & (1<adjust(attotime::from_hz(120),0,attotime::from_hz(120)); @@ -43,6 +45,8 @@ void wpc_device::device_start() void wpc_device::device_reset() { m_memprotect = 0; + m_dmd_irqsrc = false; + m_snd_irqsrc = false; } void wpc_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) @@ -62,6 +66,10 @@ READ8_MEMBER(wpc_device::read) switch(offset) { + case DMD_FIRQLINE: + if(m_dmd_irqsrc) + ret |= 0x80; + break; case WPC_WATCHDOG: if(m_zerocross) { @@ -94,7 +102,8 @@ READ8_MEMBER(wpc_device::read) ret = m_soundctrl_r(space,0); break; case WPC_FIRQSRC: - ret = 0x80; // always 0x80 since there is no DMD + if(m_snd_irqsrc) + ret |= 0x80; break; case WPC_SHIFTADRH: ret = m_shift_addr_high + ((m_shift_addr_low + (m_shift_bit1 >> 3)) >> 8); @@ -119,6 +128,33 @@ WRITE8_MEMBER(wpc_device::write) { switch(offset) { + case DMD_PAGE3000: + m_dmdbank_w(space,0,data & 0x0f); + break; + case DMD_PAGE3200: + m_dmdbank_w(space,1,data & 0x0f); + break; + case DMD_PAGE3400: + m_dmdbank_w(space,2,data & 0x0f); + break; + case DMD_PAGE3600: + m_dmdbank_w(space,3,data & 0x0f); + break; + case DMD_PAGE3800: + m_dmdbank_w(space,4,data & 0x0f); + break; + case DMD_PAGE3A00: + m_dmdbank_w(space,5,data & 0x0f); + break; + case DMD_FIRQLINE: + m_firq_cb(space,0); + m_dmd_irqsrc = false; + m_dmd_irqline = data; + break; + case DMD_VISIBLEPAGE: + m_dmd_visiblepage = data; + if(LOG_WPC) logerror("WPC: DMD Visible page set to %i\n",data); + break; case WPC_ROMBANK: m_bank_w(space,0,data); if(LOG_WPC) logerror("WPC: ROM bank set to %02x\n",data); @@ -163,6 +199,7 @@ WRITE8_MEMBER(wpc_device::write) break; case WPC_FIRQSRC: m_firq_cb(space,0); + m_snd_irqsrc = false; break; case WPC_PROTMEMCTRL: if(m_memprotect == 0xb4) diff --git a/src/mame/machine/wpc.h b/src/mame/machine/wpc.h index 3d214647f84..f296c18dff8 100644 --- a/src/mame/machine/wpc.h +++ b/src/mame/machine/wpc.h @@ -17,6 +17,15 @@ * 9 = WPC-95 */ /* AMFDS9 */ +/* DMD */ +#define DMD_PAGE3200 (0x08) +#define DMD_PAGE3000 (0x09) +#define DMD_PAGE3600 (0x0a) +#define DMD_PAGE3400 (0x0b) +#define DMD_PAGE3A00 (0x0c) +#define DMD_FIRQLINE (0x0d) +#define DMD_PAGE3800 (0x0e) +#define DMD_VISIBLEPAGE (0x0f) /* Printer board */ #define WPC_PRINTBUSY (0x10) /* xxxxx R: Printer ready ??? */ #define WPC_PRINTDATA (0x11) /* xxxxx W: send to printer */ @@ -80,6 +89,9 @@ #define MCFG_WPC_ROMBANK(_bank_w) \ downcast(device)->set_bank_write(DEVCB2_##_bank_w); +#define MCFG_WPC_DMDBANK(_dmdbank_w) \ + downcast(device)->set_dmdbank_write(DEVCB2_##_dmdbank_w); + class wpc_device : public device_t { public: @@ -92,6 +104,10 @@ public: bool memprotect_active() { if(m_memprotect == 0xb4) return false; else return true; } UINT16 get_alphanumeric(UINT8 offset) { if(offset < 40) return m_alpha_data[offset]; else return 0; } void reset_alphanumeric() { memset(m_alpha_data,0,40*2); } + UINT8 get_visible_page() { return m_dmd_visiblepage; } + UINT8 get_dmd_firq_line() { return m_dmd_irqline; } + void set_dmd_firq() { m_dmd_irqsrc = true; } + void set_snd_firq() { m_snd_irqsrc = true; } // callbacks template void set_irq_callback(_irq irq) { m_irq_cb.set_callback(irq); } @@ -102,6 +118,7 @@ public: template void set_sound_ctrl_write(_soundctrl_w soundctrl_w) { m_soundctrl_w.set_callback(soundctrl_w); } template void set_sound_s11_write(_sounds11 sounds11) { m_sounds11_w.set_callback(sounds11); } template void set_bank_write(_bank_w bank_w) { m_bank_w.set_callback(bank_w); } + template void set_dmdbank_write(_dmdbank_w dmdbank_w) { m_dmdbank_w.set_callback(dmdbank_w); } virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr); static const device_timer_id TIMER_IRQ = 1; @@ -123,7 +140,10 @@ private: UINT16 m_alpha_data[40]; bool m_zerocross; UINT32 m_irq_count; - emu_timer* m_irq_timer; + UINT8 m_dmd_visiblepage; + bool m_dmd_irqsrc; + bool m_snd_irqsrc; + UINT8 m_dmd_irqline; emu_timer* m_zc_timer; devcb2_write_line m_irq_cb; @@ -134,6 +154,7 @@ private: devcb2_write8 m_soundctrl_w; devcb2_write8 m_sounds11_w; devcb2_write8 m_bank_w; + devcb2_write8 m_dmdbank_w; }; extern const device_type WPCASIC;